DE102005053494A1 - Verfahren zum Herstellen elektrisch leitender Durchführungen durch nicht- oder halbleitende Substrate - Google Patents

Verfahren zum Herstellen elektrisch leitender Durchführungen durch nicht- oder halbleitende Substrate Download PDF

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Publication number
DE102005053494A1
DE102005053494A1 DE102005053494A DE102005053494A DE102005053494A1 DE 102005053494 A1 DE102005053494 A1 DE 102005053494A1 DE 102005053494 A DE102005053494 A DE 102005053494A DE 102005053494 A DE102005053494 A DE 102005053494A DE 102005053494 A1 DE102005053494 A1 DE 102005053494A1
Authority
DE
Germany
Prior art keywords
electrically conductive
conductive
substrate
feedthroughs
semiconductive substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE102005053494A
Other languages
German (de)
English (en)
Inventor
Wolfgang Reinert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Priority to DE102005053494A priority Critical patent/DE102005053494A1/de
Priority to EP06807782.5A priority patent/EP1946367B1/de
Priority to JP2008539431A priority patent/JP2009515348A/ja
Priority to US12/093,089 priority patent/US7781331B2/en
Priority to PCT/EP2006/068247 priority patent/WO2007054521A1/de
Publication of DE102005053494A1 publication Critical patent/DE102005053494A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
DE102005053494A 2005-11-09 2005-11-09 Verfahren zum Herstellen elektrisch leitender Durchführungen durch nicht- oder halbleitende Substrate Ceased DE102005053494A1 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE102005053494A DE102005053494A1 (de) 2005-11-09 2005-11-09 Verfahren zum Herstellen elektrisch leitender Durchführungen durch nicht- oder halbleitende Substrate
EP06807782.5A EP1946367B1 (de) 2005-11-09 2006-11-08 Verfahren zum herstellen elektrisch leitender durchführungen durch nicht- oder halbleitende substrate
JP2008539431A JP2009515348A (ja) 2005-11-09 2006-11-08 非導電性または半導電性の基板に導電性ブッシングを製作する方法
US12/093,089 US7781331B2 (en) 2005-11-09 2006-11-08 Method for producing electrically conductive bushings through non-conductive or semiconductive substrates
PCT/EP2006/068247 WO2007054521A1 (de) 2005-11-09 2006-11-08 Verfahren zum herstellen elektrisch leitender durchführungen durch nicht- oder halbleitende substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102005053494A DE102005053494A1 (de) 2005-11-09 2005-11-09 Verfahren zum Herstellen elektrisch leitender Durchführungen durch nicht- oder halbleitende Substrate

Publications (1)

Publication Number Publication Date
DE102005053494A1 true DE102005053494A1 (de) 2007-05-16

Family

ID=37651073

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102005053494A Ceased DE102005053494A1 (de) 2005-11-09 2005-11-09 Verfahren zum Herstellen elektrisch leitender Durchführungen durch nicht- oder halbleitende Substrate

Country Status (5)

Country Link
US (1) US7781331B2 (https=)
EP (1) EP1946367B1 (https=)
JP (1) JP2009515348A (https=)
DE (1) DE102005053494A1 (https=)
WO (1) WO2007054521A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008031836A1 (de) * 2008-07-05 2010-01-21 Deutsche Cell Gmbh Lotkontakt
DE102023101372B3 (de) 2023-01-20 2024-03-28 Audi Aktiengesellschaft Elektronikanordnung, Kraftfahrzeug und Verfahren zum elektrischen Verbinden

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5298559B2 (ja) * 2007-06-29 2013-09-25 富士通株式会社 半導体装置及びその製造方法
JP2009021433A (ja) * 2007-07-12 2009-01-29 Fujikura Ltd 配線基板及びその製造方法
JP4713602B2 (ja) * 2008-02-21 2011-06-29 パナソニック株式会社 基板モジュールおよびその製造方法ならびに電子機器
US7973416B2 (en) * 2008-05-12 2011-07-05 Texas Instruments Incorporated Thru silicon enabled die stacking scheme
JP5351164B2 (ja) * 2008-07-28 2013-11-27 株式会社アドバンテスト 半導体装置、プローブウエハおよび製造方法
JP2010251558A (ja) * 2009-04-16 2010-11-04 Toshiba Corp 固体撮像装置
FR2951017A1 (fr) * 2009-10-05 2011-04-08 St Microelectronics Crolles 2 Via de connexion electrique pour substrat de dispositif semi-conducteur
FR2951018A1 (fr) * 2009-10-05 2011-04-08 St Microelectronics Crolles 2 Via de connexion electrique pour substrat de dispositif semi-conducteur
JP2011187754A (ja) * 2010-03-10 2011-09-22 Toshiba Corp 固体撮像装置及びその製造方法
US8946083B2 (en) * 2011-06-24 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ formation of silicon and tantalum containing barrier
TW201401396A (zh) * 2012-05-25 2014-01-01 村田製作所股份有限公司 半導體裝置
US20150243597A1 (en) * 2014-02-25 2015-08-27 Inotera Memories, Inc. Semiconductor device capable of suppressing warping
US9601354B2 (en) * 2014-08-27 2017-03-21 Nxp Usa, Inc. Semiconductor manufacturing for forming bond pads and seal rings
WO2019132332A1 (ko) 2017-12-26 2019-07-04 주식회사 포스코 리튬 이차 전지용 양극 활물질, 이의 제조 방법, 및 이를 포함하는 리튬 이차 전지

Citations (3)

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US4897708A (en) * 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array
US20010028113A1 (en) * 1997-04-24 2001-10-11 Katsuya Kosaki Method of manufacturing semiconductor device
US6903442B2 (en) * 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts

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US4726879A (en) * 1986-09-08 1988-02-23 International Business Machines Corporation RIE process for etching silicon isolation trenches and polycides with vertical surfaces
JPH04174539A (ja) * 1990-11-07 1992-06-22 Oki Electric Ind Co Ltd 半導体装置
US5910687A (en) * 1997-01-24 1999-06-08 Chipscale, Inc. Wafer fabrication of die-bottom contacts for electronic devices
DE69737262T2 (de) * 1997-11-26 2007-11-08 Stmicroelectronics S.R.L., Agrate Brianza Herstellungsverfahren für einen Vorder-Hinterseiten-Durchkontakt in mikro-integrierten Schaltungen
US6300670B1 (en) * 1999-07-26 2001-10-09 Stmicroelectronics, Inc. Backside bus vias
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JP3879816B2 (ja) * 2000-06-02 2007-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
JP2003332417A (ja) * 2002-05-08 2003-11-21 Toshiba Corp 半導体チップの製造方法
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JP2004095849A (ja) * 2002-08-30 2004-03-25 Fujikura Ltd 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法
DE10244077B4 (de) 2002-09-06 2007-03-15 INSTITUT FüR MIKROTECHNIK MAINZ GMBH Verfahren zur Herstellung von Halbleiterbauteilen mit Durchkontaktierung
JP4145301B2 (ja) 2003-01-15 2008-09-03 富士通株式会社 半導体装置及び三次元実装半導体装置
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Publication number Priority date Publication date Assignee Title
US4897708A (en) * 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array
US20010028113A1 (en) * 1997-04-24 2001-10-11 Katsuya Kosaki Method of manufacturing semiconductor device
US6903442B2 (en) * 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008031836A1 (de) * 2008-07-05 2010-01-21 Deutsche Cell Gmbh Lotkontakt
DE102023101372B3 (de) 2023-01-20 2024-03-28 Audi Aktiengesellschaft Elektronikanordnung, Kraftfahrzeug und Verfahren zum elektrischen Verbinden

Also Published As

Publication number Publication date
EP1946367A1 (de) 2008-07-23
EP1946367B1 (de) 2016-10-26
US7781331B2 (en) 2010-08-24
JP2009515348A (ja) 2009-04-09
WO2007054521A1 (de) 2007-05-18
US20080233740A1 (en) 2008-09-25

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