Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/4985—Flexible insulating substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
  • H01L21/4814—Conductive parts
  • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/0011—Working of insulating substrates or insulating layers
  • H05K3/0017—Etching of the substrate by chemical or physical means
  • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0266—Marks, test patterns or identification means
  • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/03—Use of materials for the substrate
  • H05K1/0393—Flexible materials
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/01—Dielectrics
  • H05K2201/0104—Properties and characteristics in general
  • H05K2201/0108—Transparent
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/01—Dielectrics
  • H05K2201/0183—Dielectric layers
  • H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/03—Conductive materials
  • H05K2201/0332—Structure of the conductor
  • H05K2201/0335—Layered conductors or foils
  • H05K2201/0355—Metal foils
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
  • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
  • H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
  • H05K2203/0759—Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer

Definitions

• COF substrate laminate method for producing the same, and COF film carrier tape formed using this COF substrate laminate
• the present invention relates to a laminate for a flexible printed circuit board used as a CF application and a method for producing the same.
• TAB method tape automated bonding in which a driver IC is mounted on a tape carrier is widely used in the electronics industry that uses liquid crystal display elements (LCD).
• LCD liquid crystal display elements
• COF chip 'on' film
• COF chip 'on' film
• the flexible printed circuit board (FPC) used in this COF does not have the device holes used in the TAB method, when measuring the relative position when mounting the chip, the driver IC chip is transmitted through the insulating layer. It is necessary to recognize the wiring. In particular, in the flexible printed circuit board (FPC) used in this COF, the wiring pitch is becoming narrower and it is necessary to be able to perform fine processing.
• a laminate used for such an FPC for COF there is a laminate in which an adhesion reinforcing layer such as nickel is sputtered on an insulating film such as a polyimide film and then copper plating is applied.
• the polyimide film is relatively transparent, so that it is easy to align when mounting ICs, and the adhesion between the conductor and the insulating layer is weakened. If the mouth migration is inferior, there is a problem.
• a casting type in which a polyimide film is laminated on a copper foil by a coating method, or a thermoplastic resin or a thermosetting resin on the copper foil is used.
• thermocompression bonding type in which an insulating film is thermocompression bonded.
• Japanese Patent Application Laid-Open No. 2003-23046 has a structure in which a conductor layer and an insulating layer are laminated, and the surface roughness of the surface of the conductor layer in contact with the insulating layer is 0.1 to 1.8 xm.
• the body is disclosed.
• the above-mentioned laminated body can solve the problem of recognizing the wiring of the driver IC chip through the insulating layer to some extent, it can be used as a high-density substrate material that requires a pitch of 30 ⁇ m or less, for example. Is not always satisfactory.
• JP 2004-142183 A describes a laminate in which the surface roughness of the surface in contact with the insulating layer is 1.0 zm or less and the surface roughness force of the back surface is 3 ⁇ 4.0 xm or less.
• the surface roughness of the surface that is not in contact with the insulating layer is large, unevenness in thickness occurs during resist formation, and the subsequent linear circuit patterning process improves the linearity of the circuit. It was difficult.
• the conductor even when the conductor is thick, it is difficult to ensure the linearity of the circuit, and in particular, fine processing with a pitch of 30 / im or less is difficult. That is, a laminate that can satisfy the requirements for fine processing with appropriate roughness on the insulating layer side and roughness on the resist surface side has been strong.
• Patent Document 1 Japanese Patent Laid-Open No. 2003-23046
• Patent Document 2 JP 2004-142183 A
• An object of the present invention is to provide a laminate capable of being finely processed, for example, having a pitch of 30 / m or less, and a manufacturing method thereof.
• the conductor forming the multilayer body has a predetermined thickness, and the surface of the surface of the conductor that is in direct contact with the insulating layer
• the roughness Rz should be 1.0 ⁇ m or less, and the surface roughness Rz should be 1.0 ⁇ m or less in contact with the insulating layer.
• the surface roughness Rz represents “10-point average roughness” and is measured according to JIS B 0601.
• the present invention is a COF substrate laminate in which an insulating layer made of an insulating resin is formed on one surface of a conductor made of a conductive metal foil, wherein the conductor has a thickness of 1 to 8 ⁇ m. m, the surface roughness Rz of the surface in contact with the insulating layer of the conductor is 1.0 xm or less, and the surface roughness Rz of the surface not in contact with the insulating layer of the conductor is 1.0 ⁇ or less, C ⁇ It is a laminate for F substrates.
• the present invention also provides a method for manufacturing a laminate for a COF substrate in which an insulating layer made of an insulating resin is formed on one surface of a conductor, and has a thickness of at least 10 zm and has one surface.
• the thickness of the conductive metal foil is formed by forming an insulating layer on the surface of the conductive metal foil having a surface roughness Rz of 1.0 xm or less and chemically polishing the surface of the conductive metal foil not in contact with the insulating layer. 1 to 8 ⁇ m, and a conductor is formed with a surface roughness Rz of 1.0 ⁇ m or less.
• the driver IC chip wiring can be recognized through the insulating layer. Further, when the surface roughness Rz of the conductor that is not in direct contact with the insulating layer is 1.0 ⁇ or less, when a high-density wiring is required, for example, processing of 30 ⁇ pitch or less is possible.
• the surface roughness Rz of the conductor that is in direct contact with the insulating layer has a lower limit of 0.3 ⁇ m for ensuring the adhesion to the insulating layer, and the surface roughness of the conductor that is not in direct contact with the insulating layer.
• Rz has a lower limit of 0.1 ⁇ m in order to ensure adhesion with an insulating protective film to be laminated later.
• Examples of the conductor made of the conductive metal foil in the present invention include a copper foil made of copper or a copper alloy, as well as a metal foil made of gold, silver, etc., preferably a copper foil. Good.
• Examples of the copper foil include rolled copper foil, electrolytic copper foil, and the like, and an electrolytic copper foil that can reduce the risk of mixing an oxide as an insulator as much as possible is more preferable.
• the thickness of the conductor is 1 to 8 ⁇ m. If the thickness of the conductor is smaller than 1 ⁇ m, it is difficult to control the thickness during the chemical polishing process and sufficient reliability cannot be obtained. On the other hand, if it is larger than 8 xm, it becomes very difficult to obtain the linearity of the conductor, for example, when machining at 30 zm pitch. The invention's effect
• the wiring of the driver IC chip can be recognized through the insulating layer, and the adhesive force between the conductor and the insulating layer is high.
• the adhesive force between the conductor and the insulating layer is high.
• the electrolytic copper foil having a surface roughness Rz of 1.0 zm or less on the surface on which an insulating layer is to be provided later is used. This is because, as described above, when the insulating layer is formed on this surface and the conductor is removed, the wiring of the driver IC chip can be recognized through the insulating layer.
• Rz is preferably 0.3 zm or more.
• the thickness of the conductor in the finally obtained laminate is l to 8 xm.
• the thickness of this electrolytic copper foil is about 10 xm or more thick as the copper foil to be prepared because chemical polishing will be described later. It is preferable to use one having a thickness of 12 to 18 ⁇ m.
• the insulating layer forming the laminate is formed from an insulating film having a thermosetting resin layer, which may be formed from an insulating film having a thermoplastic resin layer, for example. There may be. Alternatively, a polyimide precursor resin solution may be applied to the conductor, and the polyimide precursor resin solution may be dried and cured. Of these, the insulating layer is preferably formed by applying a polyimide precursor resin solution to the conductor and then drying and curing.
• diamines used include 4,4'-diaminodiphenyl ether, 2'-methoxy 4,4'-diaminobenzanilide, 1,4 bis (4 aminophenoxy) benzene, 1 , 3 Bis (4 aminophenoxy) benzene, 2,2'-bis [4— (4 aminophenoxy) phenyl] pro Bread, 2,2′-dimethyl-4,4′-diaminobiphenyl, 3,3′-dihydroxy-4,4′-diaminobiphenyl, 4,4′-diaminobenzanilide and the like.
• Examples of the acid anhydride include pyromellitic anhydride, 3,3 ′, 4,4′-biphenyltetracarboxylic dianhydride, 3,3 ′, 4,4′-diphenylsulfonetetracarboxylic acid Examples include dianhydrides and water-free 4,4'-oxydiphthalic acid.
• diamine and acid anhydride can be used alone or in combination of two or more.
• Examples of the solvent include dimethylacetamide, n_methylpyrrolidinone, 2-butanone, diglyme, xylene, and the like, and they can be used alone or in combination of two or more.
• the polyimide precursor resin solution preferably has a polymerized resin viscosity in the range of 500 cps to 35,000 cps, preferably applied directly to one side of the conductor in the precursor state.
• the applied resin solution must be heat-treated. For this heat treatment, for example, heat treatment is performed at 100 ° C to 150 ° C for 2 to 4 minutes in the atmosphere, and then heated from room temperature to 340 ° C by vacuum heating. It's better to heat up and bring it back to room temperature for about 9 hours.
• the insulating layer made of the polyimide resin thus formed may be formed of only a single layer of the polyimide resin layer or a plurality of layers.
• the polyimide resin layer is formed from a plurality of layers, other polyimide resins made of different components may be sequentially applied on the polyimide resin layer.
• the polyimide resin layer is composed of three or more layers, the polyimide resin composed of the same component may be used twice or more.
• the thickness of the conductor is reduced to 1 to 8 ⁇ by chemically polishing the surface of the conductor that is not in direct contact with the insulating layer.
• the surface roughness Rz of the surface should be 1.0 / im or less.
• the surface roughness of the copper foil varies depending on the conditions of chemical polishing. In the present invention, the copper foil of the desired laminate is adjusted by adjusting the polishing conditions such as the known polishing temperature and polishing rate. The surface roughness can be adjusted.
• the polishing liquid is a hydrogen peroxide Z sulfuric acid system containing hydrogen peroxide and sulfuric acid as main components.
• the concentration of hydrogen peroxide is in the range of 70 to 85 g / L, and the concentration of sulfuric acid is in the range of 18 to 22 g / L. If the concentration range is not within the above range, precise control of the surface roughness tends to be difficult.
• the polishing temperature is 20-50 Keep it constant at any temperature of ° C.
• the insulating layer is formed by applying a polyimide resin on the electrolytic copper foil.
• an insulating layer is formed by laminating one or more polyimide films on the electrolytic copper foil, Thereafter, chemical polishing as described above may be performed.
• the laminate thus produced may be a single-sided copper-clad laminate having an electrolytic copper foil only on one side of the insulating layer, or a double-sided copper-clad laminate having an electrolytic copper foil on both sides of the insulating layer.
• double-sided copper-clad laminates after forming a single-sided copper-clad laminate, a method of crimping electrolytic copper foil by hot pressing, a method of sandwiching a polyimide film between two electrolytic copper foils, and crimping by hot pressing, etc. Can be mentioned.
• the surface roughness Rz of the surface of the electrolytic copper foil that is not in direct contact with the insulating layer is set to 1.0 zm or less, and the thickness of the electrolytic copper foil is in the range of 1 to 8 xm. So that chemical polishing is performed.
• the surface roughness Rz of the electrolytic copper foil that is not in direct contact with the insulating layer is desirably 0.1 ⁇ m or more from the viewpoint of ensuring adhesion with the insulating protective film on which the rear force is also laminated.
• Copper foil 1 Electrolytic copper foil Insulation layer side Rz0.7 ⁇ m, resist side Rz2.0 ⁇ m
• Copper foil 2 Electrolytic copper foil Insulation layer side Rzl.6 ⁇ m, resist side Rzl.5 ⁇ m
• Copper foil 3 Electrolytic copper foil Insulation layer side Rz2.5 ⁇ m, resist side Rzl.5 ⁇ m
• Copper foil 4 Electrolytic copper foil Insulation layer side Rz0.8 ⁇ m, resist side Rzl.O ⁇ m
• ⁇ -methylpyrrolidinone was placed in a reaction vessel equipped with a thermocouple and a stirrer and capable of introducing nitrogen. After immersing this reaction vessel in ice water contained in the vessel, pyromellitic anhydride (PMDA) was added to the reaction vessel, and then 4,4-diaminodiphenyl ether, (DAPE) and 2, -methoxy- 4,4,-Gaminobensanilide ( ⁇ ) was introduced.
• the total amount of monomer input is At 15 wt%, the molar ratio of each diamine (MABA: DAPE) was 3 ⁇ 40: 40, and the molar ratio of acid anhydride to diamine was 0.98: 1.0.
• N-methylpyrrolidinone was placed in a reaction vessel equipped with a thermocouple and a stirrer and capable of introducing nitrogen. After immersing this reaction vessel in ice water contained in the vessel, PMDA / 3, 3, 4, 4, 4-biphenyltetracarboxylic dianhydride (BTDA) is charged into the reaction vessel, and then 4, 4, -Diaminodiphenyl ether (DAPE) was added. The total amount of monomers charged was 15 wt%, and the molar ratio of acid anhydride to diamine was 1.03: 1.0. Thereafter, stirring was further continued, and the reaction vessel was removed from the ice water when the temperature in the reaction vessel was in the range of room temperature to ⁇ 5 ° C. Stirring was continued for 3 hours at room temperature, and the resulting polyamic acid solution viscosity was 3,200 cps.
• BTDA 4-biphenyltetracarboxylic dianhydride
• DAPE -Diaminodiphenyl
• N-methylpyrrolidinone was placed in a reaction vessel equipped with a thermocouple and a stirrer and capable of introducing nitrogen. After immersing this reaction vessel in ice water contained in the vessel, 3,3 '4,4'-diphenylsulfone tetracarboxylic dianhydride (DSDA) and PMDA were added to the reaction vessel, and then 1,3- Bis (4-aminophenoxy) benzene (TPE-R) was added. The total amount of monomers charged was 15 wt%, the molar ratio of each acid anhydride (DSDA: PMDA) was 3 ⁇ 40: 10, and the molar ratio of acid anhydride to diamine was 1.03: 1.0.
• DSDA 3,3 '4,4'-diphenylsulfone tetracarboxylic dianhydride
• TPE-R 1,3- Bis (4-aminophenoxy) benzene
• a wiring pattern was formed on the COF substrate laminate obtained above to obtain a COF film carrier tape.
• the linearity of the circuit is visually confirmed with a laser microscope with a magnification of 50 times, and the line width is uneven. If the condition was observed, it was determined as NG.
• an IC with gold bumps was mounted on the inner lead of the COF film carrier tape.
• Flip chip bonder “TFC_2100” manufactured by Shibaura Mechatronics Co., Ltd. is used for mounting. Bond head head temperature is 100 ° C, stage temperature is 420 ° C, and bonding pressure is 20gf per bump. It was done like that.
• the polyamic acid solution of Synthesis Example 1 was dried by a roll coater to a thickness of 2.0 ⁇ m. And then dried at 150 ° C for 2 minutes, and the other surface is coated with the polyamic acid solution of Synthesis Example 2 using a roll coater so that the thickness force after drying is 3 ⁇ 4.0 xm. 70. 140 minutes after drying for 5 minutes at C and 5 minutes at 110 ° C. C2 minutes, 180.
• the side coated with the polyamic acid solution of Synthesis Example 1 is a non-thermoplastic polyimide resin layer, and the polyamic acid solution of Synthesis Example 2 is applied A polyimide insulating film having a heat-resistant polyimide resin layer on the finished side was obtained.
• a roll laminator covered with silicon rubber was used by superimposing the surface of the insulating film obtained above on the side of the thermoplastic polyimide resin layer and the surface of the copper foil 4 on the side of the insulating layer.
• the copper foil 4 and the above insulating film were bonded together under the conditions of 240 ° C. and pressure 1.5 MPa.
• annealing was performed in a batch type autoclave at a temperature of 340 ° C. for 4 hours under a nitrogen atmosphere to obtain a laminate.
• the obtained laminate was chemically polished in the same manner as in Example 1.
• COF substrate laminate consisting of a conductor and an insulating layer, with the conductor being formed with a copper foil thickness of 8.0 ⁇ and a copper foil surface roughness Rz of 0.6 / im that is not in contact with the insulating film Got.
• This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after COF mounting were evaluated. The results are shown in Table 1.
• Example 2 Using the copper foil 2, a laminate was formed in the same manner as in Example 1, and chemical polishing was performed.
• the thickness of the conductor of the obtained laminate for COF substrate is 8.0 ⁇ m
• the surface roughness Rz of the surface in contact with the insulating layer is 1.6 ⁇ m
• the side not in contact with the insulating layer resist side
• the surface roughness Rz was 1.2 zm.
• This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after mounting the COF were evaluated. The results are shown in Table 1.
• a laminate was formed in the same manner as in Example 1 using copper foil 4. This laminated body was not subjected to chemical polishing.
• the thickness of the conductor of the obtained COF substrate laminate is 18 ⁇ m
• the surface roughness Rz of the surface on the opposite side is 0.8 ⁇ m
• the surface roughness Rz is in contact with the insulating layer
• the surface roughness Rz on the side (resist surface side) was 1.0 xm.
• This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after COF mounting were evaluated. The results are shown in Table 1.
• a laminate was produced in the same manner as in Example 1 until just before chemical polishing.
• this laminate is subjected to chemical polishing using a polishing solution having a sulfuric acid concentration of 80 g / L, a hydrogen peroxide concentration of 20 g / L, and an additive concentration of 3% so that the thickness force of the copper foil becomes 0.0 / m.
• a conductor was formed such that the surface roughness Rz of the copper foil not in contact with the polyimide resin layer was 1.6 ⁇ m, and a laminate for a COF substrate comprising a conductor and an insulating layer was obtained.
• This COF substrate laminate was mounted in the same manner as in Example 1 and evaluated for image recognition during mounting, linearity of the inner leads, and reliability after COF mounting. The results are shown in Table 1.

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• 2005
  • 2005-12-13 KR KR1020077016686A patent/KR101169829B1/ko active IP Right Grant
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