Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/11—Printed elements for providing electric connections to or between printed circuits
  • H05K1/111—Pads for surface mounting, e.g. lay-out
  • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
  • H05K1/113—Via provided in pad; Pad over filled via
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
  • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
  • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0237—High frequency adaptations
  • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
  • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/14—Structural association of two or more printed circuits
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/07—Electric details
  • H05K2201/0776—Resistance and impedance
  • H05K2201/0792—Means against parasitic impedance; Means against eddy currents
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
  • H05K2201/09718—Clearance holes
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
  • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
  • H05K2201/09809—Coaxial layout
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
  • H05K3/341—Surface mounted components
  • H05K3/3431—Leadless components
  • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/49126—Assembling bases
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Definitions

• the circuit board assembly disclosed herein relates generally to printed circuit board (PCB) technology, and more specifically to substrate configurations that minimize capacitive coupling on signal paths.
• PCB printed circuit board
• an electronic assembly 10 often includes a flip-chip bonded semiconductor device 12 mounted within a ball grid array (BGA) package 14 that in- turn, interfaces with a PCB assembly 16. While different in size and scale, both the package and the PCB assembly employ multi-layer circuit board technology.
• Multi-layer circuit boards whether large PCBs or small micro-boards, typically utilize a plurality of stacked layers 20 for efficient signal routing.
• the layers are laminated in a stacked arrangement with relative precision to preserve strict planarity specifications.
• Vias 26 formed transverse to the substrate and conductor portion enable layer-to-layer signal routing.
• the vias are electrically isolated from the conductive plane by a dielectric-filled and metallization- free area known generally as an anti-pad 28.
• the entire structure is fabricated according to design rules appropriate for the specific process. Deviating from the standard design rules for a given process often results in additional cost, and/or unexpected problems.
• One design rule governing the formation of anti-pads constrains the diameter of the anti- pad in an effort to minimize sagging, or non-planarity in the area of the anti-pad (illustrated in phantom in Figure 2B).
• circuit board structure described herein provides a unique way to enlarge anti-pad structures with minimal effects on overall board planarity. This allows for a significant reduction in capacitive coupling between signal paths and power/ground planes. As a result, optimal signal performance and fidelity is available for high- bandwidth applications.
• the circuit board structure in one form comprises a circuit board structure.
• the structure includes a fiat substrate having oppositely disposed planar surfaces and a conductor.
• the conductor is formed on at least one of the planar surfaces and defines a conductor plane.
• the structure further includes an oversized-in-diameter anti-pad formed through the substrate layer and the conductor layer.
• the anti-pad further includes a spacer formed substantially coplanar with the conductor plane.
• the circuit board structure is employed in a multi-layered circuit board assembly for routing a plurality of signal paths.
• the multi-layered circuit board assembly comprises a plurality of layers, with each layer comprising a flat substrate having oppositely disposed planar surfaces and a conductor formed on at least one of the planar surfaces.
• the conductor defines a conductor plane.
• An oversized-in-diameter anti-pad is formed through the substrate and the conductor, and includes a conductive via oriented transverse to the substrate and the conductor layer.
• the anti-pad further includes a spacer disposed substantially coplanar with the conductor plane.
• the circuit board structure is employed in a ball-grid-array package for housing at least one semiconductor device.
• the package has a contact interface adapted for interfacing to a circuit board, the contact interface comprising an array of solder ball pads disposed across an interface layer.
• the package further comprises a circuit board assembly coupled to the contact interface, the circuit board assembly including a flat substrate having oppositely disposed planar surfaces and a conductor formed on at least one of the planar surfaces.
• the conductor defines a conductor plane.
• An oversized-in-diameter anti-pad is formed through the substrate and the conductor and includes a spacer disposed substantially coplanar with the conductor plane.
• a method of manufacturing a circuit board structure comprises the steps forming a flat substrate having oppositely disposed planar surfaces; establishing an opening through the substrate transverse to the planar surfaces; filling the opening with a dielectric to form an anti- pad having an outer diameter; depositing a conductor on the substrate to form a conductor plane; and removing portions of the conductor to expose the anti-pad, the removing step further including forming electrically isolated spacers coplanar with the conductor plane within the anti pad outer diameter.
• FIG. 1 is a high level diagram, not to scale, of a ball-grid-array package mounted to a printed circuit board assembly;
• FIG. 2A is a partial transverse view of a conventional circuit board layer
• FIG. 2B is a view similar to Figure 2A, and illustrates the non-planar sagging associated with conventional anti-pads having overly expanded diameters;
• FIG. 3 is a partial transverse view of an improved circuit board structure;
• FIG. 4 is a flow chart illustrating a method of manufacturing the circuit board structure of Figure 3;
• FIG. 5 is a partial perspective view of a circuit board structure of Figure 3 applied to a printed circuit board having signal vias; and
• FIG. 6 is a partial perspective view of a circuit board structure of Figure 3 applied to a BGA package scheme with solder ball pads.
• the circuit board structure described herein provides a high performance solution for minimizing capacitive coupling acting on a signal path due to undesirably small anti-pad diameters. This is accomplished by employing a spacer in the anti-pad such that an expanded diameter may be realized with minimal deviations to overall planarity due to sag.
• an improved circuit board structure generally designated 30, comprises a substrate layer 32 and a conductor layer 34 deposited on the substrate.
• the substrate preferably takes the form of a dielectric material, such as FR-4, or , for example. Copper foil provides an acceptable conductor layer.
• a cylindrical area free of metallization and filled with a dielectric is formed transverse to the substrate layer and conductor layer to define an anti-pad 36.
• the anti-pad diameter is oversized with respect to predefined process design rules.
• design rules would typically constrain the size of the anti-pad.
• an enlarged anti-pad provides enhanced signal propagation performance.
• the anti-pad 36 is supplemented with an electrically isolated spacer 38.
• the spacer preferably takes the form of a ring, or a plurality of concentric rings (not shown) disposed at one axial end of the anti-pad, substantially coplanar with the conductor layer 34, and fabricated out of a similar electrically conductive material as that of the conductor layer.
• a dielectric fills in any gaps associated with the spacer and its positioning with respect to the conductive layer such that a flat planar surface is maintained.
• a suitable substrate is first formed, at step 50.
• An opening is then established through the substrate, at step 52, by a mechanical drilling process to define the anti-pad opening.
• the opening is then filled with dielectric, at step 54.
• the metallization or conductive layer is then deposited, at step 56, then etched, at step 58, using a masking process at the locations corresponding to the anti-pads. During this step, the isolated spacers are defined.
• Additional dielectric is then applied, at step 60, to fill the anti-pad, thereby completing the general circuit board structure. Further steps in the basic method may be performed, such as via formation, depending on the application. The process may be repeated several times, depending on the number of layers desired.
• the spacer 38 provides a rigid structure to cooperate with the dielectric and prevent sagging of the oversized-in-diameter anti-pad 36.
• the spacer comprises a conductive material matching that of the conductor layer, the design rule diameter is satisfied by the diameter dimension "d" ( Figure 3), while the effective diameter for high-performance purposes, defined by the dimension "D", is maximized.
• FIG. 5 illustrates the application, where a conductive via 70 is formed through the anti-pad defined by the opening at 72, and electrically isolated from both the conductor layer 74 and a plurality of concentric spacers 76 and 78.
• the ratio of the anti-pad diameter to the via diameter is approximately three (3).
• one of the primary purposes of this constraint is to minimize sagging (from an enlarged anti-pad) which would lead to layer- to-layer planarity problems.
• the close proximity of the via 70 to the anti-pad 72 helps reduce sagging, it also contributes to parasitic capacitive coupling, which degrades signal performance.
• parasitic capacitance acting on the signal via 70 coupled from the conductor layer 74 is greatly reduced.
• the impedance of the via structure approaches fifty (50) ohms, which is highly desirable.
• FIG. 6 illustrates an additional application for the general circuit board structure described above involving ball-grid-array (BGA) interface connections.
• BGA and microBGA packages allow for efficient electrical connections between packaged semiconductor devices and PCBs.
• the package includes solder ball pads 80 that couple to a BGA-packaged circuit board 82 through a plurality of solder balls 84 that are precisely registered with oppositely confronting solder ball pads 86 disposed on a supporting PCB assembly 88. Both the BGA-packaged circuit board and the PCB assembly have respective power/ground planes 90 and 92.
• the parallel plate capacitance between the solder ball pads 80, 86 and the respective power/ground planes 90 and 92 for both the BGA package and the PCB can be minimized. This is done by forming anti-pads proximate the solder ball pad locations at 94 and 96, thereby removing one side of the parallel plate capacitor. To minimize any sagging in the anti-pad, ring-shaped spacers 100 similar to those described in the previous examples are employed. As a result, signals propagating through the BGA package and out through the PCB retain high fidelity.
• circuit board structure disclosed herein optimally enhances signal fidelity at several levels of routing.
• An electronic assembly comprising an MCM/BGA package interface (such as that in Figure 5) mounted to a printed circuit board (such as that in Figure 4) achieves optimal performance by consistently employing the anti-pad spacer configuration throughout the assembly.
• the overall assembly is shown generally by the illustration in Figure 1.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Electromagnetism (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)
• Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (1)

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Citations (3)

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• 2004
  • 2004-09-17 US US10/817,785 patent/US7388158B2/en not_active Expired - Lifetime
• 2005
  • 2005-07-27 WO PCT/US2005/026688 patent/WO2006036282A1/en not_active Ceased
  • 2005-07-27 EP EP05777457A patent/EP1795057A1/en not_active Withdrawn
  • 2005-07-27 CN CN201210074096.7A patent/CN102638931B/zh not_active Expired - Lifetime
  • 2005-07-27 CN CNA2005800315532A patent/CN101044801A/zh active Pending
  • 2005-07-27 JP JP2007532322A patent/JP5172341B2/ja not_active Expired - Lifetime
  • 2005-07-27 KR KR1020077007805A patent/KR101136423B1/ko not_active Expired - Lifetime

Patent Citations (3)

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