WO2005104230A1 - 配線基板及び半導体装置並びに配線基板の製造方法 - Google Patents
配線基板及び半導体装置並びに配線基板の製造方法 Download PDFInfo
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- WO2005104230A1 WO2005104230A1 PCT/JP2005/007325 JP2005007325W WO2005104230A1 WO 2005104230 A1 WO2005104230 A1 WO 2005104230A1 JP 2005007325 W JP2005007325 W JP 2005007325W WO 2005104230 A1 WO2005104230 A1 WO 2005104230A1
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- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0314—Elastomeric connector or conductor, e.g. rubber with metallic filler
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1536—Temporarily stacked PCBs
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
Definitions
- the present invention relates to a wiring board, a semiconductor device having a semiconductor chip mounted on the wiring board, and a method for manufacturing a wiring board.
- the wiring board includes a multilayer wiring board in which a plurality of resin layers in which wirings are embedded are laminated, for example, a package board having an MLTS (Multi Layer Thin Substrate) (trade name) structure or the like.
- MLTS Multi Layer Thin Substrate
- this technique has the following problems. That is, silicon, which is the material of the semiconductor chip, and the resin that forms the wiring board have different thermal expansion coefficients. For this reason, even if the semiconductor chip is mounted on the wiring board so that no force is applied to the solder balls during mounting, when the semiconductor device is cooled to room temperature, the amount of shrinkage of the semiconductor chip and the amount of shrinkage of the wiring substrate become mutually different. Therefore, the semiconductor device is warped, and a force is applied to the solder ball. Further, when heat and cooling cycles are repeatedly applied to the semiconductor device due to heat generated by the operation of the semiconductor chip and changes in the outside air temperature, the solder balls may be broken by fatigue due to fatigue.
- Patent Document 1 discloses a technique in which an insulating material having an elastic modulus of 10 GPa or more is used as a material of a wiring board.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2002-198462 Disclosure of the invention
- the present invention has been made in view of the difficult problems, and it is an object of the present invention to provide a wiring board, a semiconductor device, and a method of manufacturing a wiring board having high connection reliability against a temperature cycle. I do.
- the wiring board according to the present invention has a wiring layer made of wiring and an insulating material, and the insulating material is a material having a Young's modulus of 1 GPa or less in a temperature range of 10 to 30 ° C.
- the wiring layer of the wiring board is formed of a relatively soft insulating material having a Young's modulus of 1 GPa or less in a temperature range of 10 to 30 ° C., so that a semiconductor chip or the like is formed on the wiring board.
- the wiring layer can follow the thermal expansion of the external device.
- the semiconductor device can be prevented from warping, and the force applied to the connection between the wiring board and the external element can be reduced. Therefore, the connection reliability of the semiconductor device with respect to the temperature cycle can be improved.
- the wiring includes conductive members such as vias and pads.
- Another wiring board according to the present invention is a wiring board in which a plurality of wiring layers made of wiring and an insulating material are laminated.
- the insulating material forming the wiring layer disposed on a surface electrically connected to an external element is a material having a Young's modulus in a temperature range of 10 to 30 ° C. of 1 GPa or less. I do.
- the material having a Young's modulus of 1 GPa or less preferably has an elongation at break of 50% or more. Thereby, the reliability of the semiconductor device is further improved.
- a semiconductor device includes the wiring board, a semiconductor chip, and a plurality of terminals interconnecting the wiring board and the semiconductor chip.
- the semiconductor device may have a plurality of other terminals connected to a surface of the wiring substrate different from the surface on which the semiconductor chip is mounted and connecting the wiring substrate to a circuit substrate.
- the insulating material forming the wiring layer disposed on the surface to which the other terminal is connected is a material having a Young's modulus in a temperature range of 10 to 30 ° C. of IGPa or less.
- the circuit board is a board such as a mother board, for example, and is different from a wiring board that forms part of the semiconductor device.
- Another semiconductor device is a semiconductor device, comprising: the wiring board, a semiconductor chip, a plurality of terminals interconnecting the wiring board and the semiconductor chip, and the semiconductor chip in the wiring board.
- a plurality of other terminals connected to a surface different from the surface on which the circuit board is mounted and connecting the wiring board to the circuit board; and the wiring arranged on the surface of the wiring substrate on the side mounted on the circuit board.
- the insulating material forming the layer is a material having a Young's modulus of IGPa or less.
- the method for manufacturing a wiring board according to the present invention includes a step of forming a wiring layer made of wiring and an insulating material on a supporting substrate, and a step of removing at least a part of the supporting substrate. It is characterized in that the insulating material is a material having a Young's modulus of IGPa or less in a temperature range of 10 to 30 ° C.
- a step of forming a reinforcing plate on the lower surface of the wiring layer may be included, or at least a part of the support substrate is removed. In this step, a part of the support substrate may be left to form a reinforcing plate.
- the wiring layer of the wiring board by forming the wiring layer of the wiring board with an insulating material having a Young's modulus of IGPa or less in a temperature range of 10 to 30 ° C., when an external element is mounted on the wiring board, in addition, since the wiring layer can follow the thermal expansion of the external element, it is possible to prevent the warpage of the wiring board and the destruction of the connection portion, and to improve the connection reliability with respect to the temperature cycle. be able to.
- FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.
- FIG. 2 is a schematic view showing features of the semiconductor device.
- FIG. 3 is a perspective view showing a semiconductor device assumed in a simulation of Test Example 1.
- FIG. 4 is a partially enlarged view of the semiconductor device shown in FIG. 3.
- (a) and (b) are perspective views showing the results of this simulation, (a) shows an example of the present invention, and (b) shows a comparative example.
- FIG. 6 is a diagram schematically illustrating an evaluation substrate manufactured in Test Example 4.
- FIG. 7 is a plan view showing the evaluation substrate in detail.
- FIG. 8 is a partially enlarged cross-sectional view of the evaluation substrate.
- FIG. 1 is a cross-sectional view showing a semiconductor device according to the present embodiment
- FIG. 2 is a schematic diagram showing features of the semiconductor device.
- the semiconductor device 1 according to the present embodiment is an FCBG A type semiconductor device.
- the semiconductor device 1 is provided with a package substrate 2.
- the package substrate 2 is formed by laminating a plurality of wiring layers. In each wiring layer, for example, a wiring 3 having copper strength and a via 4 connected to the wiring 3 are formed.
- a plurality of mounting pads 5 are formed on the uppermost wiring layer 16 of the package substrate 2 (see FIG. 2). Note that the wiring 3, the via 4, and the mounting pad 5 are also collectively referred to as wiring.
- a plurality of ball pads 6 are formed on the lower surface of the package substrate 2.
- the mounting pads 5 and the ball pads 6 are each arranged in a matrix shape as viewed from a direction perpendicular to the upper surface of the package substrate 2 (hereinafter, referred to as a plan view).
- the ball pad 6 is larger than the mounting pad 5, and the arrangement interval of the ball pad 6 is larger than the arrangement interval of the mounting pad 5.
- Each mounting pad 5 is connected to a ball pad 6 via a wiring 3 and a via 4.
- the mounting pad 5 is connected to a solder bump 7, and the ball pad 6 is connected to a BGA ball 8.
- BGA ball 8 is larger than solder bump 7.
- a semiconductor chip 9 is mounted on the node / cage substrate 2.
- the semiconductor chip 9 has, for example, a multilayer wiring layer (not shown) provided on a silicon substrate (not shown), and an integrated circuit formed on the surface of the silicon substrate and the multilayer wiring layer.
- Input / output pads are provided on the surface of the multilayer wiring layer of the semiconductor chip 9, that is, on the surface facing the package substrate 2, and each input / output pad is connected to each solder bump 7. .
- the input / output pads of the semiconductor chip 9 are connected to the mounting pads 5 via the solder bumps 7, and further connected to the BGA balls 8 via the wirings 3, vias 4 and ball pads 6.
- the underfill resin 10 is filled around the solder bumps 7 between the package substrate 2 and the semiconductor chip 9. Thereby, the semiconductor chip 9 is connected and fixed to the package substrate 2.
- a stiffener 11 having stainless or copper strength is provided! /
- the stiffener 11 is bonded to the knock substrate 2 by an adhesive layer 15.
- the shape of the stiffener 11 is frame-shaped in plan view, and the semiconductor chip 9 is housed in the opening.
- the upper surface of the stiffener 11 is substantially flush with the upper surface of the semiconductor chip 9.
- a ridge 12 that also has a ceramic force is provided on the semiconductor chip 9 and the stiffener 11, for example.
- the lid 12 is bonded to the semiconductor chip 9 by the adhesive layer 13, and is bonded to the stiffener 11 by the adhesive layer 14.
- the shape of the rim 12 is such that it substantially overlaps the package substrate 2 in plan view.
- the lid 12 functions as a heat sink for the semiconductor chip 9.
- the semiconductor device 1 is mounted on a mother board (not shown) via a BGA ball 8.
- the uppermost wiring layer of the knock substrate 2, that is, the wiring layer 16 (see FIG. 2) disposed on the surface facing the semiconductor chip 9 and having the mounting pads 5 formed thereon has a temperature of 10 ° C. It is made of an insulating material having a Young's modulus of 1 GPa or less at a temperature of 30 to 30 ° C. (hereinafter referred to as room temperature) and an elongation at break of 20% or more.
- This insulating material contains an elastomer (A, hereinafter referred to as a reactive elastomer) capable of reacting with epoxy resin, an epoxy resin (B), and a curing agent for epoxy resin (C). Is what you do.
- A elastomer
- A an elastomer capable of reacting with epoxy resin
- B epoxy resin
- C curing agent for epoxy resin
- the value of (AX 100) Z (A + B + C) is 50% by mass or more and less than 100% by mass.
- the reactive elastomer (A) is, for example, a polyamide-polybutadiene-acrylonitrile copolymer containing a phenolic hydroxyl group.
- the phenolic hydroxyl group-containing polyamide-polybutadiene acrylonitrile copolymer (hereinafter also simply referred to as a copolymer) is composed of a dicarboxylic acid having a phenolic hydroxyl group represented by the following chemical formula 1 and a phenolic hydroxyl group represented by the following chemical formula 2 Obtained by reacting a dicarboxylic acid having no, a diamine represented by the following chemical formula 3, and a polybutadiene acryl-tolyl copolymer having a carboxylic acid at both terminals represented by the following chemical formula 4: It is.
- This phenolic hydroxyl group-containing polyamide-polybutadiene-acrylonitrile copolymer is represented by the following general formula 5:
- R 1 described in Formula 1 and Formula 5 below represents a divalent aromatic compound with a carbon number of 6 to 12 having a phenolic hydroxyl group.
- Examples of the dicarboxylic acid having a phenolic hydroxyl group represented by Chemical Formula 1 include 5-hydroxyisophthalic acid, 4-hydroxyisophthalic acid, 2-hydroxyphthalic acid, 3-hydroxyphthalic acid, and 2-hydroxyterephthalic acid. No.
- R 2 described in the above Chemical Formula 2 and Chemical Formula 5 below is a divalent aromatic compound having 6 to 12 carbon atoms having no phenolic hydroxyl group or a divalent aromatic compound having 1 to 10 carbon atoms. Represents a monovalent aliphatic compound.
- Dicarboxylic acids having no phenolic hydroxyl group represented by Chemical Formula 2 include, for example, phthalic acid, isophthalic acid, terephthalic acid, Taren, succinic acid, fumaric acid, glutaric acid, adipic acid, 1,3 cyclohexanedicarbonic acid, 4,4'-diphenyldicarboxylic acid, 3,3'-methylene dibenzoic acid, etc.
- R 3 described in the above Chemical Formula 3 and Chemical Formula 5 below represents a divalent aromatic compound having 6 to 12 carbon atoms or a divalent aliphatic compound having 1 to 10 carbon atoms.
- diamines represented by the above chemical formula 3 as the diamine having a phenolic hydroxyl group, 3,3'-diamine-4,4'-dihydroxypheninolemethane, 2,2'-bis (3 amino-4-hydroxyphenyl- Hexafluoropropane, 2,2,1-bis (3 amino-4-hydroxyphenyl) difluoromethane, 3,4, diamino-1,5,1-benzenediol, 3,3, dihydroxy-1,4,4,1-dichloromethane Aminobisphenyl, 3,3,1-diamino-1,4,4-dihydroxybiphenyl, 2,2, -bis (3 amino-4hydroxyphenyl) ketone, 2,2,1-bis (3 amino-4hydroxy) (Sulfide) sulfide, 2,2,1-bis (3 amino-4
- x represents an average degree of polymerization, which is an integer of 3 to 7
- y represents an average degree of polymerization, and is an integer of 1 to 4.
- a particularly preferred copolymer is a copolymer represented by the following General Formula 6 shown below.
- the weight average molecular weight (Mw) of the copolymer is 100,000 or less, sufficient fluidity can be obtained in a temperature range of 160 to 180 ° C.
- the weight average molecular weight (Mw) is 20,000 or less, good fluidity can be obtained even in a temperature range of 100 to 160 ° C. Therefore, the weight average molecular weight (Mw) of the copolymer is preferably 100,000 or less, more preferably 20,000 or less.
- the resin (D) having a longer distance between functional groups than the phenol novolak resin contained in the epoxy resin curing agent (C) is represented by the following chemical formula 7, for example.
- R 4 in Chemical Formula 7 represents a monovalent substituent having 1 to 3 carbon atoms or hydrogen.
- al represents an integer of 1 to 4.
- al ′ represents an integer of 1 to 3.
- X represents a compound X represented by the following chemical formula 9 or a compound X represented by the following chemical formula 10.
- b is 1
- the resin (D) having a longer distance between functional groups than the phenol novolak resin represented by the above chemical formula 7 has a phenolic hydroxyl group as a functional group, for example, ethylene oxide.
- a phenolic hydroxyl group as a functional group, for example, ethylene oxide.
- An ethylene oxide compound in which the distance between the phenolic hydroxyl groups in the molecular structure is longer than the distance between the phenolic hydroxyl groups in the phenol novolak resin can be exemplified.
- An example is an ethylene oxide conjugate represented by the following chemical formula 8.
- R 4 described in the above Chemical Formula 8 represents a monovalent substituent having 1 to 3 carbon atoms, or hydrogen.
- a2 represents an integer of 1 to 4.
- a2 ' represents an integer of 1 to 3.
- X ′ represents a compound X represented by the following chemical formula 9 or a compound X represented by the following chemical formula 10.
- b ' is 1 to
- Formula R 5 described in 9 represents a monovalent substituent having 1 to 3 carbon atoms, or hydrogen.
- e represents an integer of 1 to 4.
- f represents an integer of 0 to 9.
- Formula R 6 described in 10 represents a monovalent substituent having 1 to 3 carbon atoms, or hydrogen.
- g represents an integer of 1 to 4.
- h represents an integer of 0 to 9.
- the resins represented by the above chemical formulas 7 and 8 have a longer distance between the functional groups than the phenol novolak resin represented by the following chemical formula 11.
- the epoxy resin (B) is not particularly limited, but is preferably an epoxy resin having a longer distance between functional groups than phenol novolak epoxy resin.
- Epoxy resins having a longer distance between functional groups than such phenol novolak epoxy resins include phenol biphenyl-alkyl epoxide resins, phenol xylene aralkyl epoxy resins, and phenol diphenyl ether resins.
- bisphenol A type, bisphenol F type, bisphenol S type or biphenol skeleton-containing type, and phenoxy resin having epoxy groups at both ends are listed. This phenoxy resin has a weight average molecular weight in terms of polystyrene of about 20,000 to 100,000.
- the epoxy resin (B) any of these epoxy resins may be used alone or in combination of two or more.
- epoxy resins other than the epoxy resin having a long distance between the functional groups are not particularly limited.
- glycidyl diamides of amine compounds such as diaminodiphenylmethane, diethylenetriamine and diaminodiphenylsulfone can also be used.
- epoxy resins may be used alone or as a mixture of two or more.
- the resin (D) having a longer distance between functional groups than the above-mentioned phenol novolak resin The components other than are not particularly limited.
- this component for example, bisphenol A-type phenol resin, bisphenol F-type phenol resin, bisphenol S-type phenol resin, dihydroxy ether of biphenyl isomer, naphthalene diol-type resin, phenol novola Resin, cresol novolak resin, phenol diphenyl ether aralkyl resin, naphthalene-containing novolak resin, anthracene-containing novolak resin, fluorene-containing novolak resin, bisphenol fluorene-containing novolak resin Novolac phenol resin containing bisphenol F, novolak phenol resin containing bisphenol A, phenol biphenyl triazine resin, phenol xylene triazine resin, phenol Nol triazine type resin, cre
- an amine compound such as diaminodiphenylmethane, diethylenetriamine, and diaminodiphenylsulfone may be contained in addition to the above-mentioned resin.
- phenolic resins of bisphenol A type, bisphenol F type, bisphenol S type or biphenol skeleton-containing type having one or both terminal hydroxyl groups can also be used. This phenoxy resin has a polystyrene equivalent weight average molecular weight of, for example, about 20,000 to 100,000.
- These components may be contained alone in the epoxy resin curing agent (C), or may be contained as a mixture of a plurality of types.
- the resin material of the present embodiment may contain an inorganic filler.
- the inorganic filler in the total amount of the reactive elastomer (A), the epoxy resin (B), the curing agent for the epoxy resin (C) and the inorganic filler in the present invention Is preferably 30% by mass or less.
- the mass ratio of the inorganic filler exceeds 30% by mass, the elongation at break is reduced, and the Young's modulus is increased, so that the stress relaxation property may be insufficient.
- inorganic filler known fillers can be used, for example, fused silica, crystalline silica, alumina, zircon, calcium silicate, calcium carbonate, silicon carbide, silicon nitride, boron nitride , Beryllia, talc (talc), mica (my strength), titanium oxide, zirconium, and other powders, or beads of these materials in spherical form, calcium titanate, silicon carbide, silicon nitride, Single crystal fibers such as boron nitride and alumina; metal hydrates such as aluminum hydroxide, magnesium hydroxide and zinc borate; and surfaces made of various organic substances such as epoxy resin and phenol resin. Examples of the treated metal hydrate include various metal hydrates such as magnesium hydroxide and the like, in which the metal is solid-dissolved to improve the acid resistance.
- these fillers may be used alone, or two or more thereof may be mixed.
- the resin material of the present embodiment contains a curing acceleration catalyst!
- a curing acceleration catalyst those generally used for curing epoxy resins and curing agents are used. Yes, it is not particularly limited. Examples include imidazoles, diazabicycloalkenes and derivatives thereof, tertiary amines, and the like. One of these curing accelerating catalysts may be used, or two or more of them may be used in combination.
- the resin material of the present embodiment may further include, as necessary, a flexibility imparting agent such as silicone rubber, silicone powder, acrylonitrile butadiene rubber (NBR), and indene.
- a coupling agent such as an organosilane conjugate, an organic titanate compound, or an organic aluminate conjugate may be appropriately compounded.
- an organic silane coupling agent that is, an alkoxysilane having a reactive functional group, is effective in improving the adhesiveness of the resin material according to the present embodiment and the heat resistance of the binder.
- alkoxysilane examples include aminosilane compounds such as ⁇ -aminopropyltrimethoxysilane, ⁇ -phenyl ⁇ -aminopropyltriethoxysilane, epoxysilane compounds such as silane, and y-mercaptopropyltrimethoxysilane. And ureidosilane compounds such as ⁇ -ureidopropyltriethoxysilane.
- the resin material of the present embodiment contains, as an agent for improving the adhesion between the resin material and the copper foil surface, a component used for a heat-resistant agent capable of forming a bond with the copper surface, that is, , A triazole compound, a mercapto compound other than the mercaptosilane conjugate, and a copper complex of imidazole may be added.
- Triazole compounds include 1,2,3 benzotriazole and tolyltriazole.
- Examples of mercaptoid conjugates include 2,4,6 trimercapto s-triazine, 2 di- ⁇ -butylamino-4,6 dimercapto-s triazine, and 2 varino-4,6-dimercapto-s triazine.
- Examples of the imidazole copper complex include a 2-methylimidazole copper (2) complex. One of these components may be used alone, or two or more of them may be used in combination.
- a flame retardant may be added to the resin material of the present embodiment as needed.
- These flame retardants include halogen-based flame retardants, nitrogen-based flame retardants, phosphorus-based flame retardants, and inorganic flame retardants.
- the halogen-based flame retardant include brominated bisphenol A type resin and epoxidized products thereof.
- Additive compounds among nitrogen-based flame retardants examples include melamine and isocyanuric acid conjugates.
- examples of the nitrogen-based flame retardants examples of the reactive compound include a phenol triazine type curing agent and an epoxy resin.
- the phosphorus-based flame retardant include red phosphorus, a phosphoric acid compound, an organic phosphorus compound, and the like.
- inorganic flame retardant examples include a metal hydrate, zinc molybdate, zinc stannate, zinc molybdate or zinc stannate coated on the surface of talc or silica.
- a halogen-based flame retardant when used, extremely excellent flame retardancy can be obtained by using antimony acid.
- the resin material of the present embodiment may contain a known substance other than the above as long as the reliability of a semiconductor device using the resin material is not reduced.
- it may contain a pigment, an antioxidant, an organic solvent and the like.
- a wiring layer 16 made of a resin having a Young's modulus of 1 GPa or less in a temperature range of 10 to 30 ° C. is provided on the uppermost layer.
- a semiconductor chip 9 is mounted on a package substrate 2 via a plurality of solder bumps 7. In FIG. 2, components other than those described above are not shown.
- a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIG.
- two support substrates (not shown) made of a metal material such as copper are prepared, and the two support substrates are bonded to each other.
- a Ni layer, an Au layer, a Ni layer, and a Cu layer are applied to both sides of the bonded support substrate in this order to form a multilayer film.
- the multilayer film is patterned by leaving only the portion where the mounting pad 5 is to be formed and removing the remaining portion.
- a semi-cured resin film is attached so as to embed the puttered multilayer film. After curing, this resin film is formed of an insulating material having a Young's modulus in a temperature range of 10 to 30 ° C.
- a hole is formed in the insulating layer by laser light or the like so as to reach the multilayer film, and then the inside of the hole is filled with a metal plating film to form a via 4.
- a first wiring layer in which the multilayer film and the via 4 are embedded in the insulating layer is formed on both surfaces of the two support substrates.
- a wiring 3 is formed on the first wiring layer so as to be connected to the via 4, and a semi-cured resin film is attached so as to embed the wiring 3, and heat is applied.
- the insulating layer is formed by curing.
- a via 4 is formed in the insulating layer so as to be connected to the wiring 3, and a second wiring layer in which the wiring 3 and the via 4 are buried is formed in the insulating layer.
- third and subsequent wiring layers are sequentially formed by the same steps as those for the second wiring layer.
- a ball pad 6 is formed on the last formed wiring layer by chemical plating or etching.
- the two support substrates are separated from each other.
- the supporting substrate is removed using an alkaline solution.
- the Ni layer of the multilayer film is removed using an acidic solution.
- the mounting pad 5 in which the Au layer, the Ni layer, and the Cu layer are stacked in this order is formed.
- the stiffener 11 is adhered to the surface of the knockage substrate 2 on the side where the mounting pads 5 are formed via the adhesive layer 15 to produce a “substrate with stiffener”.
- the solder bump 7 is bonded to the input / output pad (not shown) of the semiconductor chip 9 to produce the “chip with solder bump”.
- the “chip with solder bumps” is connected to the “substrate with stiffener” so that the solder bumps 7 of “chip with solder bumpers” are connected to the respective mounting pads 5 of the “substrate with stiffener”.
- an underfill resin 10 is filled between the semiconductor chip 9 and the package substrate 2 and around the semiconductor chip 9 so as to embed the solder bumps 7, and is cured by heating.
- the lid 12 is bonded to the upper surfaces of the semiconductor chip 9 and the stiffener 11, that is, the surface opposite to the surface to which the knocking substrate 2 is bonded, via adhesives 13 and 14, respectively.
- the BGA ball 8 is bonded to the ball pad 6 formed on the lower surface of the knock substrate 2.
- the semiconductor device 1 is manufactured.
- the support substrate When removing the support substrate, only the central portion of the support substrate may be removed to leave the peripheral portion in a frame shape, and the remaining portion of the support substrate may be used as the stiffener 11. Thereby, the removal of the support substrate and the formation of the stiffener 11 can be performed at the same time, and the adhesive layer 15 becomes unnecessary.
- the semiconductor device 1 is mounted on a motherboard (not shown) via a BGA ball 8.
- the mother board is, for example, an FR-4 substrate or an FR-5 substrate, for example, a glass epoxy substrate in which a glass cloth is immersed in an epoxy resin.
- the semiconductor device 1 receives a power supply potential and a signal via a motherboard. At this time, the power supply potential and the signal are input to the semiconductor chip 9 via a current path composed of the BGA ball 8 ⁇ the ball pad 6 ⁇ the via 4 and the wiring 3 ⁇ the mounting pad 5 ⁇ the solder bump 7.
- the semiconductor chip 9 performs information processing such as signal storage and calculation based on the input power supply potential and signal, and outputs the result.
- the output signal is output to the mother board via the current path consisting of the solder bump 7 ⁇ mounting pad 5 ⁇ via 4 and wiring 3 ⁇ ball pad 6 ⁇ BGA ball 8, and is output via the mother board Output to the outside.
- the semiconductor chip 9 generates heat by operating. Although a part of this heat is absorbed by the lid 12, the heat capacity of the lid 12 is limited, so that another part of the heat is conducted to the package substrate 2 via the solder bump 7, and the rest is the semiconductor chip 9. Is accumulated in As a result, the temperatures of the semiconductor chip 9, the solder bumps 7, and the package substrate 2 inevitably increase. As a result, the semiconductor chip 9 and the package substrate 2 thermally expand. However, the thermal expansion coefficient of silicon forming the substrate of the semiconductor chip 9 and the thermal expansion coefficient of the resin material mainly forming the package substrate 2 are increased. Since the expansion coefficients are different from each other, the respective thermal expansion amounts are also different from each other. As a result, a shearing force is applied between the semiconductor chip 9 and the package substrate 2 via the solder bumps 7.
- the uppermost wiring layer 16 of the knocking substrate 2 is formed of a relatively soft resin material having a Young's modulus of 1 GPa or less, the wiring layer 16 The tip 9 can be deformed following the thermal expansion. As a result, the force acting between the semiconductor chip 9 and the package substrate 2 is reduced, and a large force is not applied to the solder bump 7.
- the semiconductor device 1 is heated or cooled by an external temperature change, the thermal stress acting between the semiconductor chip 9 and the package substrate 2 is alleviated by the deformation of the wiring layer 16, and the solder bump 7 becomes excessively large. No force is applied. As a result, the solder bump 7 that does not warp the semiconductor device 1 is not broken.
- the uppermost layer of the package substrate 2, that is, the wiring layer 16 on the side of the semiconductor chip 9 has a Young's modulus at a temperature of 10 to 30 ° C. of 1 GPa or less. Since it is relatively soft and is formed of a material, even if a temperature cycle is applied to the semiconductor device 1 due to the operation of the semiconductor chip 9 or a change in external temperature, an excessive force is applied to the solder bump 7 and the solder bump 7 Can be prevented from being destroyed. Further, it is possible to prevent the solder bumps 7 from being subjected to fatigue damage due to repeated application of thermal stress to the solder bumps 7. For this reason, the semiconductor device 1 has high connection reliability with respect to a temperature cycle.
- the wiring layer was formed of a material having as high a Young's modulus as possible, that is, a hard material. For this reason, thermal stress was concentrated on the solder bumps, and the solder bumps were destroyed.
- the wiring layer 16 since the elongation at break of the material forming the wiring layer 16 is 20% or more, even if the wiring layer 16 is deformed following the thermal expansion of the semiconductor chip 9, the wiring layer 16 may have cracks or the like. The reliability of the semiconductor device 1 in which no defects occur is high.
- the material forming the wiring layer 16 is such that the content of the reactive elastomer (A) is A, the content of the epoxy resin (B) is B, the curing agent for the epoxy resin.
- the content of (C) is C
- the material may have a value of (AX 100) Z (A + B + C) of 60% by mass or more and less than 100% by mass. As a result, the elongation at break becomes 30% or more, and the reliability of the semiconductor device 1 is further improved.
- the semiconductor device according to this embodiment is different from the first embodiment in the material for forming the wiring layer 16.
- the configuration of the present embodiment other than the above is the same as that of the above-described first embodiment.
- the material forming the wiring layer 16 has a Young's modulus of 1 GPa or less at 10 to 30 ° C. and, in addition, an elongation at break of 50% or more.
- the material forming the wiring layer 16 in the present embodiment contains a reactive elastomer (A) capable of reacting with the epoxy resin, an epoxy resin (B) and a curing agent (C) for the epoxy resin. are doing.
- the epoxy resin curing agent (C) has a longer distance between the functional groups than the phenol novolak resin, and as the resin (D), for example, phenol biphenyl-alkyl aralkyl resin and phenol Phenol aralkyl type such as xylylene resin Contains fat.
- the reactive elastomer (A) for ensuring the toughness of the resin material is insufficient, and In some cases, elongation at break cannot be obtained. Therefore, the above value is preferably 60% by mass or more.
- the curing agent for epoxy resin (C) has a longer distance between functional groups than the phenol novolak resin and contains resin (D)!
- the network of the crosslinked structure when the epoxy resin (B) is thermally cured by the phenol novolak resin can be enlarged.
- the reactive elastomer (A) and the epoxy resin (B) can be efficiently reacted to positively form an IPN structure and improve the stress relaxation of the resin material.
- the semiconductor device according to this embodiment is different from the first embodiment in the material for forming the wiring layer 16.
- the configuration of the present embodiment other than the above is the same as that of the above-described first embodiment.
- the material forming the wiring layer 16 has a Young's modulus at 10 to 30 ° C. of 1 GPa or less and a breaking elongation of 50% or more, as in the second embodiment.
- the composition of this material is different from that of the second embodiment. That is, it contains a reactive elastomer (A), an epoxy resin (B), and a curing agent for epoxy resin (C).
- the curing agent for epoxy resin (C) is, in addition to the phenolic curing agent, a phenolic curing agent.
- the distance between the functional groups is longer than that of the novolak resin, and the resin (D) contains, for example, an ethylene oxide conjugate (E).
- E ethylene oxide conjugate
- the content of the reactive elastomer (A) is A
- the content of the epoxy resin (B) is B
- the content of the epoxy resin curing agent (C) is C
- the value of (A + B + C) is 60% by mass or more and less than 100% by mass.
- the epoxy resin curing agent (C) contains, for example, an ethylene oxide compound (E)
- the epoxy resin curing agent (C) is The network of the crosslinked structure when the resin (B) is thermally cured can be enlarged. As a result, the reactive elastomer (A) and the epoxy resin (B) can be efficiently reacted to positively form an IPN structure, thereby improving the stress relaxation of the resin material.
- a fourth embodiment of the present invention will be described.
- the semiconductor device according to this embodiment is different from the first embodiment in the material for forming the wiring layer 16.
- the configuration of the present embodiment other than the above is the same as that of the above-described first embodiment.
- the material forming the wiring layer 16 has a Young's modulus at 10 to 30 ° C. of 1 GPa or less and an elongation at break of 50%, as in the second and third embodiments. That is all.
- the composition of this material is different from those of the second and third embodiments. Hereinafter, the composition of this material will be described in detail.
- the material for forming the wiring layer 16 in the present embodiment contains, as essential components, a reactive elastomer (A) capable of reacting with an epoxy resin and an epoxy resin (B). Further, this resin material may contain a curing agent (C) for epoxy resin.
- a reactive elastomer (A) capable of reacting with an epoxy resin and an epoxy resin (B).
- this resin material may contain a curing agent (C) for epoxy resin.
- (AX 100) / the value of (a + B + C) is less than 100 mass% 60 mass 0/0 above. Note that the value of C may be 0.
- the value force of (AX 100) Z (A + B) is 60% by mass or more and less than 100% by mass.
- the epoxy resin (B) contains an epoxy resin having a longer distance between functional groups than the phenol novolak resin, for example, an epoxy resin conjugate (F) of an ethylene oxide compound.
- the reactive elastomer (A) for securing the toughness of the resin material is insufficient, and In some cases, elongation at break cannot be obtained. Therefore, the above value is preferably 60% by mass or more.
- the composition of the reactive elastomer (A) is the same as that of the first to third embodiments.
- the resin material according to the present embodiment may or may not contain the epoxy resin curing agent (C), but if it does, it contains a conventional epoxy resin curing agent. As long as a curing agent is used, for example, a phenolic curing agent may be used.
- Components other than the above in the resin material of the present embodiment are the same as those of the above-described first embodiment.
- the epoxy resin (B) contains the epoxidized product (F) of an ethylene oxide compound.
- the epoxide (F) of this ethylene oxide compound is represented by the following chemical formula 12. [0089] [Formula 12]
- Formula R 7 described in 12 represents a monovalent substituent having a carbon number of 1 to 3, or hydrogen.
- i represents an integer of 1 to 4.
- i ′ represents an integer of 1 to 3.
- Y represents a compound Y represented by the following chemical formula 13 or a compound Y represented by the following chemical formula 14.
- j is 1 to 10
- Formula 13 R 8 which are described, represents a monovalent substituent having 1 to 3 carbon atoms, or hydrogen.
- p represents an integer of 1 to 4.
- q represents an integer of 0 to 9.
- R 9 in the above Chemical Formula 14 represents a monovalent substituent having 1 to 3 carbon atoms or hydrogen. Represent. r represents an integer of 1 to 4. s represents an integer of 0 to 9.
- the epoxy resin (B) a resin having a longer distance between functional groups (in this case, an epoxy group) than phenol novolak epoxy resin is used. . This makes it easier to form the IPN structure more efficiently and improves toughness.
- the distance between the functional groups is longer than that of the phenol novolak resin, and a compound obtained by subjecting the above-described ethylene oxide conjugate to epoxidation so as to easily form an IPN structure as an epoxy resin.
- a resin such as (F) that can increase the distance between cross-linking points is used.
- the distance between the cross-linking points between the epoxidized object (F) and the curing agent can be lengthened, and the reactive elastomer (A) efficiently penetrates into the cross-linked structure to form a molecular chain.
- the entanglement effect becomes higher.
- the IPN structure can be efficiently formed, the Young's modulus is low, the breaking elongation is high, and a resin material can be obtained.
- the resin material of the present embodiment contains the epoxy resin (B) power and the epoxy resin compound (F) of the ethylene oxide compound. It has a low Young's modulus and a high elongation at break. As a result, as in the second and third embodiments described above, in the semiconductor device 1, connection reliability with respect to temperature cycles can be improved. Other operations and effects of the present embodiment are the same as those of the above-described first to third embodiments.
- the semiconductor device according to the present embodiment is different from the first to fourth embodiments in the material for forming the wiring layer 16.
- the configuration other than the above in the present embodiment is the same as that of the above-described first embodiment.
- the material forming the wiring layer 16 has a Young's modulus at 10 to 30 ° C. of 1 GPa or less and a breaking elongation of 50% or more as in the above-described second to fourth embodiments. It is.
- the composition of this material is different from those of the second to fourth embodiments.
- the composition of this material will be described in detail.
- the material forming the wiring layer 16 in the present embodiment is a material that can react with the epoxy resin.
- the content of the reactive elastomer (A) is A
- the content of the epoxy resin (B) is B
- the content of the epoxy resin curing agent (C) is C
- (AX 100) Z The value of (A + B + C) is 60% by mass or more and less than 100% by mass.
- the epoxy resin (B) contains an epoxy resin compound (F) of an ethylene oxide compound
- the epoxy resin curing agent (C) contains the ethylene oxide compound (E). .
- composition of (E) is the same as in the third embodiment.
- composition of the epoxidized product (F) of the ethylene oxide compound is the same as that of the fourth embodiment.
- components other than the above in the resin material of the present embodiment are the same as those of the above-described first embodiment.
- the resin material is a reactive elastomer (A) capable of reacting with an epoxy resin, an epoxy resin (B), and a curing agent for epoxy resin (C).
- the content of the reactive elastomer (A) is at least 60% by mass and less than 100% by mass with respect to the total amount of these, and the curing agent for epoxy resin (C) is an ethylene oxide conjugate (E)
- the epoxy resin (B) contains the epoxy territories (F) of the ethylene oxide territories, and thus has high elongation at break.
- the semiconductor device according to this embodiment is different from the first to fifth embodiments in the material for forming the wiring layer 16.
- the configuration other than the above in the present embodiment is the same as that of the above-described first embodiment.
- the material forming the wiring layer 16 has a Young's modulus at 10 to 30 ° C. of 1 GPa or less and an elongation at break of 55% or more, and the composition of this material is This is different from the fifth embodiment.
- the composition of this material will be described in detail.
- the material forming the wiring layer 16 in the present embodiment contains, as essential components, a reactive elastomer (A) capable of reacting with an epoxy resin and an epoxy resin (B).
- this resin material may contain a curing agent (C) for epoxy resin.
- C curing agent
- the content of the reactive elastomer (A) is A
- the content of the epoxy resin (B) is B
- the content of the epoxy resin curing agent (C) is C
- (AX 100) Z The value of (A + B + C) is 70% by mass or more and less than 100% by mass. Note that the value of C may be 0. In this case, the value of (AX 100) / (A + B) is 70% by mass or more and less than 100% by mass.
- the reactive elastomer (A) for ensuring the toughness of the resin material is insufficient, and In some cases, elongation at break cannot be obtained. Therefore, the above value is preferably 70% by mass or more.
- the compositions of the reactive elastomer (A) and the epoxy resin (B) are the same as those in the first embodiment.
- the epoxy resin curing agent (C) is used, a conventional epoxy resin curing agent may be used as in the first embodiment.
- the components other than the above in the resin material of the present embodiment are the same as those of the above-described first embodiment.
- the mass ratio of the reactive elastomer (A) ⁇ (AX 100 ) / (A + B + C) ⁇ is specified in the range of 70% by mass or more and less than 100% by mass. For this reason, for example, at room temperature, for example, at 25 ° C., there is no need to use a resin capable of increasing the distance between crosslinking points, such as the aforementioned ethylene oxide conjugate (E) or the epoxidized product (F). In addition, the elongation at break shows a specific increase, and extremely excellent stress relaxation can be realized. Other operations and effects of the present embodiment are the same as those of the above-described first embodiment.
- the uppermost wiring layer 16 of the knock substrate 2 is formed of a resin whose Young's modulus at room temperature is 1 GPa or less.
- two or more wiring layers including the uppermost layer may be formed of a resin whose Young's modulus is 1 GPa or less. It may be formed of a resin having a ratio of 1 GPa or less.
- the lowermost wiring layer of the package substrate 2 that is, the wiring layer facing the mother board (not shown) of the knock substrate 2 is also 10 It is preferable to use a resin material having a Young's modulus of 1 GPa or less in a temperature range of 30 ° C to 30 ° C.
- the lowermost wiring layer of the knock substrate 2 can be deformed following the thermal expansion of the mother board, and the thermal stress applied to the BGA balls 8 can be reduced.
- the warpage of the semiconductor device 1 and the fatigue destruction of the BGA ball 8 can be prevented, and the connection reliability with respect to a temperature cycle can be improved.
- the elongation at break of the resin material forming the lowermost wiring layer of the aforementioned knock substrate 2 is 50% or more!
- a ball pad 6 and a BGA ball 8 may be provided on the surface of the package substrate 2 on which the semiconductor chip 9 is mounted, and the BGA ball 8 may be connected to the mother board.
- Test Example 1 linear thermal stress analysis was performed by simulation, assuming the semiconductor device described in the first to fourth embodiments.
- FIG. 3 is a perspective view showing a semiconductor device assumed in this simulation
- FIG. 4 is a partially enlarged view of the semiconductor device shown in FIG. 3
- FIGS. 5 (a) and 5 (b) are perspective views showing simulation results.
- FIG. 3A shows an example of the present invention
- FIG. 3B shows a comparative example.
- FIGS. 5 (a) and 5 (b) show the (1Z4) portion of the entire semiconductor device.
- the simulation conditions will be described.
- the model used for the simulation was created using I-DEAS MasterSeries 7.0.
- an FCBGA type semiconductor device 21 was assumed as the semiconductor device to be simulated.
- the shape of the semiconductor device 21 is square in plan view, and is four-fold symmetric. Therefore, in this simulation, a (1Z4) model obtained by dividing the semiconductor device 21 into four along the symmetry plane W was analyzed.
- a package substrate 22 is provided. Yes.
- the entire knocking substrate 22 is formed of a single resin.
- a solder resist 37 is formed on the upper and lower surfaces of the knock substrate 22.
- a semiconductor chip 29 is mounted on a central portion of the package substrate 22 via a solder resist 37.
- the semiconductor chip 29 is entirely formed of silicon.
- An underfill resin 30 is provided between the solder resist 37 and the semiconductor chip 29.
- a frame-shaped stiffener 31 is provided on the periphery of the knocking board 22, and the semiconductor chip 29 is accommodated in the opening of the stiffener 31.
- An adhesive layer 38 is provided between the stiffener 31 and the solder resist 37.
- Table 1 shows the dimensions of each member of the semiconductor device 21, ie, the width and thickness, and the mechanical properties of each part, ie, Young's modulus, linear expansion coefficient, and Poisson's ratio.
- simulation was performed using the model of the example of the present invention and the model of the comparative example.
- the Young's modulus of the material forming the package substrate 22 was set to 0.73 GPa
- the Young's modulus of the material forming the package substrate 22 was set to 3.1 GPa.
- the material of the package substrate 22 used in the model of the comparative example was ABF-GX (trade name) manufactured by Ajinomoto Fine-Techno.
- the “width” shown in Table 1 is the length in the vertical direction and the horizontal direction in the (1Z4) model described above. In the semiconductor device 21 as a whole, the width of each member is twice the value described in Table 1. Value.
- Nodes on the symmetry plane restrained displacement in the direction perpendicular to the symmetry plane. Further, the node S, that is, the node on the lower surface of the package substrate 22 on the intersection line of the symmetry plane restrains displacement in all directions and is a fixed point.
- FIGS. 5 (a) and (b) and Table 2 The results of such a simulation are shown in FIGS. 5 (a) and (b) and Table 2.
- X, y, and z shown in FIGS. 5 (a) and 5 (b) indicate a rectangular coordinate system, and the X and y directions are parallel to the upper surface of the package substrate 22 when the temperature is 220 ° C. And the z direction is the direction perpendicular to this top surface.
- auxiliary lines are shown in the figures to make it easy to recognize a three-dimensional shape.
- Table 2 shows the amount of warpage at the corner of the stiffener opening, that is, at the corner of the opening of the stiffener 31, and the amount of warpage at the corner of the knocking board, that is, at the node T.
- the amount of warpage refers to the amount of displacement in the z direction.
- Test Example 2 will be described.
- the resin material described in each of the above-described embodiments was actually manufactured, and a laminate film, a double-sided copper-clad sheet, and an FCBGA type semiconductor device were manufactured using the resin material. These properties were evaluated.
- each component forming the resin material according to Examples and Comparative Examples will be described. Table 3 shows that each of these components, i.e., reactive elastomer (A), epoxy resin (B), curing agent for epoxy resin (C), and resin with a longer distance between functional groups than phenol novolak resin ( D), an ethylene oxide conjugate (E) and an ethylene oxide conjugate (F).
- Resin D 2 Phenyl-xylylene resin 1100 169-Phenyl phenylene aralkyl type ⁇ 0
- a reactive polyamide elastomer (A1) or (A2) shown in Table 3 was used as the reactive elastomer (A).
- the structure of the reactive polyamide elastomers (A1) and (A2) can be represented by the following chemical formula 15.
- x, y, z, 1 (ell) m and n are average polymerization degrees, respectively, X is an integer of 3 to 7, y is an integer of 1 to 4, and z is 5 to 15
- n l + m
- n represents an integer of 2 to 200, and m / (l + m) ⁇ 0.04.
- the epoxy resin (B) includes phenol biphenyl-enralki shepoxy resin (B1), phenol xylylene epoxy resin (B2), and phenol novolak epoxy resin shown in Table 3. (B3) was used.
- the structure of phenol biphenyl-lenaryl epoxy resin (B1) can be represented by the following chemical formula 16, and the structure of phenol xylylene epoxy resin (B2) can be represented by the following chemical formula 17, and the structure of phenol novolak epoxy resin (B3) Can be represented by the following chemical formula 18.
- n represents an integer of 0 to 75.
- p-cresol novolak resin (C1) or phenol novolak resin (C2) shown in Table 3 was used as the curing agent for epoxy resin (C).
- the structure of p-cresol novolak resin (C1) can be represented by the following chemical formula 19
- the structure of phenol novolak resin (C2) can be represented by the following chemical formula 20.
- n represents an integer of 0 to 75.
- phenol biphenyl-alkylalkyl resin (D1) or phenol xylylene resin (D2) shown in Table 1 was used.
- the structure of phenol biphenyl-alkylalkyl resin (D1) can be represented by the following chemical formula 21, and the structure of phenol xylylene resin (D2) can be represented by the following chemical formula 22.
- n represents an integer of 0 to 75.
- the ethylene oxide conjugates (E) include phenol biphenyl-ethylene aralkyl type ethylene oxide (EO) resin (E1), phenol xylylene type ethylene oxide resin (E2) shown in Table 3.
- EO phenol biphenyl-ethylene aralkyl type ethylene oxide
- E2 phenol xylylene type ethylene oxide resin
- E3 a phenol novolak type ethylene oxide resin
- the structure of phenol biphenyl-lenaralkyl type EO resin (E1) can be represented by the following chemical formula 23, and the structure of phenol xylylene type EO resin (E2) can be represented by the following chemical formula 24, and the structure of phenol monovolak EO resin (E3) Can be represented by the following chemical formula 25.
- n represents an integer of 0 to 75.
- the epoxidized product (F) of the ethylene oxide conjugated product includes the epoxidized product (F1) of the phenol biphenyl-lenaralkyl type ethylene oxide compound and the epoxidized product of the phenol xylylene type ethylene oxide compound shown in Table 3. (F2) or a phenol nopolak-type ethylene oxide conjugated epoxy ridge (F3) was used.
- the structure of the epoxide (F1) can be represented by the following chemical formula 26
- the structure of the epoxide (F2) can be represented by the following chemical formula 27, and the structure of the epoxide (F3) can be represented by the following chemical formula 28.
- n represents an integer of 0 to 75
- G represents a glycidyl group represented by the following chemical formula 29.
- the varnish solution was uniformly applied on a polyethylene terephthalate (PET) film coated with a release agent using a coating machine so as to obtain a desired thickness. Then, it is dried at a temperature of 100 ° C for 5 minutes to evaporate a certain amount of the solvent. Then, the resin surface is covered with a PET film with a release agent, and a three-layer laminated film, ie, (release) A laminate film having a structure of (PET layer-resin layer-release PET layer) was prepared. The resin layer (including the residual solvent) in the laminate film is in an uncured state.
- PET polyethylene terephthalate
- the varnish solution was uniformly applied to a roughened surface (also referred to as a mat surface) of the copper foil shown in Table 4 with a coating machine so as to obtain an intended thickness. After that, it was dried at a temperature of 100 ° C for 5 minutes to evaporate a certain amount of the solvent, and then the resin surface was covered with a PET film with a release agent. —Fat content—copper foil).
- the resin layer (including the residual solvent) in the pre-predator material is in an uncured state.
- the FCBGA type semiconductor device shown in FIG. 1 was manufactured using the resin materials according to the above-described examples and comparative examples. That is, wiring was formed on the copper foil of the single-sided copper-clad pre-preplated material described in (2) above, and a plurality of layers of the single-sided copper-clad pre-preed material were laminated by a build-up method to produce a package substrate. Then, a semiconductor chip was mounted on the package substrate, a frame-shaped stiffener was provided around the semiconductor chip, and a lid (heat sink) was bonded on the semiconductor chip and the reinforcing plate.
- a cured film for a tensile test was prepared. Then, the cured film was cut into a strip having a width of 10 mm and a length of 80 mm, and a tensile test was performed. The tensile test conditions were set such that the distance between the supports for supporting the cured film was 60 mm and the tensile speed was 5 mmZ. By this tensile test, Young's modulus and elongation at break were calculated.
- a sample was prepared in which (release mold PET layer, resin layer (resin layer of Examples or Comparative Examples) copper foil, conventional resin layer, PEN layer, and mirror wafer) were laminated in this order.
- an IMPa pressure was applied to the sample at a temperature of 180 ° C. for 30 minutes to bond the resin layer of the laminating film to the patterned copper foil.
- the sample was observed with a microscope, and the degree of embedding of the copper foil pattern in the resin layer was observed to determine whether or not the circuit embedding property was good.
- the case where the circuit embedding property was particularly excellent was rated as ⁇ , and the case where it was practically sufficient was rated as ⁇ .
- FCBGA-type semiconductor devices prepared in (4) above were prepared for each resin material, and a temperature cycle test was performed on these semiconductor devices.
- the temperature cycle test was started from room temperature, cooled to 40 ° C, held at -40 ° C for 15 minutes, heated to 125 ° C, and held at 125 ° C for 15 minutes as one cycle. .
- the heating and cooling times were fixed at 15 minutes. If a crack occurs at the joint (solder bump) between the semiconductor chip and the package substrate that constitute the FCBGA type semiconductor device after 1000 cycles of the temperature cycle test, it is regarded as a defect.
- the number of defective occurrences) was used as an index of connection reliability. The number of failure occurrences is small.
- FCBGA-type semiconductor devices have better temperature cycle resistance.
- Tables 5 to 10 show the compositions of the resin materials and the evaluation results according to each of the examples and comparative examples.
- a reactive type elastomers one (A), poly amide elastomer (A1) 60 wt 0/0, as the epoxy ⁇ (B), epoxy ⁇ the (B1) 23 86% by mass, epoxy resin curing agent (C) as epoxy resin curing agent (D1) 16.14% by mass, and imidazoles as curing accelerator catalyst 0.05% by mass
- the mixture obtained is dissolved and dispersed in an organic solvent (a mixed solvent of 78% by mass of cyclopentanone and 22% by mass of methyl ethyl ketone (MEK)) and dispersed therein to obtain a nonvolatile component (total amount of components other than the above organic solvent).
- an organic solvent a mixed solvent of 78% by mass of cyclopentanone and 22% by mass of methyl ethyl ketone (MEK)
- Epoxy resin B 1 23.86 29.83 Epoxy resin B 2
- Curing agent for epoxy resin C 2 10.17 Curing agent for epoxy resin D 1 16.14
- Curing agent for epoxy resin C 2 8.30 10.17 Curing agent for epoxy resin D 1 13.68 15. 13 17.67
- Curing acceleration catalyst (phr) 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 Elongation at break (%) 70 63 60 58 72 32 Toughness
- Epoxy resin B 1 18.71 19.21 18.71 18.88 5.20 36.91 22.00 Epoxy resin B 2
- Epoxy resin ffl curing agent C 2 5.79 13.09 8.00 Epoxy resin curing agent D 1
- Curing accelerator catalyst (phr) 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 100 20 56 Toughness
- Epoxy resin B 1 19.21 36.91 54.60 22.00 Epoxy resin B 2 18.49
- the temperature cycle test described above is set to conditions that are considerably more severe than the actual use conditions, so even if 5 out of 38 defective products occur in this test, there is no problem in actual use.
- the wiring layer of the knock substrate was formed of a resin material having a Young's modulus of 1.70 GPa at room temperature. As a result, 10 out of 38 semiconductor devices failed.
- the semiconductor devices according to Examples No. 1 to No. 25 had better connection reliability with respect to the temperature cycle than the semiconductor device according to Comparative Example No. 26.
- Examples Nos. 1 to 25 all had good circuit embedding properties. Among them, Examples No. 1 to No. 2, Example Nos. 5 to No. 17, Example No. 20 and Example No. 23 were particularly excellent in circuit embedding. As is clear from a comparison between Example No. 18 and Example No. 20 shown in Table 9, when the polyamide elastomer A1 was used as the reactive elastomer (A) (Example No. 18). Also, when the polyamide elastomer A2 having a lower molecular weight was used (Example No. 20), the circuit embedding property was superior. Test example 3
- Test Example 3 the material of the package substrate Using a commercially available resin material, a semiconductor device was fabricated in the same manner as in Test Example 2 described above, and a temperature cycle test was performed. Table 11 shows the results.
- Test Example 4 a substrate for evaluation was produced using a resin material containing the components shown in Table 12 as the reactive elastomer (A).
- Table 13 shows the components of the resin material.
- Epoxy Friend AT501 manufactured by Daiceli Gakugaku Kogyo was used as the flexible epoxy resin shown in Table 12.
- SG-95 manufactured by Nippon Talc was used as the inorganic filler described in Table 13.
- the average particle size of this inorganic filter is 2.5 m.
- the components other than the components shown in Table 12 are the same as the components shown in Table 3 described above.
- FIG. 6 is a diagram schematically showing the evaluation substrate manufactured in this test example.
- FIG. 7 is a plan view showing the evaluation substrate in detail.
- FIG. 8 is a plan view showing the evaluation substrate.
- FIG. FIG. 8 also shows the planar shape of the wiring 45.
- the evaluation board has a pair of comb-shaped wirings 41 arranged so as to be nested in each other. That is, the pair of comb-shaped wirings 41 are arranged so that the teeth of the other comb-shaped wiring 41 are located between the teeth of one of the comb-shaped wirings 41 and the comb-shaped wirings 41 do not contact each other.
- Each of the comb-shaped wirings 41 is connected to a square electrode 42.
- the evaluation substrate 43 is provided with a core FR-4 substrate 44.
- the outer shape of the substrate 44 has a length in the longitudinal direction of 24.4 mm, a length in the transverse direction of 8.0 mm, and a thickness of 0.8 mm.
- two electrodes 42 are arranged apart from each other in the longitudinal direction of the substrate 44. When viewed from above, the length of one side of the electrode 42 is 5.2 mm.
- two comb-shaped wirings 41 are nested with each other. Each comb-shaped wiring 41 is provided with ten wirings 45 serving as its teeth. The length of each wiring 45 is 8.7 mm.
- the 600 vias 46 are arranged in a (20 ⁇ 30) matrix.
- the via pitch is 300 m in both directions.
- a Cu pattern 47 made of Cu is provided intermittently along the direction in which the wiring 45 extends.
- a 50 m thick build-up resin layer 48 is provided so as to cover the Cu pattern 47.
- the build-up resin layer 48 is formed of any of the resins shown in Table 13.
- a Cu pattern 49 made of Cu is intermittently provided on the build-up resin layer 48 along the direction in which the wiring 45 extends.
- Each of the Cu patterns 47 and 49 has two circular portions each having a diameter of 150 m and a rectangular portion connecting them, as viewed from above, and has a thickness of 18 m.
- the rectangular portion of the Cu pattern 49 is located immediately above the region between the Cu patterns 47, and the circular portion of the Cu pattern 49 is located immediately above the circular portion of the Cu pattern 47.
- one via 46 is located between the circular portion of the Cu pattern 47 and the circular portion of the Cu pattern 49 in the build-up resin layer 48.
- the shape of the via 46 is a truncated cone with a diameter of 100 m at the upper end and 75 m at the lower end.
- the distance between two vias connected to the same Cu pattern 47 or 49 is 300 ⁇ m as described above.
- a 35 ⁇ m-thick solder-resist 50 is provided on the build-up resin layer 48 so as to cover the Cu pattern 49.
- a Cu pattern 51 having a thickness of 18 ⁇ m is provided on the entire back surface of the substrate 44.
- the illustration of the build-up resin layer 48 and the solder resist 50 is omitted.
- the circuit embedding property was evaluated.
- the evaluation method was the same as the test method described in (6) Evaluation of circuit embedding in Test Example 2 above. However, the lamination conditions were the same as those in Test Example 2 below, in addition to Condition 1 below, and a total of 4 conditions were added.
- Table 13 shows the evaluation results. As a result of the judgment, ⁇ indicates that the circuit embedding property was particularly excellent, ⁇ indicates that it was practically satisfactory, and ⁇ indicates that it was inferior to ⁇ and ⁇ but was practicable.
- Example No. 18 and No. 41 to No. 46 all had a HAST result of 300 hours or more, indicating good insulation reliability.
- insulation was not lost even when HAST was performed for up to 500 hours, and extremely good insulation reliability was exhibited.
- low CN polyamide elastomers (A3 and A4) and flexible epoxy resins (A5) shown in Table 12 do not contain cyanate groups, and therefore do not easily generate ammonia that dissolves Cu.
- Examples No. 42 to No. 46 had better circuit embedding properties than Examples No. 18 and No. 41. Of these, Examples No. 42 to No. 45 had particularly good circuit embedding.
- the present invention relates to a semiconductor device in which a semiconductor chip is directly mounted on a wiring board such as FCBGA. It can be suitably used for the installation.
Abstract
Description
Claims
Priority Applications (2)
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US11/568,111 US8058565B2 (en) | 2004-04-23 | 2005-04-15 | Wiring board, semiconductor device, and method for manufacturing wiring board |
JP2006512524A JP5082443B2 (ja) | 2004-04-23 | 2005-04-15 | 配線基板及び半導体装置並びに配線基板の製造方法 |
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JP2004-128948 | 2004-04-23 | ||
JP2004128948 | 2004-04-23 |
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PCT/JP2005/007325 WO2005104230A1 (ja) | 2004-04-23 | 2005-04-15 | 配線基板及び半導体装置並びに配線基板の製造方法 |
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US (1) | US8058565B2 (ja) |
JP (2) | JP5082443B2 (ja) |
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Cited By (5)
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JP2007191655A (ja) * | 2006-01-23 | 2007-08-02 | Somar Corp | 多層接着シート、熱交換器形成用材料及び熱交換器 |
JP2007306307A (ja) * | 2006-05-11 | 2007-11-22 | Dainippon Printing Co Ltd | カメラモジュール |
JP2011147182A (ja) * | 2011-04-11 | 2011-07-28 | Dainippon Printing Co Ltd | カメラモジュール用電気/電子部品埋設基材 |
US8143721B2 (en) * | 2007-06-29 | 2012-03-27 | Intel Corporation | Package substrate dynamic pressure structure |
JP2012082404A (ja) * | 2010-09-15 | 2012-04-26 | Asahi Kasei E-Materials Corp | フェノール樹脂組成物並びに硬化レリーフパターン及び半導体の製造方法 |
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JP5430655B2 (ja) * | 2009-05-27 | 2014-03-05 | 京セラ株式会社 | ろう材およびこれを用いた放熱基体ならびに電子装置 |
US9254532B2 (en) * | 2009-12-30 | 2016-02-09 | Intel Corporation | Methods of fabricating low melting point solder reinforced sealant and structures formed thereby |
US20120188721A1 (en) * | 2011-01-21 | 2012-07-26 | Nxp B.V. | Non-metal stiffener ring for fcbga |
TWI446464B (zh) * | 2011-05-20 | 2014-07-21 | Subtron Technology Co Ltd | 封裝結構及其製作方法 |
US9330993B2 (en) | 2012-12-20 | 2016-05-03 | Intel Corporation | Methods of promoting adhesion between underfill and conductive bumps and structures formed thereby |
US9282649B2 (en) * | 2013-10-08 | 2016-03-08 | Cisco Technology, Inc. | Stand-off block |
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Also Published As
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US8058565B2 (en) | 2011-11-15 |
JPWO2005104230A1 (ja) | 2008-03-13 |
JP5263374B2 (ja) | 2013-08-14 |
JP5082443B2 (ja) | 2012-11-28 |
JP2012044216A (ja) | 2012-03-01 |
US20070274060A1 (en) | 2007-11-29 |
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