WO2005086220A1 - Highly reliable, cost effective and thermally enhanced ausn die-attach technology - Google Patents

Highly reliable, cost effective and thermally enhanced ausn die-attach technology Download PDF

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Publication number
WO2005086220A1
WO2005086220A1 PCT/SE2005/000331 SE2005000331W WO2005086220A1 WO 2005086220 A1 WO2005086220 A1 WO 2005086220A1 SE 2005000331 W SE2005000331 W SE 2005000331W WO 2005086220 A1 WO2005086220 A1 WO 2005086220A1
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WIPO (PCT)
Prior art keywords
layer
wafer
evaporating
circuit die
die
Prior art date
Application number
PCT/SE2005/000331
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English (en)
French (fr)
Inventor
Sam-Hyo Hong
Henrik Hoyer
Jeffrey Hume
Original Assignee
Infineon Technologies Ag
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Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Priority to JP2007502765A priority Critical patent/JP4700681B2/ja
Publication of WO2005086220A1 publication Critical patent/WO2005086220A1/en
Priority to US11/530,276 priority patent/US7608485B2/en

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    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Definitions

  • the present invention relates to a method for attaching circuit dies, a method for manufacturing a circuit die, a circuit die, a circuit package including such a die and a power module including such a die.
  • the present invention relates to a circuit die, where said integrated circuit die should be interpreted to include discrete components, such as capacitors, inductors, diodes and resistors, a power module including such an integrated circuit die or discrete component, a package including such an integrated circuit die or discrete component, a method for manufacturing a circuit die, and a method for attaching a circuit die on a heat sink where said circuit is soldered to the heat sink using an Au-Sn soldering alloy.
  • discrete components such as capacitors, inductors, diodes and resistors
  • a power module including such an integrated circuit die or discrete component
  • a package including such an integrated circuit die or discrete component
  • a method for manufacturing a circuit die and a method for attaching a circuit die on a heat sink where said circuit is soldered to the heat sink using an Au-Sn soldering alloy.
  • Integrated circuits are, in broad terms, manufactured by processing a front side of an integrated circuit wafer comprising a multitude of integrated circuit dies or discrete power transistors or capacitors. The individual integrated circuits are then sawed from the wafer and mounted in an integrated circuit package, the connectors on the die are bonded to respective connectors on the package and the package is then sealed and ready for shipping.
  • One way of attaching a circuit die to a package is by soldering the backside of the die to a flange of the package.
  • Mounting of the die in the package comprises specific problems when the integrated circuit is a power device, since such devices produce a significant amount of heat and therefore are exposed to thermal mismatch and stress.
  • the die, solder and flange expand or contract differently due to the cooling after soldering or generated heat, delamination can occur if the induced stress is too large, thereby ruining the device.
  • CTE coefficient of thermal expansion
  • the size of the die is of great importance since a larger die will experience larger thermal mismatch and stress for the same temperature.
  • thermal mismatch can be a problem, when the die is a power device, such as RF power transistors.
  • the die, solder and flange can dissipate the generated heat, that is, that the die, solder and flange are good thermal conductors.
  • the attachment of the die is conventionally performed by an AuSi eutectic die-attach, which unfortunately oftentimes causes sever void problems with a large die.
  • the AuSi eutectic die-attach can moreover induce strong stress on the die, which limits the size and thickness of the die. Thinner die is desirable since better heat conduction from the die to the solder and flange is achieved.
  • the CTE for CuZr flanges matches the CTE for Au ⁇ n, which could be used as solder.
  • AuSn further has superior thermal and electrical conductivity and compared to AuSi.
  • a lower soldering temperature can be used with the AuSn solder compared to the AuSi eutectic alloy. This will reduce the induced stress.
  • PCM Powder Copper Molybdenum
  • CPC Copper-PCM-Copper and is a laminate of copper and PCM and copper.
  • the layers are clad under heat and pressure by rolling to form the CPC with certain thickness combinations, for example CPC (141), CPC (232), where the number stands for the thickness proportion between the different layers.
  • CPC 141
  • CPC 232
  • Even a pure copper heat sink is applicable, however the CuZr alloy is more stable with respect to mechanical and electrical properties than the pure copper.
  • GB-A-2 221 570 discloses bonding of a laser chip to a heat sink without the use of a discrete solder. The method is performed by metallizing the chip with a 2-3 urn thickness layer of tin sandwiched between submicron thickness layers of gold.
  • US 2004/0029304 Al discloses a cost effective method for assembly of hybrid optoelectronic circuits requiring flip-chip bonding of multiple active optoelectronic devices onto common substrate with fine pitch and high accuracy.
  • COB technique Chip On Board
  • a method for attaching integrated circuit dies to flanges of integrated circuit packages wherein each of the integrated circuit dies is sawed from a wafer.
  • the method comprises the steps of: reducing the thickness of the wafer by mechanical grinding, applying an isotropic wet chemical etching to the wafer to eliminate crystal defects generated by grinding, evaporating adhesion and diffusion barrier metals on the backside of the wafer, evaporating Au and Sn on the backside of the wafer, wherein the weight proportion of Au is equal to or larger than 85%, sawing the wafer into the circuit dies, and soldering each of the circuit dies to a respective flange of an integrated circuit package.
  • a method for manufacturing an integrated circuit die to be attached to a flange of an integrated circuit package, wherein the integrated circuit die is sawed from a wafer comprises the steps of: reducing the thickness of the wafer by mechanical grinding, applying an isotropic wet chemical etching to the wafer to eliminate crystal defects, evaporating adhesion and diffusion barrier metals on the backside of the wafer, evaporating Au and Sn on the backside of the wafer, wherein the weight proportion of Au, is equal to or larger than 85%, and sawing the wafer into circuit dies.
  • an integrated circuit die comprising a layer of adhesion and diffusion barrier metals on a backside of the die to be attached to a flange of an integrated circuit package, a stack of alternating layers of Au and Sn, where a first layer in the stack, which closest to the layer of diffusion barrier metals, is an Au layer and the final layer in the stack is an Au layer.
  • the integrated circuit die is characterised m that the weight percentage of Au in relation to Sn in the stack is equal to or higher than 85%.
  • an integrated circuit package comprising a flange and an integrated circuit according to the third or fourth aspect of the invention, wherein the flange is made of an alloy of Cu and Zr.
  • a rough etching is applied to the Si after the isotropic wet chemical etching to roughen the Si surface.
  • a round up etch is applied after the rough etching to eliminate sharp re-entrant peaks.
  • the rough etching achieves a mechanical interlocking function and increases the contact area between the Si and the adhesion metals, such as Ti. This eliminates or at least further reduces the risk of delamination and increases the adhesion effect.
  • the elimination of sharp re-entrant peaks removes "shadows" on the Si surface. Such "shadows” may render it more difficult to completely cover the Si surface with the adhesion metal during evaporation.
  • the step of applying an isotropic wet chemical etching removes at least 25 ⁇ m, preferably 30 ⁇ m, of the wafer backside.
  • the integrated circuit die is less than 150 ⁇ m thick, preferably approximately 40 ⁇ m to 80 ⁇ m.
  • the flange is an alloy of Cu and Zr.
  • evaporating a first Au layer, an Sn layer and a second Au layer performs the step of evaporating Au and Sn on the backside of the wafer.
  • the final layer of Au in the stack is thick enough to produce a smooth surface to facilitate release from an UV curable sawing tape, to obtain a residue free, clean Au surface, and to ensure full coverage of the Sn surface to prevent tin oxide formation.
  • Common diffusion barrier metals such as Pt, Ni, Pd, Cr etc, can form inter-metallic alloys with Sn.
  • the diffusion barrier metals can be resolved in the AuSn solder and thus erode the barrier causing delamination.
  • the invented method prevents formation of inter-metallic alloys between the Sn in the AuSn solder and the diffusion barrier metals thereby substantially increasing the reliability and high temperature operation of the device.
  • the final layer of Au is approximately between 0.5 and l.O ⁇ m thick.
  • the sawing tape from the die is facilitated, since a smoother face is achieved by the Au layer compared to the rough polycrystalline structure of the Sn.
  • the smoother Au surface can achieve a polymer residue free surface, which in turn at least reduces formation of voids.
  • evaporating a first Au layer and an Sn layer performs the step of evaporating Au and Sn on the backside of the wafer.
  • the first Au layer is so formed that at least a part of the first Au layer, being adjacent to the diffusion barrier metals layer, retain solid state during the step of soldering the circuit die to the flange.
  • the temperature is above the melting point for Sn of 232 degrees Celsius, which will then start to form inter-metallic alloys with the Au, such as AuSn and Au 5 Sn, which each has a lower melting temperature than Au.
  • Au will migrate rapidly into the molten Sn layer from both sides, that is, the Au layer adjacent to the diffusion barrier metals and also from the Au layer on the package flange. Thus a solder is achieved, attaching the circuit die onto the package flange.
  • the Au layer adjacent to the diffusion metals layer is so thick that the diffusion of solid Au into the molten Sn layer, or the Au and Sn liquid mixture, forming an eutectic alloy at approximately 280 degrees Celsius, is not complete and since the temperature, which is less than 340 degrees Celsius, during soldering do not ever reach the melting point for Au, being 1063 degrees Celsius, or for an Au rich mixture of Au and Sn, compared to the eutectic composition of Au and Sn, the part of the layer adjacent to the diffusion barrier metals is kept intact. Thereby, the Sn is not allowed to reach and erode the diffusion barrier metals.
  • the eutectic composition of Au and Sn comprises 80 weight percent Au and 2G weight percent Sn.
  • the first layer of Au is approximately 3 ⁇ m to 6 ⁇ m, preferably 5 ⁇ m thick.
  • the flange comprises a layer of plated Au, being 0.4 to 2.5 ⁇ m thick, which, together with the Au and Sn layers on the die during the step of soldering forms an alloy being Au richer than the eutectic
  • the Au rich alloy may comprise between 86 and 89
  • the step of evaporating adhesion and diffusion barrier metals comprises evaporating a Ti layer and evaporating a Pt layer on the backside of the wafer.
  • Figure 1 is a schematic flow diagram of an embodiment 25 according to the invention.
  • Figure 2 is a schematic flow diagram of the defect-etching step shown in figure 1 in greater detail.
  • Figure 3 is a schematic flow diagram of the evaporation step shown in figure 1 in greater detail.
  • Figure 4 is a schematic side view of a circuit die according to the present invention.
  • Figure 5 is a schematic top view of an integrated circuit package according to the present invention comprising an integrated circuit according to the present invention.
  • Figure 6 is a schematic top view of a part of a package according to the present invention comprising circuits and power transistors mounted according to the present invention.
  • FIG. 1 is a schematic flow diagram of an embodiment according to the present invention disclosing the different steps in the process flow.
  • step 101 the wafer is thinned, using a DISCO mechanical grinding tool, from approximately 525 or 675 ⁇ m to a wafer thickness which is approximately 30 ⁇ m thicker than the final die thickness, in the present embodiment approximately llO ⁇ m.
  • step 102 a defect etch of approximately 30 ⁇ m is performed in step 102.
  • the roughness of the surface is controlled by a SEZ chemical etcher.
  • the final thickness of the Si wafer is approximately 80 ⁇ m. For some applications it can be foreseen that the final thickness need to be as small as 40 ⁇ m.
  • the defect-etch removes crystal defects and achieves an elastic Si wafer.
  • the evaporated, metals on the Si wafer will make it bend rather much dependent on the wafer thickness and the solder metal stack composition and total thickness.
  • the wafer needs to be absolutely flat and if the wafer is brittle it will break during the flattening process. By performing the defect-etch the wafer is made elastic and it will be possible to flatten it during the sawing.
  • the roughness is controlled giving a roughness range of 0.4- l.O ⁇ m, so that an increased mechanical interlocking between the metal stack and the roughened Si surface is achieved.
  • the rough Si surface will also increase the contact area between the wafer and the adhesion metal layer. Consequently one can obtain manifold stronger adhesion compared to the flat Si surface.
  • a shear strength of more than 20kg/5mm 2 has been measured. The defect etch will be further described in connection with figure 2.
  • step 103 an HF hume treatment is performed to remove native oxide having formed on the Si surface by the oxygen in the ambient air.
  • an HF spin with a diluted solution may be used.
  • the F in the HF hume or HF water solution also bonds to the Si on the surface and achieves a Si-surface passivation by forming Si-F bonds, which prevent surface oxidation.
  • Evaporation of the adhesion metal, diffusion barrier metal and Au/Sn stack is performed in step 104. This step is further detailed in figure 3. After evaporation the wafer is taped on the backside with an UV curable tape and sawed in step 105 and finally the individual dies are soldered to respective package flanges.
  • the soldering is performed in a formic acid or nitrogen ambience at a temperature of 290-320 degrees Celsius for approximately 30 to 150 seconds dependent of the soldering tools used, such as batch-wise or single- package type. Since the solidification temperature is approximately 280 degrees, compared to 370 degrees for soldering with AuSi lower stress is induced on the dies.
  • FIG. 2 is a schematic flow diagram of step 102 in figure 1, that is the rough defect etch.
  • step 201 a bulk silicon etch is performed using Spinetch ® BT as medium with a flow of 1.2 1/min and at a temperature of 25 degrees Celsius.
  • step 201 is performed for 40 seconds.
  • step 202 a spin-off is performed for 3 seconds.
  • the chuck speed is 1400 rpm. For all of the following steps the chuck speed is 700 rpm.
  • step 203 a rough etch is performed using 1 part HF, 2 parts HN0 and 8 parts H 2 S0 4 as medium with a flow of 1.0 1/min.
  • the temperature in step 203 is set to 55 degrees Celsius and the step is performed for 60 seconds.
  • a spin-off step 204 is performed for 3 seconds and a rinse step 205 using DI as medium with a flow of 1.0 1/min is performed for 5 seconds.
  • a peak round-up step 206 using Spinetch ® D for medium and with a flow of 1.0 1/min is performed at a temperature of 25 degrees Celsius for 2 seconds.
  • a rinse step 207 using the medium DI with flow 1.0 1/min is performed for 10 seconds and finally a spin-off step 208 with chuck speed 1500 rpm is performed for 10 seconds.
  • FIG 3 is a schematic flow diagram of the evaporation step 104 in figure 1 in more detail.
  • the flow diagram in figure 3 discloses the E-beam evaporation of the Ti/Pt/Au/Sn/Au stack, in total 9.1 ⁇ m thick.
  • the E-beam evaporation is equipped with three Knudsen planetaries, which achieves deposition uniformly with accuracy better than +/-5%, typically +/- 3%, in thickness.
  • the deposition efficiency is approximately 50%.
  • the base pressure is pumped down to less than 1.5*10 " ' mbar by a cryo-pump in order to prevent oxygen induced solder aggregation.
  • step 302 the adhesion metal layer is added by evaporating a 150 nm thick Ti layer at an evaporation 5 speed of 1.0 nm/s and in step 303 the diffusion barrier metal layer is added by evaporating a 150 nm thick Pt layer at an evaporation speed of 0.5 nm/s.
  • step 304 a 5000 nm thick Au layer is added, forming the first layer in the solder stack, by evaporation at a speed of 1.0 nm/s. Evaporation induces
  • the E-beam evaporator is also equipped with six quartz crystals to monitor the thickness of the metal
  • Figure 4 is a schematic side view of an integrated circuit die according to the present invention, comprising the metal stack produced according to the methods described earlier. The figure is not to scale.
  • a circuit die 401 having on its ? ⁇ 5 backside a first layer of Ti 402 being 150 nm thick.
  • On top of the Ti layer 402 is a 150 nm thick Pt layer 403, a 5000 nm thick Au layer 404, a 2800 nm thick Sn layer 405 and finally a 1000 nm thick Au layer evaporated.
  • the layers 402 to 406 constitute the metal stack.
  • a thinner metal stack is preferable when the wafer thickness is around or below 60 ⁇ m.
  • the thinner metal stack of 6 ⁇ m requires a better flatness of the flange.
  • Such a thinner metal stack may be constituted by for instance lOOnm Ti / lOOnm Pt / 3400nm Au / 1900 nm Sn / 700 nm Au, in order from the Si surface and out.
  • FIG. 5 is a schematic top view of a package 501 according to the present invention.
  • the package comprises a flange 502 on top of which an integrated circuit die 503 according to the present invention has been soldered.
  • FIG. 6 is a schematic top view of a part of a package according to the invention.
  • a flange 601 of the package comprises a window frame 602. On the window frame is an external connector 603 mounted. Capacitors 604 are connected through Au wire bonds 606 to power transistors 605 and further to the external connector 603. In this embodiment there are thus several circuits and discrete components, of different kinds, soldered to the flange 601 according to the methods described herein.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
PCT/SE2005/000331 2004-03-09 2005-03-07 Highly reliable, cost effective and thermally enhanced ausn die-attach technology WO2005086220A1 (en)

Priority Applications (2)

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JP2007502765A JP4700681B2 (ja) 2004-03-09 2005-03-07 Ｓｉ回路ダイ、Ｓｉ回路ダイを製作する方法およびＳｉ回路ダイをヒートシンクに取り付ける方法並びに回路パッケージと電力モジュール
US11/530,276 US7608485B2 (en) 2004-03-09 2006-09-08 Highly reliable, cost effective and thermally enhanced AuSn die-attach technology

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EP04445024A EP1575089B1 (de) 2004-03-09 2004-03-09 Hochzuverlässige, kostengünstige und thermisch verbesserte Halbleiterchip-Befestigungstechnologie mit AuSn
EP04445024.5 2004-03-09

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EP (1) EP1575089B1 (de)
JP (1) JP4700681B2 (de)
DE (1) DE602004010061T2 (de)
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US7608485B2 (en) 2009-10-27
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US20070181987A1 (en) 2007-08-09

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