Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
  • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/26—Bombardment with radiation
  • H01L21/263—Bombardment with radiation with high-energy radiation
  • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
  • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

Definitions

• the present invention relates to the field of semiconductor processing, and more particularly, to the formation of spacers and source/drain formation in semiconductor devices.
• a substrate 10 has a gate 12 formed thereon.
• the gate 12 may be a polysilicon gate, for example.
• Source/drain extension regions 16 are formed, by ion implantation, for example, employing the gate 12 as an implantation mask.
• a spacer layer 14 is deposited by any suitable method, such as chemical vapor deposition.
• the spacer layer may be made of any suitable material, such as silicon nitride, silicon oxide, low- k dielectric materials, etc.
• the isotropic etching creates "D"-shaped spacers 18 that extend from the sidewalls of gate 12.
• the spacers 18 form a mask, along with the gate 12, for performing a source/drain implantation process. It is desirable to space the deep source/drains from the gate 12 in order to reduce short channel effects.
• An ion implantation process as indicated by arrows 20, is employed to create the deep source/drain implants.
• the outer regions of the D-shaped spacers 18 have a relatively thin profile at the outer edges.
• D-shaped spacers 18 Another disadvantage of the D-shaped spacers 18 is the worsening of conformity for further film deposition, necessary in such processes as the formation of a double spacer or the forming of an interconnect layer dielectric.
• the sloping nature of the outer shape of the spacers reduces conformity in subsequent film depositions.
• embodiments of the present invention which provide a method of forming a spacer comprising the steps of depositing a spacer layer over a substrate and a gate electrode having a top surface and vertically extending sidewalls, and forming a protective layer on the spacer layer.
• the protective layer is etched to remove the protective layer from the spacer layer over the top surface of the gate electrode and maintain the protective layer on the spacer layer parallel to the sidewalls of the gate electrode.
• the spacer layer is etched to remove the spacer layer from the substrate and over the top surface of the gate electrode to form spacers on the gate electrode with each spacer having two substantially vertical sidewalls extending parallel to the gate electrode sidewalls.
• a protective layer on the spacer layer the sidewall of the spacer is protected during the etching process, so that a substantially rectangular (I-shaped) spacer is formed.
• the spacer according to the present invention therefore does not have a thinner outer edge that makes the implantation profile difficult to control.
• the relatively vertical outer wall of the spacer increases conformity for further film deposition, such as double spacer processes or interconnect layer dielectrics.
• the earlier stated needs are also met by other embodiments of the present invention which provide a method of forming a semiconductor device comprising the steps of forming a gate electrode having vertically extending sidewalls on a substrate, and forming first sidewall spacers on the gate electrode. Each first sidewall spacer has a pair of vertically extending planar sidewalls that are substantially parallel to the gate electrode sidewalls. A source/drain implantation process is performed with the gate electrode and the first sidewall spacers masking the substrate.
• the earlier stated needs are also met by other embodiments of the present invention which provide a semiconductor device comprising a substrate, a gate on the substrate with the gate having vertical sidewalls, and sidewall spacers.
• the sidewall spacers are on the gate sidewalls, and have a rectangular cross-section and extend vertically to greater than half the height of the gate. Ion implanted source/drain regions are provided that are defined by the sidewall spacers.
• FIG. 1 is a schematic, cross-sectional view of a semiconductor device during one phase of manufacture in accordance with prior art methodology.
• Fig. 2 depicts the structure of Fig. 1 following isotropic etching to form spacers in accordance with prior art methodologies.
• Fig. 3 shows the structure of Fig. 2 after a source/drain implantation process has been performed.
• Fig. 4 is a schematic, cross-sectional view of a semiconductor device during one phase of manufacture in accordance with embodiments of the present invention, following the deposition of a spacer layer.
• Fig. 5 shows the structure of Fig. 4 after the deposition of a protective layer on the spacer layer, in accordance with embodiments of the present invention.
• Fig. 1 is a schematic, cross-sectional view of a semiconductor device during one phase of manufacture in accordance with prior art methodologies.
• Fig. 3 shows the structure of Fig. 2 after a source/drain implantation process has been performed.
• Fig. 4 is a schematic
• FIG. 6 depicts the structure of Fig. 5 following the etching of the protective layer in accordance with embodiments of the present invention.
• Fig. 7 shows the structure of Fig. 6 following the etching of the spacer layer in accordance with embodiments of the present invention.
• Fig. 8 depicts the structure of Fig. 7 during a source/drain implantation process performed in accordance with embodiments of the present invention.
• the present invention addresses and solves problems related to the formation of spacers and the source/drain implantation dose profile in advanced CMOSFET device technology.
• the invention overcomes problems related to the relatively thinner outer edge of the spacer created in the prior art with a D- shape that allowed punch-through during the source/drain implantation process, degrading the control of the implant dose profile.
• the invention achieves improvement in the implant dose profiling during the source/drain implantation process by creating a substantially rectangular (I-shape) spacer on the gate and employing the spacer as a mask during the source/drain implantation process.
• Fig. 4 is a schematic, cross-sectional view of a semiconductor device during one phase of manufacture in accordance with embodiments of the present invention.
• a substrate 30 has a gate electrode 32, such as a polysilicon gate, formed thereon by conventional techniques.
• a source/drain extension formation process is formed, employing the gate 32 as a mask to create source/drain extensions 36.
• the gate 32 has sidewalls 38 and a top surface 40.
• the sidewalls 38 of the gate 32 are typically formed by a dry etching technique, such as reactive ion etching (RIE), and are substantially vertical and planar.
• RIE reactive ion etching
• a spacer layer 34 is shown deposited on the substrate 30 and over the gate 32.
• the spacer layer 34 may be made of any suitable dielectric material, such as a nitride, an oxide, a low-k dielectric material, etc.
• the deposition may be by any suitable technique, such as chemical vapor deposition, for example.
• a suitable depth or thickness of the spacer layer 34 is provided, and is dependent upon the desired width of the spacers that will eventually be formed after etching of the spacer layer 34.
• the spacer layer is deposited to a thickness of between about 300 A to about 800 A.
• the formation of the spacer layer 34 is followed by an isotropic etching to form D-shaped spacers, such as depicted in Fig. 2.
• the present invention instead forms a protective layer 42, as shown in Fig. 5, that is conformally deposited on the spacer layer 34.
• the material of the protective layer 42 is different from the material forming the spacer layer 34.
• the material in the protective layer 42 should be such that it is not substantially etched when the spacer layer 34 is subjected to an etching by a particular etchant.
• an etchant should be used that is highly selective to the material in the spacer layer 34.
• a suitable material for the protective layer 42 is an oxide, for example.
• the material of the protective layer 42 should exhibit good conformity. The thickness of the protective layer 42 is much less than that of the spacer layer 34 in embodiments of the present invention.
• a thickness of between about 10 A to about 100 A may be employed to provide an adequate protection to the sidewalls of the spacers that will be formed from the spacer layer 34, as will be seen.
• a thickness that provides a sufficient amount of protection to the sidewalls of the spacers formed from the spacer layer 34 is needed, so that a relatively thin protective layer 42 is desirable to reduce material costs and processing time.
• Fig. 6 depicts the structure of Fig. 5 following an etching process to remove the protective layer 42 except along the vertically extending sidewalls of the spacer layer 34 that are parallel to the sidewalls 38 of the gate 32. These regions of the protective layer 44 are designated with reference numeral 44 in Fig. 6.
• the etching is a dry etching, such as a reactive ion etching.
• the portions of the protective layer 42 are removed except for the vertically extending regions 44.
• a conventional dry etching technique may be employed.
• Fig. 7 shows the structure of Fig. 6 after another etching has been performed to etch the spacer layer 34 and remove it from the substrate 30 and from over the top surface 40 of the gate electrode 32. This action forms spacers 46 on the gate sidewalls 38 of the gate 32.
• the protective layer 44 on the outer sidewalls 52 of the spacers 46 protects the spacer layer material from being attacked during the etching process.
• the spacers 46 exhibit a rectangular shape or "I-shape".
• the spacers 46 therefore do not present a thin outer region susceptible to punch-through during a source/drain implantation process.
• a source/drain implantation process is performed, as shown in Fig. 8, to create source/drain regions
• the source/drain implant dose profile is precise and does not extend underneath the outer edge of the spacers 46.
• the protective regions 44 are depicted in Fig. 8, this embodiment is exemplary only as in other embodiments, the protective regions 44 are removed as being unnecessary after the etching of the spacer layer 34.
• an improved conformity is provided for further film deposition, such as formation of a second sidewall spacer (shown as second sidewall spacers 54 in dashed lines in Fig. 8).
• conformity is also improved for other film depositions, such as interconnect layer dielectric material. Due to the increased conformity, a thinner film deposition for a second spacer formation may be employed. This makes larger spacers possible for devices with a smaller pitch.
• the present invention thus provides a semiconductor device and method for making the same that exhibits a more controlled source/drain implant dose profile since there is no implantation penetration from the corner of the spacer, and also allows larger spacers for devices with smaller pitch.

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• 2003
  • 2003-12-30 US US10/747,680 patent/US7022596B2/en not_active Expired - Lifetime
• 2004
  • 2004-10-26 EP EP04796395A patent/EP1704588B1/en not_active Expired - Lifetime
  • 2004-10-26 JP JP2006546981A patent/JP2007517398A/ja active Pending
  • 2004-10-26 WO PCT/US2004/035407 patent/WO2005069362A1/en not_active Ceased
  • 2004-10-26 CN CNA2004800375007A patent/CN1894783A/zh active Pending
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  • 2004-10-26 KR KR1020067013138A patent/KR101129712B1/ko not_active Expired - Fee Related
  • 2004-12-21 TW TW093139766A patent/TWI366886B/zh not_active IP Right Cessation

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