KR101129712B1 - 반도체 디바이스용 직사각형 스페이서의 형성 방법 - Google Patents

반도체 디바이스용 직사각형 스페이서의 형성 방법 Download PDF

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Publication number
KR101129712B1
KR101129712B1 KR1020067013138A KR20067013138A KR101129712B1 KR 101129712 B1 KR101129712 B1 KR 101129712B1 KR 1020067013138 A KR1020067013138 A KR 1020067013138A KR 20067013138 A KR20067013138 A KR 20067013138A KR 101129712 B1 KR101129712 B1 KR 101129712B1
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KR
South Korea
Prior art keywords
spacers
spacer layer
sidewalls
gate electrode
protective layer
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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KR1020067013138A
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English (en)
Korean (ko)
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KR20060112676A (ko
Inventor
후이카이 종
스리칸테스와라 닥쉬나-멀씨
Original Assignee
글로벌파운드리즈 인크.
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Application filed by 글로벌파운드리즈 인크. filed Critical 글로벌파운드리즈 인크.
Publication of KR20060112676A publication Critical patent/KR20060112676A/ko
Application granted granted Critical
Publication of KR101129712B1 publication Critical patent/KR101129712B1/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020067013138A 2003-12-30 2004-10-26 반도체 디바이스용 직사각형 스페이서의 형성 방법 Expired - Fee Related KR101129712B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/747,680 US7022596B2 (en) 2003-12-30 2003-12-30 Method for forming rectangular-shaped spacers for semiconductor devices
US10/747,680 2003-12-30
PCT/US2004/035407 WO2005069362A1 (en) 2003-12-30 2004-10-26 A method for forming rectangular-shape spacers for semiconductor devices

Publications (2)

Publication Number Publication Date
KR20060112676A KR20060112676A (ko) 2006-11-01
KR101129712B1 true KR101129712B1 (ko) 2012-03-28

Family

ID=34710826

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020067013138A Expired - Fee Related KR101129712B1 (ko) 2003-12-30 2004-10-26 반도체 디바이스용 직사각형 스페이서의 형성 방법

Country Status (8)

Country Link
US (1) US7022596B2 (enExample)
EP (1) EP1704588B1 (enExample)
JP (1) JP2007517398A (enExample)
KR (1) KR101129712B1 (enExample)
CN (1) CN1894783A (enExample)
DE (1) DE602004024234D1 (enExample)
TW (1) TWI366886B (enExample)
WO (1) WO2005069362A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050156229A1 (en) * 2003-12-16 2005-07-21 Yeap Geoffrey C. Integrated circuit device and method therefor
DE102005020133B4 (de) * 2005-04-29 2012-03-29 Advanced Micro Devices, Inc. Verfahren zur Herstellung eines Transistorelements mit Technik zur Herstellung einer Kontaktisolationsschicht mit verbesserter Spannungsübertragungseffizienz
US9111746B2 (en) * 2012-03-22 2015-08-18 Tokyo Electron Limited Method for reducing damage to low-k gate spacer during etching
KR101986538B1 (ko) 2012-09-21 2019-06-07 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9378975B2 (en) * 2014-02-10 2016-06-28 Tokyo Electron Limited Etching method to form spacers having multiple film layers
KR102394938B1 (ko) * 2015-05-21 2022-05-09 삼성전자주식회사 반도체 소자 및 반도체 소자의 제조 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4488351A (en) * 1983-01-27 1984-12-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
US6004851A (en) * 1997-07-22 1999-12-21 Holtek Microelectronics Inc. Method for manufacturing MOS device with adjustable source/drain extensions
US20030045061A1 (en) * 2001-08-31 2003-03-06 Samsung Electronics Co., Ltd. Method of forming a spacer
US20030227054A1 (en) 2002-06-07 2003-12-11 Fujitsu Limited Semiconductor device and method of manufacturing thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02265250A (ja) * 1989-04-05 1990-10-30 Nec Corp 半導体装置の製造方法
JP3360480B2 (ja) * 1995-04-06 2002-12-24 ソニー株式会社 半導体装置の製造方法
JPH1187703A (ja) * 1997-09-10 1999-03-30 Toshiba Corp 半導体装置の製造方法
JPH11204784A (ja) * 1998-01-09 1999-07-30 Toshiba Corp 半導体装置の製造方法
US6323519B1 (en) * 1998-10-23 2001-11-27 Advanced Micro Devices, Inc. Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process
US6190961B1 (en) * 1999-09-22 2001-02-20 International Business Machines Corporation Fabricating a square spacer
JP4771607B2 (ja) 2001-03-30 2011-09-14 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US6440875B1 (en) * 2001-05-02 2002-08-27 Taiwan Semiconductor Manufacturing Co., Ltd Masking layer method for forming a spacer layer with enhanced linewidth control

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4488351A (en) * 1983-01-27 1984-12-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
US6004851A (en) * 1997-07-22 1999-12-21 Holtek Microelectronics Inc. Method for manufacturing MOS device with adjustable source/drain extensions
US20030045061A1 (en) * 2001-08-31 2003-03-06 Samsung Electronics Co., Ltd. Method of forming a spacer
US20030227054A1 (en) 2002-06-07 2003-12-11 Fujitsu Limited Semiconductor device and method of manufacturing thereof

Also Published As

Publication number Publication date
WO2005069362A1 (en) 2005-07-28
EP1704588B1 (en) 2009-11-18
EP1704588A1 (en) 2006-09-27
CN1894783A (zh) 2007-01-10
US7022596B2 (en) 2006-04-04
TWI366886B (en) 2012-06-21
TW200525693A (en) 2005-08-01
JP2007517398A (ja) 2007-06-28
DE602004024234D1 (de) 2009-12-31
US20050146059A1 (en) 2005-07-07
KR20060112676A (ko) 2006-11-01

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