WO2005055130A1 - 電子装置の製造方法 - Google Patents
電子装置の製造方法 Download PDFInfo
- Publication number
- WO2005055130A1 WO2005055130A1 PCT/JP2004/017939 JP2004017939W WO2005055130A1 WO 2005055130 A1 WO2005055130 A1 WO 2005055130A1 JP 2004017939 W JP2004017939 W JP 2004017939W WO 2005055130 A1 WO2005055130 A1 WO 2005055130A1
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- WIPO (PCT)
- Prior art keywords
- antenna
- chip
- chips
- short
- electronic device
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 claims abstract description 66
- 230000005540 biological transmission Effects 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 114
- 239000012790 adhesive layer Substances 0.000 claims description 72
- 239000011888 foil Substances 0.000 claims description 50
- 229910052751 metal Inorganic materials 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 29
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 19
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 19
- 229910052782 aluminium Inorganic materials 0.000 claims description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 14
- 239000011347 resin Substances 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 14
- -1 polyethylene terephthalate Polymers 0.000 claims description 13
- 238000003825 pressing Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 9
- 229920001721 polyimide Polymers 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229920005668 polycarbonate resin Polymers 0.000 claims description 6
- 239000004431 polycarbonate resin Substances 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 4
- 239000004676 acrylonitrile butadiene styrene Substances 0.000 claims description 3
- 229920000728 polyester Polymers 0.000 claims description 3
- 239000011112 polyethylene naphthalate Substances 0.000 claims description 3
- 239000009719 polyimide resin Substances 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 3
- 241000283707 Capra Species 0.000 claims 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 claims 1
- 238000004891 communication Methods 0.000 abstract description 11
- 239000002313 adhesive film Substances 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 230000005284 excitation Effects 0.000 description 6
- 239000002245 particle Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 241000652704 Balta Species 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 102100025490 Slit homolog 1 protein Human genes 0.000 description 2
- 101710123186 Slit homolog 1 protein Proteins 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- BZHJMEDXRYGGRV-UHFFFAOYSA-N Vinyl chloride Chemical compound ClC=C BZHJMEDXRYGGRV-UHFFFAOYSA-N 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000002788 crimping Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 241000282693 Cercopithecidae Species 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2208—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/29001—Core members of the layer connector
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- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Definitions
- the present invention relates to a non-contact type individual identification device equipped with an IC chip, a method for manufacturing an electronic device which is inexpensive, excellent in productivity, and suitable for obtaining good communication characteristics, and a member used therefor.
- RFID Radio Frequency Identification
- 2.45 GHz microwave-based R FID tags have attracted attention because of the feature that a communication distance of several meters is possible with the structure in which an external antenna is attached to the IC chip.
- Systems are being constructed for the purpose of merchandise distribution, product management, and product history management.
- Examples of the RFID tag of the radio wave method using the microwave include, for example, a tag using a TCP (Tape Carrier Package) type inlet developed by Hitachi, Ltd. and Neisse / Renesas Technology Co., Ltd.
- TCP Transmission Carrier Package
- one IC chip with all external electrodes formed on the same surface is mounted on a tape carrier consisting of a polyimide substrate and a copper antenna circuit continuously.
- the TAB (Tape Automated Bonding) method is adopted (Susumu Kayama and Kunihiko Naruse, "1 ⁇ 1 Packaging Technology (Top), (Bottom)", Nikkei Business Publications, 1993).
- TAB Transmission Automated Bonding
- FIG. 1 first, as shown in FIG. 1 (a), an IC chip 110 in which all external electrodes are formed on the same surface on which a gold bump 104 is formed on a circuit surface is separated by a die-synthesis. After the shading, it is sucked from the Daishinda film 10 by the vacuum suction device 20. Next, as shown in FIG. 1 (b), the wafer is transferred to the vacuum suction station 30 so that the gold bumps 104 of the IC chip 110 on which all the external electrodes are formed on the same surface are on the surface. Next, as shown in FIG. 1 (c), the vacuum suction station 30 is turned upside down so that the gold bump 104 is on the lower surface.
- the heater 40 After positioning the IC chip 110 on which all external electrodes are formed on the same surface at a predetermined position on an antenna substrate 500 manufactured by processing a copper foil of a polyimide base material with a copper foil into an antenna circuit, the heater 40 And heat-pressed to fix. By applying tin plating or solder plating to a portion of the antenna circuit 501 connected to the gold bump, a connection made of a gold-tin alloy can be obtained.
- the gap between the IC chip 110 having all the external electrodes formed on the same surface and the antenna substrate 500 is sealed with a thermosetting resin 600.
- the state in which the thermosetting resin has been cured is an intermediate form of an RFID tag called an inlet. By storing this inlet in a label or thin case, it can be used as an RFID tag.
- FIG. 10 Other inlet structures include, for example, Usami of Hitachi, Ltd., in which an IC chip in which external electrodes of an IC chip are formed one on each of a pair of opposing surfaces is formed on each surface.
- a glass diode package structure in which a dipole antenna is connected to each of the external electrodes has been developed (Japanese Patent Application Laid-Open No. 2002-269520).
- the antenna uses the IC.
- a sandwich 'antenna structure' has been developed that sandwiches each external electrode, one on each side of a set of opposing chips (ISSCC Digest of Technical Papers, pp. 398-399, 2003) .
- the dipole antenna structure having the excitation slit can match the antenna impedance with the input impedance of the IC chip, thereby improving the communication distance.
- the two external electrodes of the IC chip are connected to the antenna across the excitation slit to form a resonance circuit.
- IC chips with all external electrodes formed on the surface It is necessary to accurately align the two external electrodes for force with the slit. For this reason, conventionally, one IC chip was mounted on the antenna substrate one by one using the TAB method shown in FIG. 1, and in the 1S TAB method, all of the IC chips were mounted on the same surface by a vacuum suction device from the die cinda film.
- Adsorption of the IC chip with external electrodes formed thereon, positioning of the IC chip with all external electrodes formed on the same surface and the antenna substrate, heat-compression bonding, and resin sealing are performed on the same surface.
- the above-described antenna has two external electrodes opposed to each other.
- a pair of IC chips are formed one on each surface.
- An external electrode formed on each surface of the IC chip is sandwiched.
- the use of a structure eliminates the need for high-precision alignment between the excitation slit and each external electrode formed on each surface of the IC chip, but the conventional production method using the TAB method If the size of the IC chip, which is formed one by one on each set of two external electrodes facing each other, is reduced to 0.4 mm or less, the conventional vacuum suction device This makes it difficult to mass-produce the inlet and reduce the cost.
- the present invention has been made in view of the above, and provides a method of manufacturing an electronic device which is inexpensive, has excellent productivity, and can obtain good communication characteristics, and a member used therefor.
- the present invention is as follows.
- the method of manufacturing an electronic device provided with If at least one IC chip is aligned with a predetermined position on the corresponding antenna circuit to be mounted, the antenna can be aligned without high-precision alignment with the remaining IC chips.
- a method for manufacturing an electronic device comprising at least a step of heating and press-fitting a package on an IC chip and an antenna substrate.
- the number of IC chips arranged in the width direction of the antenna substrate is one by one, and the number of IC chips that can be simultaneously heat-pressed is one.
- An electronic device having at least a step of aligning with a row of antenna circuits and a step of collectively heating and pressing a short-circuiting plate on the IC chip and the antenna substrate via an anisotropic conductive adhesive layer. Manufacturing method.
- At least one of the first and second metal foils is supported on a base substrate made of an organic resin, and the organic resin is Vinyl chloride resin (PVC), acrylonitrile butadiene styrene (ABS), polyethylene terephthalate (PET), glycol-modified polyethylene terephthalate (PETG), polyethylene naphthalate (PEN), polycarbonate resin (PC), biaxially oriented polyester (O — A method for manufacturing an electronic device, wherein the method is selected from PET) and polyimide resin.
- PVC Vinyl chloride resin
- ABS acrylonitrile butadiene styrene
- PET polyethylene terephthalate
- PET glycol-modified polyethylene terephthalate
- PEN polyethylene naphthalate
- PC polycarbonate resin
- O biaxially oriented polyester
- a method for manufacturing an electronic device comprising:
- An IC chip formed on each of a pair of surfaces facing the external electrodes, a transmitting / receiving antenna having a slit formed therein, and a short circuit for electrically connecting the IC chip to the antenna.
- An IC chip formed on each of a pair of surfaces facing the external electrodes, a transmitting / receiving antenna having a slit formed therein, and a short circuit for electrically connecting the IC chip and the antenna.
- a member in an electronic device having a plate and an external electrode of the IC chip, Forming an anisotropic conductive adhesive layer on each surface of the semiconductor chip, and the IC chip is sandwiched between the anisotropic conductive adhesive layers;
- the plurality of IC chips are arranged at the same intervals as when they are arranged at predetermined positions on the plurality of antenna circuits to be mounted.
- a method of aligning at least one of a column and a row in which a number of the IC chips are aligned and collectively aligning a plurality of the IC chips is performed by reducing a number of recesses having dimensions enough to accommodate the IC chips.
- a method of manufacturing an electronic device comprising: a method of vibrating a jig using about ten thousand formed jigs so that the above-described IC chip on the jig is accommodated in each recess.
- the following effects can be obtained by the method for manufacturing an electronic device of the present invention and the members used for the method.
- the base is required to reduce the production tact time per inlet to about 1 second or less, and to connect the IC chip to the antenna substrate and short-circuit plate via the anisotropic conductive adhesive layer. Since an inexpensive material can be used for the base material and the antenna circuit, a low-cost inlet can be realized.
- FIG. 1 is a diagram for explaining a conventional manufacturing method.
- FIG. 2 is a view showing a structure of an inlet obtained by a production method of the present invention.
- FIG. 3 is a diagram for explaining an example of a method for aligning IC chips according to the present invention.
- FIG. 4 is a manufacturing process diagram for explaining the first embodiment of the present invention.
- FIG. 5 is a manufacturing process diagram for explaining a second embodiment of the present invention.
- an external electrode is formed on each of a pair of surfaces facing each other. And a transmitting / receiving antenna having a slit formed therein, and a short-circuit plate for electrically connecting the IC chip and the antenna.
- FIG. 2A is a schematic view of the RFID tag inlet as viewed from above.
- FIG. 2B is a schematic cross-sectional view taken along the line AA ′ in FIG. 2A. The structure of the inlet will be briefly described with reference to FIG.
- a first external electrode 102 and a second external electrode 103 are formed on each of a pair of opposing surfaces of the IC chip 100, respectively.
- the IC chip 100 is contained in the anisotropic conductive adhesive layer 400 at the first connection portion 2 on the antenna substrate 200 composed of the base substrate 202 and the antenna circuit 201 by the first external electrode 102. They are connected via conductive particles 401.
- the short-circuit plate 300 composed of the base material 302 and the metal foil 301 and the second external electrode 103 of the IC chip 100 are connected at the second connection portion 3, and the short-circuit plate 300 and the antenna substrate 200 are connected.
- the second connection part 3 of the second external electrode 103 of the IC chip and the third connection part 4 on the antenna substrate are connected to each other across a slit 1 formed in the antenna substrate. That is, the first external electrode 102 and the second external electrode 103 of the IC chip are connected to the first connection portion 2, the antenna circuit 201, the third connection portion 4, the metal foil 301 of the short-circuit plate, and the second connection portion. Electrically connected via part 3.
- the gap between the antenna substrate 200 and the short-circuit plate 300 is sealed by a matrix resin 402 of an anisotropic conductive adhesive layer.
- a first example of the method of manufacturing the electronic device according to the present invention includes: an IC chip formed on each of a pair of surfaces having external electrodes facing each other; a transmitting and receiving antenna having a slit formed therein;
- a method of manufacturing an electronic device including an IC chip and a short-circuit plate for electrically connecting the antenna a step of forming a plurality of antenna circuits using a first metal foil, and the step of forming the antenna on a base substrate
- the multiple to be mounted Arranging at least one of a column or a row in which the plurality of IC chips are arranged at the same interval as when arranging the IC chips in a predetermined position on the antenna circuit; Forming a short circuit board with an IC chip on the short circuit board on which the second metal foil is formed so as to be electrically connected to each other via the first anisotropic conductive adhesive layer; Aligning the short-circuiting plate with the IC chip so that the plurality of IC chips are electrically connected to a predetermined position on the antenna circuit; At the same time through a second anisotropic conductive adhesive layer.
- a second example of the method of manufacturing the electronic device according to the present invention includes an IC chip formed on each of a pair of surfaces facing external electrodes, and a transmission / reception antenna formed with a slit.
- a third example of the method of manufacturing the electronic device according to the present invention includes an IC chip formed on each of a pair of surfaces facing external electrodes, and a transmission / reception antenna formed with slits. Forming a plurality of antenna circuits using a first metal foil in a method of manufacturing an electronic device including a short-circuit plate for electrically connecting the IC chip and the antenna.
- the method according to claim 2 further comprising at least a step of aligning the short-circuit plate on which the metal foil is formed, and a step of heat-pressing the short-circuit plate collectively on the plurality of IC chips and the antenna substrate.
- At least one of the first and second metal foils is aluminum. In the first to third examples, at least one of the first and second metal foils is supported by a base material made of organic resin or paper.
- the organic resin is vinyl chloride resin (PVC), acrylonitrile butadiene styrene (ABS), polyethylene terephthalate (PET), glycol-modified polyethylene terephthalate (PETG), polyethylene naphthalate (PEN), polycarbonate resin (PC) And biaxially oriented polyester (O-PET) and polyimide resin.
- a method of forming an antenna substrate for example, a plurality of antenna circuits are formed using a first metal foil, and a force is also provided on a base substrate.
- a method of forming a substrate and a method of forming an antenna substrate by providing a first metal foil on a base material and forming a plurality of antenna circuits by, for example, etching.
- a jig in which several to several tens of thousands of concave portions having a size that can accommodate the IC chips are formed on a metal plate surface is used. It is possible to use a method in which after preparing, supplying the IC chips of the number of the concave portions or more to the jig, and then vibrating the jig, the IC chips are placed in the concave portions.
- FIG. 3 schematically shows an example of a jig used for the alignment method. In FIG. 3, as shown in FIG.
- 61 is a recess for accommodating the IC chip
- 62 is a hole for vacuum suction provided on the bottom of each recess
- 63 is a vacuum. It is a pump.
- FIG. 3 (b) shows the state where the IC chip is supplied on the jig, and Fig. 3 (c) vibrates the jig to remove the excess IC chip after the IC chip is settled in the concave portion. This shows the completion of the alignment.
- a high-speed balta feeder or a parts feeder for arranging chip components such as a chip capacitor and a chip resistor in one line
- chip components such as a chip capacitor and a chip resistor in one line
- a high-speed chip mounter mounted on a printed circuit board or the like is combined.
- a plurality of the IC chips discharged from the high-speed balta feeder are mounted on an antenna circuit to be mounted on a short-circuit plate with an anisotropic conductive adhesive layer using a high-speed chip mounter.
- the IC chip-attached short-circuit plate can be mounted collectively at a predetermined position on the antenna substrate.
- the remaining IC chips can be collectively arranged at a predetermined position on the antenna circuit without performing high-precision alignment.
- short-circuiting is performed such that the number of IC chips that can be collectively heated and pressed together is one piece. Dividing the plate, positioning the short-circuit plate at a predetermined position on the antenna circuit, It is preferable to have a step of collectively heating and pressing the short-circuiting plate on the IC chip and the antenna substrate via the anisotropic conductive adhesive layer since the tact time can be reduced.
- an anisotropic conductive adhesive layer is formed on each surface of the IC chip to which an external electrode is attached, and the IC chip is attached to the anisotropic conductive adhesive. Inlet can be manufactured more efficiently than in this case even if a semiconductor element sandwiched between layers is used in advance.
- a plurality of the IC chips are heat-pressed together with the antenna substrate and the short-circuit plate by heating and pressing the first and second anisotropic conductive adhesive layers.
- the gap between the antenna substrate and the short-circuit plate can be sealed.
- the total thickness of the first and second anisotropic conductive adhesive layers is at least half the thickness of the IC chip, It is preferable because sealing property can be obtained and high reliability can be realized.
- the short-circuit plate is divided into a plurality of pieces before the thermocompression bonding in that the misalignment due to thermal distortion can be prevented.
- an anisotropic conductive adhesive layer is formed on each surface of the IC chip to which an external electrode is attached, and the IC chip is attached to the anisotropic conductive adhesive.
- a short circuit plate may be further provided on one surface of the anisotropic conductive adhesive layer of the semiconductor element sandwiched between the layers in advance. Can be manufactured.
- the second metal foil is simply provided on the base substrate. Since there is no need to perform processing such as etching on the second metal foil, the number of steps can be reduced, tact time can be reduced, and cost can be reduced. Preferred in terms! / ,.
- the short-circuiting plate after the step of heat-pressing the short-circuit plate all together on the IC chip and the antenna substrate via the anisotropic conductive adhesive layer, the short-circuiting plate is continuously! / ⁇ And cutting the antenna circuit into individual pieces.
- the cutting step when the direction of AA in FIG. 2 is defined as a width direction, the short-circuiting plate spans the slit and has a length which is about the IC chip. It is necessary to have a length substantially equal to the width of the antenna circuit in terms of the appearance of the entire inlet.
- the inlet When the inlet is used in the form of an RFID tag, it is preferable to provide cover sheets above and below the inlet in order to protect a circuit and prevent a short circuit or the like.
- the IC chips when a plurality of the IC chips are aligned and fixed to the short-circuit plate and the antenna substrate at a time, the IC chips are mounted one by one. Excellent productivity can be realized. Improving productivity can reduce the tact time per inlet.
- the external electrode on the side of the IC chip in contact with the antenna circuit is formed.
- High-precision alignment of the excitation slit on the antenna circuit with the antenna circuit is not required, and even the rough and positional accuracy of the IC chip aligned by using a sieve or a mold makes it possible to collectively mount the IC chip well on the antenna substrate.
- each electrical connection between the IC chip and the antenna substrate, the short-circuit plate, the short-circuit plate, and the antenna substrate is performed via an anisotropic conductive adhesive layer.
- the connection by the anisotropic conductive adhesive layer is performed by contacting each external electrode formed on each surface of the IC chip as a connected body with conductive particles contained in the anisotropic conductive adhesive layer. It does not require surface plating on the antenna circuit and does not require a high heat-resistant base material that can withstand bonding at high temperatures of 200 ° C or higher to form metal joints. Thus, inexpensive base materials and antenna circuits can be used, and low cost can be achieved.
- an antenna substrate obtained by forming an aluminum antenna circuit on a polyethylene terephthalate base material is a suitable member for manufacturing an inexpensive RFID tag inlet.
- the first anisotropic conductive adhesive layer may be formed on the short-circuit plate in advance, or may be formed on the second external electrode side of the IC chip. Further, the second anisotropic conductive adhesive layer may be formed in advance on the antenna substrate, or may be formed on the first external electrode 102 side of the IC chip.
- the first anisotropic conductive adhesive layer may be formed on the antenna substrate in advance, or may be formed on the first external electrode 102 side of the IC chip. . Further, the second anisotropic conductive adhesive layer may be formed on the short-circuit plate in advance, or may be formed on the IC chip and the antenna circuit.
- the IC chip is Accordingly, the remaining IC chips can be collectively arranged at a predetermined position on the antenna circuit without performing high-precision alignment.
- the method of manufacturing an electronic device includes the steps of: providing an IC chip formed on each of a pair of surfaces facing external electrodes; a transmitting / receiving antenna having a slit formed therein; A method of manufacturing an electronic device, comprising: a short-circuit plate for electrically connecting the at least one IC chip of the aligned plurality of IC chips with a predetermined position on a corresponding antenna circuit to be mounted. A method of manufacturing an electronic device, characterized in that if alignment is performed, the remaining IC chips can be collectively arranged at a predetermined position on the antenna circuit without performing high-precision alignment accordingly. .
- the IC chips are collectively fixed so as to be electrically connected to the short-circuit plate and the antenna substrate.
- Productivity can be dramatically improved.
- FIG. 2 (a) is an embodiment of the present invention, and is a schematic view of an inlet for an RFID tag using the manufacturing method of the present invention as viewed from above.
- FIG. 2B is a schematic cross-sectional view taken along the line AA ′ of FIG. 2A. The structure of the inlet will be briefly described with reference to FIG.
- a first external electrode 102 and a second external electrode 103 are formed on each of a pair of opposing surfaces of the IC chip 100.
- the IC chip 100 is connected to the antenna substrate 200 composed of the base substrate 202 and the antenna circuit 201 by the first external electrode 102 at the first connection portion 2 in the conductive material contained in the anisotropic conductive adhesive layer 400. Connected via particle 401.
- the short-circuit plate 300 composed of the base material 302 and the metal foil 301 and the second external electrode 103 of the IC chip 100 are at the second connection portion 3, and the short-circuit plate 300 and the antenna substrate 200 are at the second connection portion 3.
- connection portion 3 are connected to each other via the conductive particles 401 at the connection portion 4. That is, the second connection portion 3 of the second external electrode 103 of the IC chip and the third connection portion 4 on the antenna substrate are connected to each other across the slit 1 formed on the antenna substrate. . That is, the first external electrode 102 and the second external electrode 103 of the IC chip are connected to the first connection part 2, the antenna circuit 201, the third connection part 4, the metal foil 301 of the short-circuit plate, and the second connection part. Are electrically connected via the connection part 3 of the Further, the gap between the antenna substrate 200 and the short-circuit plate 300 is sealed by a matrix resin 402 of an anisotropic conductive adhesive layer.
- the antenna circuit 201 is formed continuously using an aqueous ferric chloride solution as an etching solution.
- the width of the antenna per antenna circuit was 2.5 mm
- the slit width was 0.5 mm
- the pitch of the antenna circuits was 3 mm. Due to space limitations, only B is shown in the following process.
- external electrodes are formed on each of a pair of facing surfaces.
- IC chips 100 each 0.4 mm in height and 0.15 mm in thickness were prepared, and a concave part of the size that fits the IC chip on the surface of the metal plate was placed horizontally (in the width direction with respect to the direction of progress of the manufacturing line).
- a jig was prepared for a total of 2,000 pieces, each of which had 40 pieces at a pitch of 3 mm and 50 pieces at a pitch of 2 mm (vertical direction of the production line).
- the jig was vibrated for about 60 seconds, so that the IC chips were placed in the respective recesses and aligned.
- a hole for vacuum suction is provided on the bottom surface of each concave portion, and the vacuum suction is performed together with the vibration of the jig, so that the IC chip once accommodated in the concave portion is prevented from falling off by further vibration, Further, after the IC chip was set in the recess, the excess IC chip was removed with a brush.
- an anisotropic conductive adhesive film 400 (AC-2052P-45 (manufactured by Hitachi Chemical Co., Ltd.)) having a width of 110 mm is laminated at 80 ° C, and the separator film is peeled off to form an anisotropic conductive adhesive layer. Formed.
- the jig is turned upside down while vacuum suction of the IC chip is stopped, and the vacuum suction is stopped, so that one of the surfaces of the 2,000 IC chips with external electrodes is attached. It was arranged in a state where it was arranged in a lump at the bottom.
- the anisotropic conductive adhesive film having the width is provided on the external electrode surface opposite to the external electrode on the short-circuit plate side of the aligned IC chips.
- the separator film was peeled off to form an anisotropic conductive adhesive layer, and the above-mentioned short circuit board with IC chip was obtained.
- each surface of the IC chip with the external electrode is sandwiched by the anisotropic conductive adhesive layer.
- the short-circuit plate with the IC chip was cut so as to be mounted in the width direction of the antenna substrate with a width of 2 mm, and 40 IC chips were arranged in a row at a pitch of 3 mm.
- the short-circuit boards with IC chips arranged in a row was divided into the short-circuit boards with IC chips arranged in a row.
- the force on the anisotropic conductive adhesive layer of the divided short-circuit plate with an IC chip is also transmitted.
- the IC chip of the short circuit board with the IC chip was temporarily fixed in a direction in which the IC chip was connected to the antenna substrate.
- only one IC chip A CCD camera and an image processing device are used to align with a predetermined position on the antenna circuit, and accordingly, the remaining 39 IC chips are also aligned with high accuracy using the camera and the device. It is possible to collectively arrange them at a predetermined position on the antenna circuit without performing any operation.
- the crimping head was lowered from the short-circuit plate side, and under the conditions of a pressure of 3 MPa, a temperature of 180 ° C, and a heating time of 15 seconds, the short-circuit plate with the IC chip was arranged in the width direction of the antenna substrate. Heat and pressure were applied collectively to predetermined positions for the rows, and the gap between the antenna substrate and the short-circuit plate was sealed. Subsequently, the remaining 49 rows were heat-pressed to the antenna substrate through the same process.
- a protrusion corresponding to the thickness of the IC chip is formed at a predetermined position on the pressure bonding head so that the connection between the IC chip and the antenna substrate and the short circuit plate and the connection between the short circuit plate and the antenna substrate can be performed simultaneously.
- Fig. 4 (g) each piece was cut using a press cutter to obtain an inlet structure having the shape shown in Fig. 2.
- the time required for aligning the IC chip was 0.03 seconds per inlet, and the time required for connecting the short-circuit plate with the IC chip to the antenna substrate was per inlet. It was 0.375 seconds.
- the tact time per inlet can be further reduced.
- the mounting position accuracy of the IC chip was within ⁇ 0.3 mm from a predetermined position, and assembly failure and communication failure due to displacement were strong.
- the antenna circuit 201 is continuously formed using a ferric chloride aqueous solution as an etching solution.
- the width of the antenna per antenna circuit was 2.5 mm
- the slit width was 0.5 mm
- the pitch of the antenna circuits was 3 mm. Due to space limitations, only the portion B 'is shown in the following steps.
- an anisotropic conductive adhesive film 400 (AC-2052P-45 (manufactured by Hitachi Chemical Co., Ltd.) having a width of 2 mm was placed at a predetermined position on the antenna circuit. ) was laminated at 80 ° C and the separator film was peeled off to form an anisotropic conductive adhesive layer.
- IC chips 100 each having a thickness of 0.4 mm and a thickness of 0.15 mm each formed on a pair of surfaces facing the external electrodes were formed.
- a total of 2000 jigs were prepared.
- the jigs were vibrated for about 60 seconds, so that the IC chips were placed in each recess and aligned.
- a hole for vacuum suction is provided on the bottom surface of each concave portion, and by performing vacuum suction together with the vibration of the jig, the IC chip once settled in the concave portion is obtained.
- the IC chip was prevented from falling off by further vibration, and after the IC chip was set in the concave portion, the excess IC chip was removed with a brush.
- the jig was turned upside down while only 40 of the aligned IC chips in one horizontal row were suctioned, and the CCD camera and image processing were performed. It was temporarily fixed by positioning it at a predetermined position on the antenna circuit using the device and stopping the vacuum suction. At this time, only one IC chip needs to be aligned with a predetermined position on the antenna circuit using a CCD camera and an image processing device, and accordingly, the camera and the device are also used for the remaining 39 IC chips.
- the antenna can be collectively arranged at a predetermined position on the antenna circuit without performing high-accuracy alignment using the antenna.
- a 9 mm thick aluminum foil was bonded to a 50 ⁇ m thick polyethylene terephthalate base material with an adhesive, and a 2 mm wide tape-shaped base material was attached.
- the short-circuiting plate with the anisotropic conductive adhesive layer and the antenna substrate were aligned at predetermined positions based on the external dimensions and temporarily fixed. Subsequently, the pressure bonding head was lowered from the short-circuit plate side with the anisotropic conductive adhesive layer, and the short-circuit plate with the anisotropic conductive adhesive layer was mounted on the antenna substrate under the conditions of a pressure of 3 MPa, a temperature of 180 ° C, and a heating time of 15 seconds. One row of the IC chips and the antenna circuit arranged in the width direction were heat-pressed together at a predetermined position, and a gap between the antenna substrate and the short-circuit plate was sealed.
- a protrusion corresponding to the thickness of the IC chip is formed at a predetermined position on the pressure bonding head so that the connection between the IC chip and the antenna substrate and the short circuit plate and the connection between the short circuit plate and the antenna substrate can be performed at the same time.
- each piece was cut into individual pieces by using a press cutter, and an inlet having a shape shown in FIGS. 2 and 3 was obtained.
- the time required for alignment of the IC chips was 0.03 seconds per inlet, and the time required to connect the short-circuit plate to the antenna substrate was required. The time was 0.375 seconds per inlet.
- the mounting position accuracy of the IC chip was within ⁇ 0.3 mm from a predetermined position, and there was no assembly failure or communication failure due to positional displacement. . That is, in the method in which the IC chips are arranged at regular intervals with the arrangement of the corresponding antenna circuits to be mounted on the short-circuiting plate, and the number of IC chips that can be heat-pressed together is divided into one piece.
- the IC chip or the anisotropic conductive adhesive layer may be provided on the antenna circuit.
- the antenna substrate is processed using the same steps as in the second embodiment, and the anisotropic conductive adhesive film is laminated on an antenna circuit to form an anisotropic conductive film.
- a conductive adhesive layer is formed, an IC chip formed on each of a pair of surfaces facing the external electrodes is aligned, and the IC chip is placed at a predetermined position on an antenna circuit. Temporarily fixed collectively to one row arranged in the width direction of the antenna substrate.
- the anisotropic conductive adhesive film having the same width as the laminated anisotropic conductive adhesive film was laminated at 80 ° C. on the temporarily fixed IC chip, and the separator film was peeled off to remove the anisotropic conductive adhesive film. An adhesive layer was formed.
- a tape-shaped base material having a width of 2 mm was prepared by bonding an aluminum foil having a thickness of 9 ⁇ m to a polyethylene terephthalate base material having a thickness of 50 ⁇ m with an adhesive, and this was used as a short-circuit plate. With the aluminum foil side of the short-circuiting plate facing the IC chip, the short-circuiting plate was aligned and temporarily fixed so as to overlap the anisotropic conductive adhesive film based on the external dimensions.
- the crimping head was lowered from the short-circuit plate side, and the short-circuit plate was divided into one row of the IC chip and the antenna circuit arranged in the width direction of the antenna substrate under the conditions of a pressure of 3 MPa, a temperature of 180 ° C., and a heating time of 15 seconds.
- they were heat-pressed together at a predetermined position and the gap between the antenna substrate and the short-circuit plate was sealed.
- the remaining 49 rows were heat-pressed to the antenna substrate through the same process.
- a protrusion corresponding to the thickness of the IC chip is formed at a predetermined position on the pressure bonding head so that the connection between the IC chip and the antenna substrate and the short circuit plate and the connection between the short circuit plate and the antenna substrate can be performed simultaneously.
- each individual piece was cut using a press cutter to obtain an inlet structure having a shape shown in Figs. 2 and 4.
- the time required for alignment of the IC chips is 0.03 seconds per inlet, and the short-circuit plate is connected to the antenna substrate.
- the time required for each inlet was 0.375 seconds.
- the mounting position accuracy of the IC chip is within ⁇ 0.3 mm from a predetermined position, and there is no assembly failure and communication failure due to positional displacement.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Credit Cards Or The Like (AREA)
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Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04819892A EP1830309A4 (en) | 2003-12-05 | 2004-12-02 | METHOD FOR PRODUCING ELECTRONIC EQUIPMENT |
JP2005515960A JP4353181B2 (ja) | 2003-12-05 | 2004-12-02 | 電子装置の製造方法 |
US10/581,721 US8273605B2 (en) | 2003-12-05 | 2004-12-02 | Manufacturing method for electronic device having IC chip and antenna electrically connected by bridging plate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2003-407182 | 2003-12-05 | ||
JP2003407182 | 2003-12-05 |
Publications (1)
Publication Number | Publication Date |
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WO2005055130A1 true WO2005055130A1 (ja) | 2005-06-16 |
Family
ID=34650298
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/017939 WO2005055130A1 (ja) | 2003-12-05 | 2004-12-02 | 電子装置の製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8273605B2 (ja) |
EP (1) | EP1830309A4 (ja) |
JP (1) | JP4353181B2 (ja) |
KR (1) | KR100895567B1 (ja) |
CN (1) | CN100562889C (ja) |
TW (1) | TW200527311A (ja) |
WO (1) | WO2005055130A1 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7230580B1 (en) * | 2003-08-29 | 2007-06-12 | National Semiconductor Corporation | Design of a two interconnect IC chip for a radio frequency identification tag and method for manufacturing same |
WO2005069205A1 (ja) * | 2004-01-15 | 2005-07-28 | Hitachi Chemical Co., Ltd. | 電子装置の製造方法 |
JP4992465B2 (ja) * | 2007-02-22 | 2012-08-08 | 富士通株式会社 | Rfidタグおよびrfidタグの製造方法 |
JP5299749B2 (ja) * | 2008-03-19 | 2013-09-25 | Nec東芝スペースシステム株式会社 | 広帯域給電回路及びそれを備えたスロットアンテナ |
KR101288165B1 (ko) * | 2011-08-29 | 2013-07-18 | 삼성전기주식회사 | 바이오칩 스탬핑 장치 및 스탬핑 방법 |
JP6179843B2 (ja) * | 2012-12-04 | 2017-08-16 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 実装装置及び実装方法 |
JP2015053418A (ja) * | 2013-09-09 | 2015-03-19 | 株式会社東芝 | 半導体製造装置 |
JP6212011B2 (ja) * | 2014-09-17 | 2017-10-11 | 東芝メモリ株式会社 | 半導体製造装置 |
JP6442707B2 (ja) * | 2015-04-09 | 2018-12-26 | パナソニックIpマネジメント株式会社 | 部品実装装置及び部品実装方法 |
WO2016179023A1 (en) * | 2015-05-01 | 2016-11-10 | Adarza Biosystems, Inc. | Methods and devices for the high-volume production of silicon chips with uniform anti-reflective coatings |
JP2019032733A (ja) * | 2017-08-09 | 2019-02-28 | 日本メクトロン株式会社 | 貼付タグ、タグシステム |
JP7082874B2 (ja) * | 2017-12-26 | 2022-06-09 | ヤマシンフィルタ株式会社 | フィルタ装置 |
TWI684135B (zh) * | 2018-07-17 | 2020-02-01 | 昱盛國際企業股份有限公司 | 智能膠帶及使用其的物流系統 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5027107A (en) | 1988-07-06 | 1991-06-25 | Hitachi, Ltd. | Frequency sensor |
JP2001217380A (ja) * | 2000-02-04 | 2001-08-10 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002190003A (ja) * | 2000-12-21 | 2002-07-05 | Hitachi Ltd | Icモジュールの製造方法 |
JP2004127230A (ja) * | 2002-08-08 | 2004-04-22 | Renesas Technology Corp | 半導体装置、半導体装置の製造方法、電子商取引方法及びトランスポンダ読み取り装置 |
JP2004363415A (ja) * | 2003-06-06 | 2004-12-24 | Hitachi Ltd | 無線認識半導体装置および無線認識半導体装置製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4433629B2 (ja) * | 2001-03-13 | 2010-03-17 | 株式会社日立製作所 | 半導体装置及びその製造方法 |
JP2002366917A (ja) * | 2001-06-07 | 2002-12-20 | Hitachi Ltd | アンテナを内蔵するicカード |
US7204425B2 (en) * | 2002-03-18 | 2007-04-17 | Precision Dynamics Corporation | Enhanced identification appliance |
JP4177241B2 (ja) * | 2003-12-04 | 2008-11-05 | 株式会社日立情報制御ソリューションズ | 無線icタグ用アンテナ、無線icタグ及び無線icタグ付き容器 |
-
2004
- 2004-12-02 CN CNB2004800358459A patent/CN100562889C/zh not_active Expired - Fee Related
- 2004-12-02 JP JP2005515960A patent/JP4353181B2/ja not_active Expired - Fee Related
- 2004-12-02 EP EP04819892A patent/EP1830309A4/en not_active Withdrawn
- 2004-12-02 KR KR1020067013553A patent/KR100895567B1/ko not_active IP Right Cessation
- 2004-12-02 WO PCT/JP2004/017939 patent/WO2005055130A1/ja active Application Filing
- 2004-12-02 US US10/581,721 patent/US8273605B2/en not_active Expired - Fee Related
- 2004-12-03 TW TW093137524A patent/TW200527311A/zh not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5027107A (en) | 1988-07-06 | 1991-06-25 | Hitachi, Ltd. | Frequency sensor |
JP2001217380A (ja) * | 2000-02-04 | 2001-08-10 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002190003A (ja) * | 2000-12-21 | 2002-07-05 | Hitachi Ltd | Icモジュールの製造方法 |
JP2004127230A (ja) * | 2002-08-08 | 2004-04-22 | Renesas Technology Corp | 半導体装置、半導体装置の製造方法、電子商取引方法及びトランスポンダ読み取り装置 |
JP2004363415A (ja) * | 2003-06-06 | 2004-12-24 | Hitachi Ltd | 無線認識半導体装置および無線認識半導体装置製造方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1830309A4 * |
Also Published As
Publication number | Publication date |
---|---|
EP1830309A4 (en) | 2009-05-13 |
JPWO2005055130A1 (ja) | 2007-12-06 |
EP1830309A1 (en) | 2007-09-05 |
KR20060105880A (ko) | 2006-10-11 |
TW200527311A (en) | 2005-08-16 |
KR100895567B1 (ko) | 2009-04-29 |
US8273605B2 (en) | 2012-09-25 |
CN1890678A (zh) | 2007-01-03 |
JP4353181B2 (ja) | 2009-10-28 |
TWI296392B (ja) | 2008-05-01 |
US20110133345A1 (en) | 2011-06-09 |
CN100562889C (zh) | 2009-11-25 |
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