Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/26—Testing of individual semiconductor devices
  • G01R31/2607—Circuits therefor
  • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G01R19/175—Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/26—Testing of individual semiconductor devices
  • G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/26—Testing of individual semiconductor devices
  • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
  • G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the invention relates to an electronic circuit, a circuit test arrangement and a method for determining the operability of an electronic circuit.
• the reliability of a gate oxide in an integrated semiconductor component with a field effect transistor reaches intrinsic load limits as the scaling progresses, particularly when developing transistors with increasingly thin layers and increasing operating field strengths in spite of lower operating voltages.
• the statistical nature of the dielectric breakdown of a gate oxide leads to a broader statistical spread of the service life of the respective semiconductor component.
• the predicted service life of the semiconductor components is reduced by means of area scaling and can no longer be reliably predicted.
• a dielectric breakdown is characterized by a significantly smaller increase in the leakage current in the case of a thin dielectric than in the case of a thicker dielectric layer.
• the only slight increase in the leakage current in many circuitry applications only leads to an increase in the power loss in the electronic circuit, but not necessarily to a malfunction, i.e. to a failure of the entire electronic circuit.
• Circuitry evaluate the first small change in gate current flowing through the gate oxide, but not actually relevant malfunction of the electronic circuit or the electronic circuit in the relevant circuit environment.
• a breakthrough event also referred to as a breakdown event, must result in a significant current surge above the base level of the electronic load current
• Circuit hereinafter also referred to as the stress current of the electronic circuit, in order to be detected with sufficient certainty.
• the maximum active area of the entire test structure is according to the state of FIG.
• Gate oxide in transistors in an electronic circuit the failure of one or more transistors in the electronic circuit due to a breakdown in the respective gate oxide of a field effect transistor does not necessarily lead to the failure of the functionality of the entire electronic circuit compared to the desired function of the electronic circuit.
• [1] and [2] describe a ring oscillator structure with 47 inverters connected to form a ring, an inverter being designed as a NAND gate.
• a frequency divider circuit is connected downstream of the ring oscillator.
• the circuit arrangement consisting of ring oscillator and frequency divider circuit would be subjected to a load by applying an electrical voltage and the behavior of the function of the circuit arrangement would be examined.
• [3] describes the influence of a gate oxide breakdown in a field effect transistor in an SRAM memory cell (Static Random Access Memory memory cell).
• Polarity of the applied stress voltage Depending on the polarity of the applied stress voltage, either the respective NMOS field effect transistor or the respective PMOS transistor is subjected to greater stress and destroyed earlier.
• an NMOS field effect transistor to be tested with a gate oxide with a layer thickness of 1.7 n is described in [5], to the gate connection of which a PMOS field effect transistor with a thicker gate oxide is connected.
• the stress voltage is applied to the drain connection of the PMOS field effect transistor.
• a leakage current was measured after a breakdown of the gate oxide in the NMOS field effect transistor, which was less than 100 ⁇ A, at a stress voltage of 3.4 volts and a current driver capability of less than 200 ⁇ A.
• the behavior of the gate oxide in the NMOS field effect transistor when the stress voltage was applied to the PMOS field effect transistor was investigated in isolation.
• [6] discloses an integrated circuit arrangement in MOS technology with field effect transistors, which has a circuit arrangement for the rapid testing of various blocks of the circuit.
• This circuit arrangement has three transistor switch groups.
• a first transistor switch group is used for testing an input block.
• a second transistor switch group is used to switch the input block and an output block on and off so that the blocks can be tested together, and a third block for testing the output block.
• [7] discloses an electrically erasable and programmable read-only memory with a NAND cell structure, which has memory cells (M) which are arranged on an N substrate.
• the memory cells are divided into NAND cell blocks, each of which has series-connected memory cell transistor arrays (M1 to M4).
• Each of the transistors has a floating gate (50), a control gate which is connected to a word line (Li) and an N-type diffusion layers (68, 70) which serve as corresponding sources and drains.
• the invention is based on the problem of determining the reliability of a gate insulation layer of a field effect transistor, with a product-relevant statement regarding the reliability of an electronic circuit which the respective field-effect transistor is enabled without being subject to the restriction with regard to the area limitation, as is given according to the prior art.
• An electronic circuit has a test signal input connection for applying a test input signal.
• a test signal output connection is also provided, at which a test output signal can be provided.
• a plurality of test circuit blocks are connected between the test signal input connection and the test signal output connection, each test circuit block having at least one first sub-circuit block and at least one second sub-circuit block. This means that a test input signal applied to the test signal input connection runs through it in accordance with the configuration of the test circuit blocks or is processed by it in accordance with the functionality of the test circuit blocks and is output to the
• Test output connection is provided as a test output signal.
• the coupling of the test circuit blocks on the input side to the test signal input connection and on the output side to the test signal output connection thus ensures that the functionality of the test circuit blocks can be tested by means of the test input signal.
• the first sub-circuit block of each test circuit block contains at least one first field effect transistor with a gate insulation layer.
• the second sub-circuit block of each test circuit block there is at least one second field effect transistor with a gate insulation layer contain.
• the gate insulation layer of the first field effect transistor is thicker than the gate insulation layer of the second field effect transistor.
• Functionality of an electronic circuit has the electronic circuit described above and a test input signal generation unit for generating a test input signal to be fed to the test signal input connection, and a test output signal evaluation unit with which the functionality of the electronic circuit can be determined. Furthermore, an operating voltage source is provided for providing an operating voltage with which the electronic circuit is operated.
• test input signal is applied to the test signal input connection and the associated one
• Test output signal is tapped at the test signal output connection. Using the test output signal, it is determined whether the electronic circuit is functional or not.
• test circuit blocks arranged one behind the other not only is an individual transistor checked for its functionality in the electronic circuit, but the functional target behavior of the entirety of the test circuit blocks is tested. In this way, product-relevant information regarding the functionality of a product with integrated semiconductor components is guaranteed.
• the different thickness of the gate insulation layers in the respective sub-circuit blocks of the test circuit blocks ensures that only the respective second field effect transistor, ie the field effect transistor with the thin gate insulation layer, is effectively tested and loaded with regard to a gate insulation layer breakdown and the gate insulation layer of the first field effect transistor, ie the field effect transistor with the thicker gate Insulation layer itself is not tested for a possible gate insulation layer breakdown, since the probability of a gate insulation layer breakdown is significantly less with the first field effect transistor than with the second field effect transistor.
• the first field effect transistor thus clearly represents a source of stress, in other words a driver for the second field effect transistor.
• the first sub-circuit block represents a stress source or a driver for the second sub-circuit block.
• the first field effect transistor generally the first sub-circuit block, clearly serves for signal conditioning and only the second field effect transistor, clearly the second sub-circuit block, is tested for the occurrence of a possible gate insulation layer breakdown.
• the gate insulation layer of the first field effect transistor is thicker than the gate insulation layer of the second field effect transistor by at least a factor 1.2, particularly preferably by at least a factor 1.3.
• Field effect transistor is at least a factor 1000 greater than the service life of the second field effect transistor, which ensures statistically certain that essentially only the gate insulation layer of the second field effect transistor breaks through with a corresponding load by an operating voltage applied to the electronic circuit. This ensures that the first sub-circuit block represents a reliable source of stress for the second sub-circuit block for signal conditioning of the test input signal.
• the layer thickness of the gate insulation layer of the second field effect transistor is less than 5 nm, particularly preferably less than 2 nm.
• the invention is particularly suitable for so-called thin oxide
• the first field effect transistor thus preferably has a gate insulation layer at least a thickness of 6 nm.
• the gate insulation layer of the first field effect transistor With a layer thickness of the gate insulation layer of the second field effect transistor of 2 nm, the gate insulation layer of the first
• Field effect transistor preferably has a layer thickness of at least 2.4 nm.
• the field effect transistors can be MOS field effect transistors (metal oxide semiconductor field effect transistors), particularly preferably CMOS field effect transistors (complementary metal oxide semiconductor field effect transistors).
• MOS field effect transistors metal oxide semiconductor field effect transistors
• CMOS field effect transistors complementary metal oxide semiconductor field effect transistors
• the gate insulation layers are preferably formed from oxide material, particularly preferably from silicon dioxide, alternatively from a dielectric with a higher dielectric constant, such as one or more transition metal oxides, e.g. Aluminum oxide (AI2O3), hafnium oxide (Hf ⁇ 2), and their silicates.
• oxide material particularly preferably from silicon dioxide
• dielectric with a higher dielectric constant such as one or more transition metal oxides, e.g. Aluminum oxide (AI2O3), hafnium oxide (Hf ⁇ 2), and their silicates.
• the at least one first sub-circuit block and the at least one second sub-circuit block are coupled to one another in series in the respective test circuit block.
• the at least one first sub-circuit block and / or the at least one second sub-circuit block contain / contains at least one inverter.
• each sub-circuit block ensures that on the one hand signal processing is carried out in the test circuit block, but on the other hand that the respective sub-output signal which is present at the output of the respective test circuit block has the same polarity as the partial input signal present at the respective test circuit block.
• inverters makes it possible to also readily detect the switching from a first signal level to a second signal level, for example a transition from a level of 3 volts, generally a high level, to a level of 0 volts, in general a low level, and vice versa.
• the first sub-circuit block consists of a first inverter in which both field effect transistors, i.e. a PMOS field effect transistor and an NMOS field effect transistor thick gate insulation layers, i.e. have thick gate oxides.
• the second sub-circuit block of each test circuit block is formed from exactly one inverter, the respective NMOS field effect transistor and the respective PMOS field effect transistor having a thin gate oxide layer, generally a thin gate insulation layer preferably of a maximum thickness of 5 nm.
• the second sub-circuit block is preferably connected downstream of the first sub-circuit block in the respective test circuit block.
• each test circuit block has a two-stage inverter, preferably a two-stage CMOS inverter, in which the first inverter stage with a thicker gate oxide and the second inverter stage with the thinner gate oxide to be assessed, ie to be tested, or a gate dielectric is designed with high dielectric constants.
• the two inverter chains with different oxide thicknesses ie a first inverter chain which is formed from the first sub-circuit blocks and a second inverter chain which is formed from the second sub-circuit blocks, are preferably interleaved.
• the upstream first inverter stage represents a product-like control of the tested inverter stage, which ensures the product relevance of the results obtained in the course of testing the electronic circuit.
• the first subcircuit block also has the task of compensating for the inverter function of the second inverter stage, without being itself essential for breakdown distribution, i.e. to contribute to the statistical distribution of the occurrence of breakdowns in the gate insulation layers. This is achieved in that the first inverter stage is implemented in a thicker gate oxide. The technology required for this is provided in standard processes in standard technology generations today.
• the level inversion ie the inversion of the respective electrical voltage which is present at the respective sub-circuit block, by the first inverter stage ensures that each inverter stage is loaded with transistors with thin gate oxide with the same electrical voltage.
• all NMOS field effect transistors or all PMOS field effect transistors can be selected for loading.
• the buffer chain clearly represents a simple integrated circuit on which a basic logical function can be tested.
• test output signal evaluation unit is set up in such a way that it can determine the minimum amplitude of the operating voltage at which the electronic circuit is still functional.
• a new evaluation criterion for reliability, in particular for dielectrics is specified, which is directly relevant to the product.
• a function is determined in which the smallest operating voltage, i.e. the minimum supply voltage, at which the respective logic function of the test circuit blocks is still correctly carried out, is specified as a function of the stress load.
• the operating voltage source is set up in such a way that the frequency of the operating voltage can be varied and that the
• Test output signal evaluation unit is set up such that the frequency at which the operating voltage is applied is used to determine the frequency at which the electronic circuit is still functional.
• the area limitation no longer applies as in the prior art, since the breakdown Current is evaluated in relation to the leakage current under stress conditions. Rather, the logic function on an arbitrarily long inverter chain can be assessed; the structure should only be connected with a low impedance, so that the same stress voltage is applied to each device, ie preferably to each field effect transistor with a thin gate insulation layer.
• the method according to the invention provides that, by varying the amplitude of an applied operating voltage, it is determined from or at which minimum operating voltage the electronic circuit is functional.
• Thick oxide inverters and thin oxide inverters to buffer chains to investigate the reliability of thin dielectrics, i.e. of thin oxides can be combined.
• the buffer chain according to the invention allows the targeted loading of NMOS field effect transistors or PMOS field effect transistors under product-like surroundings, solves the limitation of the area limitation in the case of ' thin dielectrics in accordance with the prior art and provides the logic function or the functionality of the evaluation Test circuit blocks represent a product-relevant evaluation criterion.
• the electronic circuit can be integrated on a wafer, for example in an electronic one to be formed Chip, alternatively in a saw frame of a wafer, in which a large number of electronic chips are manufactured.
• Figure 1 shows an electronic circuit to be tested according to a first embodiment of the invention
• Figure 2 shows a circuit test arrangement according to a first embodiment of the invention
• FIG. 3 shows a schematic layout illustration of an inverter stage of a circuit to be examined in accordance with FIG. 1;
• FIGS. 4A and 4B to be tested electronic circuits according to a second embodiment of the invention.
• FIG. 2 shows a circuit test arrangement 200 according to a first exemplary embodiment of the invention.
• the circuit test arrangement 200 for determining the functionality of an electronic circuit 100 has a signal generator 201 for generating an electrical test signal and for providing an operating voltage.
• a test signal 203 is provided by the signal generator 201 and a test signal input terminal 101 of the electronic circuit 100, which is coupled to the first output terminal 202 of the signal generator 201.
• the signal generator 201 has four operating voltage connections 204, 205, 206, 207, with a first operating potential V ⁇ D at a first operating voltage connection, and a second at a second
• the four operating voltage connections 204, 205, 206, 207 of the signal generator 201 are associated with four
• Input ports 102, 103, 104, and 105 coupled.
• the circuit test arrangement 200 has a test output signal evaluation unit 208, configured as a personal computer, which is coupled to a test signal output connection 106 of the electronic circuit 100 by means of an input / output interface 209.
• a test output signal evaluation unit 208 configured as a personal computer, which is coupled to a test signal output connection 106 of the electronic circuit 100 by means of an input / output interface 209.
• the electronic circuit 100 to be tested is integrated in an electronic chip (not shown) of a wafer 210.
• the electronic circuit 100 is arranged in a saw frame of the wafer 210.
• the structure of the electronic circuit 100 to be examined is described in more detail below with reference to FIG.
• the electronic circuit 100 to be tested has N inverter stages which are connected in series, two inverter stages arranged directly adjacent to one another each forming an inverter stage pair 107 as a test circuit block. This means that N / 2
• Inverter stage pairs 107 are provided in the electronic circuit 100 to be tested.
• a first inverter stage 108 of each pair of inverter stages 107 has a PMOS field-effect transistor 109 and one
• NMOS field effect transistor 110 wherein the gate oxides, i.e. the silicon dioxide layers for isolating the gate layer of the respective field effect transistor from its channel region have a thickness of 6 nm.
• the first inverter stage is formed from field-effect transistors with a thick gate oxide.
• a second inverter stage 111 Downstream of the first inverter stage 108 in each case in the signal flow direction in a pair of inverter stages 107 is a second inverter stage 111, which likewise has a PMOS field effect transistor 112 and an NMOS field effect transistor 113.
• the gate oxide layer i.e. according to this embodiment of the invention, the silicon dioxide layer, the two
• Field effect transistors 112, 113 for isolating the gate layer from the channel region of the respective field effect transistors 112, 113 is 5 nm thick according to this exemplary embodiment of the invention.
• Field effect transistors 109, 110 of the first inverter stage 108 are coupled to the test signal input terminal 101, so that the test signal generated by the signal generator 201 directly to the gate terminals 109a, 110a
• Field effect transistors 109, 110 of the first inverter stage 108 is applied.
• a first source-drain connection 109b of the PMOS field-effect transistor 109 of the first inverter stage 108 is coupled to a first source-drain connection 110b of the NMOS field-effect transistor 110 of the first inverter stage.
• a first source-drain connection 112b of the PMOS field-effect transistor 112 of the second inverter stage 111 is coupled to a first source-drain connection 113b of the NMOS field-effect transistor 113 of the second inverter stage 111.
• All second source-drain connections 109c, 112c of all PMOS field-effect transistors 109, 112 of all inverter stages 108, 111 are coupled to the first operating voltage connection 102 of the electronic circuit 100 to be tested, so that the first operating potential Von is connected to the respective first source-drain Terminal 109c, 112c of the PMOS field effect transistor 109, 112 of the electronic circuit 100 is applied.
• the well connections 109d, 112d of all PMOS field-effect transistors 109 and 112 of all inverter stages 108, 111 are coupled to the third operating voltage connection 104 of the electronic circuit 100, so that the respective well potential V we n is connected to the respective well connection 109d, 112d of a PMOS field-effect transistor 109d , 112d of all inverter stages 108, 111 of the electronic circuit 100 is applied.
• All second source-drain connections 110c, 113c of all NMOS field-effect transistors 110, 113 of all inverter stages 108, 111 are coupled to the second operating voltage connection 103.
• the second operating potential Vgg is applied to the respective second source-drain connection 110c, 113c of each NMOS field-effect transistor 110, 113.
• the substrate connections llOd, 113d of all NMOS field effect transistors 110, 113 of all inverter stages 108, 111 are coupled to the fourth operating voltage connection 105, so that the substrate potential V su b is applied to the respective substrate connection 11Od of each NMOS field effect transistor 110, 113.
• the two gate connections 112a, 113a of the two field effect transistors 112, 113 of the second inverter stage 111 are connected to the first source-drain connection 109b of the PMOS field-effect transistor 109 of the first inverter stage 108 and to the first source-drain connection 110b of the NMOS field-effect transistor 110 of the first inverter stage 108.
• the other pairs of inverter stages 107 are coupled to the operating voltage connections 102, 103, 104, 105 and are connected to one another in series, so that the two gate connections 109a, 110a of the field effect transistors 109, 110 of the first inverter stage 108 with the two first source drain - Connections 112b, 113b of the field effect transistors of the second inverter stage 111 of the pair of inverter stages 107 preceding each in the signal flow direction are coupled.
• the first source-drain connections 112b, 113b of the field effect transistors 112, 113 of the second inverter stage 111 of the last pair of inverter stages 107 in the signal flow direction within the electronic circuit 100 is coupled to the test signal output terminal 106, to which a test signal output voltage is provided by the electronic circuit 100 V Q ut is provided.
• N denotes the number of inverter stages in the electronic circuit 100.
• the dimensions of the NMOS field-effect transistors 113 of the second inverter stage 111 and the PMOS field-effect transistors 112 of the second inverter stage 111 are preferably different a small width with different lengths.
• FIG. 3 shows a schematic layout illustration of a pair of inverter stages 107 with a first inverter stage 108 and a second inverter stage 111.
• the first inverter stage 108 is shown in the left half and the second inverter stage 111 in the right half of FIG.
• the thick oxide area i.e. with a gate oxide layer with a thickness of 6 nm is designated in FIG.
• the active areas of the field effect transistors 109, 110, 112, 113 are provided with the reference symbol 302.
• the N well for the PMOS field effect transistors 109, 112 of the pair of inverter stages 107 is provided with the reference symbol 303.
• the regions made of polysilicon are identified by reference numeral 304.
• the conductor tracks of the first metallization level, to which the source-drain connections of the field effect transistors are connected, are identified by the reference symbol 305.
• the conductor tracks of the second metallization level M2, to which the gate connections of the field effect transistors are connected, are provided with the reference symbol 306.
• the reference symbol 307 denotes the contact holes for contacting the conductor tracks with the gate connections and the source-drain connections of the field effect transistors.
• the reference number 308 denotes the contact holes for contacting the N well.
• the contact holes for contacting the NMOS field effect transistors i.e. in particular the substrate connections of the NMOS field-effect transistors with the substrate.
• Reference numeral 310 denotes the axis of symmetry of a unit cell 311 formed by the inverter stage pair 107 in the layout.
• An electronic test signal of a predetermined test signal profile is applied by the signal generator 201 to the gate connections 109a, 110a of the field effect transistors 109, 110 of the first inverter stage 108.
• the first operating potential VD ⁇ J is varied by the signal generator 201.
• the voltage supply that is supplied to the electronic circuit 100 clearly represents the stress pin, that is to say the connection via which the stress current, which is intended to load the field effect transistors to be tested and loaded with thin gate oxides, is supplied.
• the first operating potential VQD is varied and it is in each case after loading; by means of the test output signal evaluation unit 208 determines the minimum supply voltage, that is to say the minimum operating voltage at which the logic function, which is determined by the
• Inverter stages 108, 111 is realized, is executed correctly.
• the specific voltage thresholds for each wafer can be different and depend on "the materials used and the manufacturing processes used.
• the voltage thresholds are thus to be determined empirically for each wafer and the test output signal evaluation unit 208 is corresponding to calibrate or adjust.
• a and b show two electronic circuits 400, 450 according to a second exemplary embodiment of the invention.
• the first electronic circuit 400 according to the second exemplary embodiment of the invention has identical inverter stages 401, each of which has a PMOS field effect transistor 402 with a thick gate oxide, ie with a gate oxide with a thickness of 6 nm and an NMOS field effect transistor 403, with a gate oxide layer with a thickness of 5 nm, ie with a thin gate oxide.
• the connection is identical to the connection of the inverter stages according to the first exemplary embodiment of the invention, ie the gate connections 402a, 403a of the field effect transistors 402, 403 are coupled to a test signal input connection 404.
• the first source-drain connections 402b, 403b of the field-effect transistors 402, 403 are connected to one another and to the gate connections 402a, 403a of the field-effect transistors 402, 403 of the next inverter stage 401 following in the signal flow direction.
• the second source-drain connection of the PMOS field effect transistor 402a with thick gate oxide is each coupled to a first operating voltage connection 405, to which the first operating potential V-QQ- is applied.
• the second source-drain connection 403c of the NMOS field-effect transistor 403 with thin gate oxide of each inverter stage 401 is coupled to a second operating voltage connection 406, to which a second operating potential Vgg is applied.
• each PMOS field-effect transistor 402 is coupled to a third operating voltage connection 407, to which the well potential V we n is applied.
• the substrate connection 403d of each NMOS field-effect transistor 403 and the inverter 401 is coupled to a fourth operating voltage connection 408, to which the substrate potential V su b is applied.
• the determination of the reliability of the gate dielectrics is carried out in the same way as in the first exemplary embodiment by means of a signal generator (not shown) and a corresponding test output signal evaluation unit.
• the first source-drain connections 402b, 403b of the field effect transistors 402, 403 of the last inverter stage 401 in the signal flow direction in the electronic circuit 400 are coupled to a test signal output connection 409, to which the test output signal V ou t is provided.
• the field effect transistors to be tested are the NMOS field effect transistors 403.
• a second electronic circuit 450 is provided for testing gate oxides of PMOS field-effect transistors in accordance with the second exemplary embodiment of the invention.
• the circuit structure is identical to that of the first electronic circuit 400 according to FIG. 4 a with the difference that in this case the PMOS field effect transistors 451 as transistors with thin gate oxide, i.e. is provided with a gate oxide of the thickness of 5 nm and the NMOS field effect transistors 502 are with a thickness of the respective gate oxide layer of 6 nm, i.e. with a thick gate oxide.
• the gate connections 451a, 452a of the field effect transistors 451, 452 are coupled to the test signal input connection 404 in the first inverter 453 and to the two first source-drain connections in the subsequent inverter stages
• the second source-drain connection 451c of each PMOS field-effect transistor 451 is in each case with the second
• Operating voltage connection 405 coupled and the second source-drain connection 452c of each NMOS Field effect transistor 452 is coupled to the third operating voltage connection 406.
• each PMOS field effect transistor 451 is coupled to the third operating voltage connection 407 and the substrate connection 452d of each NMOS field effect transistor 452 is coupled to the fourth operating voltage connection 408.
• the first source-drain connections 451b, 452b of the last inverter 453 in the signal flow direction are coupled to the test signal output connection 409.
• test signal input connection 101 test signal input connection 102 first operating voltage connection
• test signal output connector 107 pair of inverter stages
• first operating voltage connection signal generator 205 second operating voltage connection signal generator 206 third operating voltage connection signal generator 207 fourth operating voltage connection signal generator
• first source-drain connection NMOS field-effect transistor 452c second source-drain connection NMOS field-effect transistor 452d substrate connection NMOS field-effect transistor

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• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Semiconductor Integrated Circuits (AREA)
• Tests Of Electronic Circuits (AREA)
• Testing Of Individual Semiconductor Devices (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)

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• 2003
  • 2003-09-17 DE DE10342997A patent/DE10342997A1/de not_active Ceased
• 2004
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