Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
  • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
  • G11C13/0009—RRAM elements whose operation depends upon chemical change
  • G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/401—Multistep manufacturing processes
  • H01L29/4011—Multistep manufacturing processes for data storage electrodes
  • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

• the invention relates to a method for producing a memory device having semiconductor structures with memory cells in which digital information is stored in a memory layer, in which: - two source / drain regions are formed in a semiconductor substrate, spaced apart by a channel region, - on a substrate surface of the Semiconductor substrate is provided with a gate dielectric substantially above the channel region.
• the invention also relates to a memory cell with a storage layer storing digital information, with two source / drain regions formed in a semiconductor substrate and spaced apart from one another by a channel region, and with a gate dielectric provided on a substrate surface of the semiconductor substrate essentially above the channel region.
• DRAM Dynamic Random Access Memory
• EEPROM Electrical Erasable and Programmable Read-Only-Memory
• memory cells are used in which digital information is stored as a charge state of a charge storing unit.
• the amount of the stored charge must not be less than a predetermined minimum. This fact leads to a considerable effort in the case of a further downsizing of the memory cells. Because the smaller the memory cell, the smaller the possible amount of stored charge will be and the more expensive It will reliably prove the state of charge of the cell.
• One approach to improve the situation is to design the charge storage unit of a memory cell, which is usually designed as a capacitor connected to a selection transistor, as a storage layer that stores the charge and is arranged over the channel region of a field effect transistor.
• the charge stored in the storage layer can be capacitively coupled into the channel region of the field effect transistor and thus an amplification of the field effect transistor can be used. Due to the amplification of the field effect transistor, even a small amount of stored charge is sufficient to enable reliable detection of the stored information.
• This approach is used, for example, in ferroelectric field effect transistors in which the memory layer consists of a ferroelectric material. A detailed description of a field effect transistor with a ferroelectric memory layer can be found in the publication by I.
• the storage layer consists of an organic material
• the organic storage layer can consist, for example, of porphyrin molecules. Oxidation and reduction of the porphyrin molecules lead to different charge states in the storage layer. A reduction corresponds to charging the storage layer with electrons and oxidation to discharging the storage layer.
• a gate electrode of the field effect transistor is connected a constant read voltage is applied and a resulting drain current is detected between the two source / drain regions.
• the storage layer If the storage layer is charged with electrons, a threshold voltage above which the drain current depends approximately exponentially on the level of the gate voltage shifts to higher voltage values. With a suitable read voltage, the drain current in the reduced state of the storage layer is approximately non-existent and indicates a logic state of zero. A drain current flows in the oxidized state of the storage layer and indicates a logic state one.
• FIG. 1 A conventional field effect transistor of a memory cell with an organic memory layer is shown in FIG. 1.
• Two source / drain regions 5 are separated from one another in a half-substrate by a channel region 4.
• a gate electrode 7 is provided on the organic storage layer 10.
• a predetermined reading voltage is applied to the gate electrode 7 and, depending on whether the storage layer 10 is in a reduced or oxidized state, when the reading voltage is applied, there is approximately no drain current between the two source / drain regions 5th
• the described dependence of the drain current on the charge state of the storage layer is shown in FIG. 5.
• the logarithm of the drain current is plotted on the ordinate and the gate voltage of an n-channel field-effect transistor of an memory cell, as shown in FIG. 1, containing an organic memory layer.
• Such a memory cell can also be implemented with a p-channel field effect transistor without restriction.
• the current-voltage Characteristic curve corresponds to the field effect transistor with a discharged oxidized storage layer.
• the current-voltage characteristic marked with b corresponds to the field effect transistor with a loaded reduced storage layer.
• An oxidation or reduction of the organic layer leads to a parallel shift of the current-voltage characteristic of the field effect transistor along the abscissa.
• the value UL marked on the abscissa indicates the level of the reading voltage at the gate electrode.
• the storage layer of the field effect transistor is in a reduced state with the
• the drain current D2 belonging to the value UL is quasi zero on the ordinate. If the storage layer is in an oxidized state with the current-voltage characteristic curve a, then the drain current Dl belonging to the value UL assumes a significantly higher value. There can therefore be two charge states of the storage layer with a constant reading voltage at the gate electrode be distinguished by the amount of the resulting drain current.
• FIG. 1 the production of memory devices with the memory cells shown in FIG. 1 is disadvantageous.
• semiconductor structures of the field effect transistors of memory cells and their mutual isolation are first processed. This concludes part of the overall process, which is also referred to as the front part FEOL (Front End of Line) and relates to the processing of mono- and polycrystalline semiconductor structures. After processing the semiconductor structures, the individual mono- and polycrystalline semiconductor structures are contacted and connected. This part of the overall process is also referred to as the rear part BEOL (Back End Of Line). Since very high temperatures of up to 1,100 degrees Celsius are used in the FEOL, the conventional memory cell shown in FIG.
• FEOL Front End of Line
• organic storage layers have the advantage of permanent charge storage when using extremely thin insulator layers compared to inorganic storage layers.
• Organic storage layers also have good scalability. This is advantageous in the case of a further downsizing of memory cells.
• the object of the invention is therefore to provide a method for producing a memory device with memory cells in which digital information is stored in a temperature-sensitive memory layer.
• the invention is based on the object of providing a memory cell with a temperature-sensitive memory layer.
• a method for producing a memory device having semiconductor structures with memory cells in which digital information is stored in a memory layer is provided.
• two source / drain regions spaced apart from one another by a channel region are formed in a semiconductor substrate.
• a gate dielectric is provided on a substrate surface of the semiconductor substrate essentially above the channel region.
• a first gate electrode is arranged on the gate dielectric.
• the processing of polycrystalline and monocrystalline semiconductor structures, in which high temperatures are used is completed before the storage layer is applied.
• Poly- or monocrystalline semiconductor structures are, for example, source / drain regions, channel region and first gate electrode of a field effect transistor.
• the application of the storage layer is thus relocated to a part of the processing in which the individual monocrystalline and polycrystalline semiconductor structures are contacted and connected and in which high temperatures are no longer used.
• the relocation of the application of the storage layer to a more advanced processing part generally also forces the storage layer to be separated from the first gate electrode, which is generally formed from a polycrystalline semiconductor substrate.
• a conductive connection between the storage layer and the first gate electrode is therefore provided, for example in the form of a metal-filled contact hole, which is introduced into an insulation layer.
• the second gate electrode which is separated by an insulator layer from the storage layer which is in conductive connection with the first gate electrode of the field effect transistor, is used for driving the field effect transistor.
• the main advantage of the method according to the invention is that the thermal load on the storage layer is significantly reduced in a simple manner and without additional process steps by moving the application of the storage layer into a more advanced processing part. This will make the range of materials used for Storage layers are provided to be significantly expanded.
• the method according to the invention also makes it possible to use organic storage layers.
• the storage layer is advantageously arranged between a first and a second electrode.
• electrode materials can be used that are matched to a material of the storage layer.
• Another advantage is that the electrode areas can be selected independently of the transistor and contact areas.
• the first electrode is preferably formed by a section of the conductive connection. If the conductive connection is designed, for example, as a contact hole filled with a conductive material, the storage layer can also be applied directly to the contact hole filling. This saves one process step.
• One of the metals aluminum, tungsten or copper is advantageously provided for the first and the second electrode. These are metals like those used in the other process steps. The formation of the electrodes would therefore not require an additional process step.
• one of the noble metals platinum, gold or silver is provided for the first and second electrodes.
• the first electrode is preferably formed in a first metal level and the second electrode in a second metal level.
• the conductive connection between the first gate electrode and the first electrode is established through a contact hole filled with conductive material.
• the formation of the first and the second electrode in one metal level in each case advantageously means that no additional process step for forming the electrodes forces. This is because the electrodes can be processed together with conductor tracks that are formed in the metal levels.
• An additional advantage of this procedure is that the storage layer can easily be introduced into a hole that is provided in an insulation layer that electrically separates the two metal planes from one another.
• the conductive connection between the first gate electrode and the first electrode is established through a contact hole filled with conductive material.
• no additional process step is necessary to produce the contact hole for the conductive connection between the first gate electrode and the first electrode.
• the first and second electrodes are each formed in a metal level that is processed in the further course of the process.
• the conductive connection between the first electrode and the first gate electrode is produced through contact holes which are arranged one above the other and filled with conductive material.
• the advantage of this procedure is that by forming the electrodes at a later point in the overall process, ie by moving the first and second electrodes to higher metal levels, the thermal load to which the storage layer is exposed is further reduced.
• the conductive connection between the first gate electrode and the first electrode is advantageously established through contact holes arranged one above the other, which are introduced into the insulation layers between the metal planes.
• the stacked contact holes filled with conductive material create a conductive connection through several metal levels.
• An organic layer which can be provided, for example, with porphyrin molecules, is preferably provided as the storage layer.
• Organic storage layers, such as those consisting of porphyrin molecules, have the advantage of permanent charge storage and less
• the gate dielectric through which the charge carriers can flow off, can be provided thinner than when inorganic storage layers are used.
• a thinner gate dielectric offers the advantage of an accelerated charging and discharging process of the storage layer and thus faster access times.
• Organic storage layers also have the advantage of good scalability. This is of great benefit for further downsizing of memory cells.
• source / drain regions of memory cells arranged in rows in a row are advantageously connected to one another in an electrically conductive manner by doped areas provided in the semiconductor substrate.
• conductive connections with conductor tracks formed in a metal plane and connecting the source / drain regions of memory cells are provided.
• the doped regions can be introduced into the semiconductor substrate by diffusion of a dopant.
• a memory cell is provided with a storage layer storing digital information, with two source / drain regions formed in a semiconductor substrate and spaced apart from one another by a channel region, and with a gate dielectric arranged on a substrate surface of the semiconductor substrate essentially above the channel region.
• a first gate electrode is arranged on the gate dielectric.
• the storage layer is arranged on the first gate electrode or at a distance from the first gate electrode.
• a conductive connection between the storage layer and the first gate electrode is provided.
• the memory cell according to the invention has the advantage that non-crystalline or polycrystalline semiconductor structures, such as, for example, channel region, source / drain region and first gate electrode of a field effect transistor, can be processed before the memory layer is applied. Since high temperatures are normally used in the processing of semiconductor structures, the application of the storage layer at a later time reduces the thermal load on the storage layer. This prevents degradation of, for example, organic storage layers. The storage layer is charged and discharged by the conductive connection of the storage layer to the first gate electrode. With the memory cell according to the invention, the spectrum of materials from which memory layers can consist can be expanded considerably.
• the storage layer is arranged between a first and a second electrode.
• electrode materials can be used. Det are matched to a material of the storage layer. Another advantage is that the electrode areas can be selected independently of the transistor and contact areas.
• the first electrode is preferably formed by a section of the conductive connection. If the conductive connection is designed, for example, as a contact hole filled with a conductive material, then the storage layer can also be applied directly to the contact hole filling. This saves one process step.
• the first and the second electrode advantageously consist of one of the metals aluminum, tungsten or copper. These are metals like those used in the other process steps. The formation of the electrodes would therefore not require an additional process step.
• the first and the second electrode preferably consist of one of the noble metals platinum, gold or silver.
• the first electrode is preferably formed in a first metal level and the second electrode in a second metal level.
• the conductive connection between the first gate electrode and the first electrode is provided through a contact hole filled with conductive material.
• the formation of the electrodes, between which the storage layer is arranged, in adjacent conductor tracks and metal planes containing contact holes has the advantage that additional process steps for forming the electrodes are avoided.
• the first and the second electrode are each formed in a metal plane spaced further from the first gate electrode than the first or the second metal plane.
• the conductive connection from the first electrode to the first gate electrode is provided through contact holes which are introduced into insulation layers, are arranged one above the other and are filled with conductive material.
• the conductive connection between the first gate electrode and the first electrode is advantageously provided by contact holes arranged one above the other, which establish a connection through a plurality of metal planes.
• the storage layer is provided as an organic layer which contains, for example, porphyrin molecules.
• Layers permanently bind charge carriers and mainly have low leakage currents.
• the gate dielectric through which the charge carriers can flow out can be provided thinner.
• a thinner gate dielectric offers the advantage of an accelerated charging and discharging process of the storage layer.
• Organic storage layers also have the advantage of good scalability. This is of great benefit for further downsizing of memory cells.
• a storage device is arranged with rows of
• Memory cells having semiconductor structures and storing digital information are provided.
• the described memory cells according to the invention are preferably arranged in the memory device.
• the storage device has the advantage that digital information can be stored in it in organic storage layers. Leakage currents are due to the durability of the charge storage reduced.
• Memory devices with the memory cells according to the invention are distinguished by permanent information storage and accelerated programming processes.
• source / drain regions of memory cells which are respectively adjacent in one row are electrically conductively connected to one another by doped regions provided in the semiconductor substrate.
• conductive connections to conductor tracks formed in a metal plane and connecting source / drain regions of memory cells are provided.
• locally diffused source and drain lines have the advantage of saving space on a semiconductor wafer per memory cell, which results from the fact that contacting each individual memory cell with the metal level can be dispensed with.
• lines made of a doped semiconductor substrate have the disadvantage of a higher resistance.
• a conductive connection to the conductor track in the metal level is provided after a predetermined number of memory cells, for example eight or sixteen memory cells. This compensates for the disadvantage of increased resistance and still exploits the advantage of saving space.
• the respective memory layers of selected memory cells are charged in order to program the memory device. This is done by applying voltages to the source / drain regions contained in the selected memory cells and to the second gate electrode.
• the storage layers are then charged by means of high-energy electrons or by means of a tunneling process of electrons through the gate dielectric.
• the charged memory layers are used to delete the programming discharging electrons to the channel region or to a source / drain region by applying an erase voltage which differs from the voltage applied during programming to the second gate electrode by means of a tunneling process.
• a strength of a drain current is detected as a function of a charge state of the memory layer.
• a voltage between the second electrode and the channel region is required which is large enough that at least one reduction potential corresponding to the storage layer is present on the storage layer.
• the necessary voltage can be generated by applying a positive potential to the second electrode and a negative potential to a doped region in the semiconductor substrate in the source / drain regions and channel region of a transistor, which is also referred to as a well. If the voltage at the second gate electrode is sufficient to effect charging of the organic storage layer, a voltage can advantageously also be applied to the drain region. If the material used for the storage layer has several redox states, several states can be written in by applying different voltages. To erase the charged storage layer, the oxidation potentials can be applied accordingly, i. that is, a negative potential is applied to the second electrode and a positive potential to the well.
• a voltage of 5 V to 7 V and a voltage of 10 V to 12 V can be applied to the second gate electrode.
• high-energy electrons are generated in the channel region of the field effect transistor and pass through the gate dielectric into the first gate electrode and through the conductive connection to the storage layer.
• Electrons are Layer taken and held. A change in the state of charge and thus also a change in the electrical potential has occurred in the storage layer.
• Another possibility of charging the storage layer is to use a tunneling process of electrons through the gate dielectric which is supported by an electric field.
• the tunneling process of electrons from the storage layer through the gate dielectric to the channel region or to one of the source / drain regions, which is supported by an electric field, can be used to discharge the storage layer. For example, by applying a voltage of 5 V to the source region and a voltage of -8 V to the second gate electrode.
• a voltage of 5 V to the source region and a voltage of -8 V to the second gate electrode.
• a fixed read voltage and a voltage between the source and the drain region are applied to the second gate electrode in order to generate a lateral field.
• the level of the drain current depends approximately linearly on the level of the voltage at the second gate electrode. The drain current is approximately non-existent below the threshold voltage.
• the threshold voltage shifts towards a higher voltage at the second gate electrode.
• a higher voltage is applied to the second gate electrode.
• the drain current flows, which is quasi not available in the charged state of the storage layer, i.e. can be assigned the logical value zero and has a finite value in the discharged state and can be assigned the logical value one.
• FIG. 1 shows a schematic cross section through a memory cell corresponding to the prior art
• FIG. 2 shows a schematic cross section through a memory cell according to the invention according to a first exemplary embodiment
• FIG. 3 shows a schematic cross section through a memory cell according to the invention in accordance with a second exemplary embodiment
• Fig. 4 shows a schematic section of a storage device according to the invention in plan view
• Fig. 5 current-voltage characteristics of a field effect transistor with an organic memory layer.
• FIG. 1 has already been explained in more detail in the introduction to the description.
• a memory cell 1 shown in FIG. 2 in which digital information is stored in a temperature-sensitive organic memory layer 10, two source / drain regions 5 spaced apart from one another by a channel region 4 are provided as doped regions in a semiconductor substrate 17.
• a gate dielectric 6 is arranged essentially above the channel region 4 and a first gate electrode 7a is arranged on the gate dielectric 6.
• the organic storage layer 10 is provided above the first gate electrode 7a between a first metal level 11a and a second metal level 11b. Because the If organic storage layer 10 is arranged above the polycrystalline or monocrystalline semiconductor structures, that is to say those structures that are provided in semiconductor substrate 17 or consist of a semiconductor substrate 17, processing of the semiconductor structures can be completed before the organic storage layer 10 is applied. Since temperatures of up to 1100 degrees Celsius are used in the processing of the semiconductor structures and the organic storage layer 10 is damaged at such temperatures, the application of the organic
• the thermal load on the organic storage layer 10 can be reduced at a later time.
• the organic storage layer 10 is connected to the first gate electrode 7a by a conductive connection 8 and can be charged by electrons which reach the first gate electrode 7a from the channel region 4 through the gate dielectric 6.
• the conductive connection is provided in the form of a metal-filled contact hole 14 which is introduced into an insulation layer 12.
• the organic storage layer 10 is introduced in a hole between two metal planes 11a, b and is arranged between a first and a second electrode 9a, b.
• the second gate electrode 7b is located above the second electrode and is separated from the second electrode 9b by an insulator layer 18.
• the second gate electrode 7b is used to control a field effect transistor consisting of the elements described.
• the elements of the field effect transistor with the organic memory layer 10 contained in the memory cell 1 can be seen from FIG.
• the source / drain regions 5 spaced apart by a channel region 4 are located in a semiconductor substrate 17.
• a gate dielectric 6 is arranged above the channel region and a first gate electrode 7a is arranged on the gate dielectric.
• Two metal planes 11a, b can be seen, in which the electrodes 9a, b are pronounced.
• the organic one is located between the electrodes 9a, b Storage layer 10.
• the conductive connection 8 between the first electrode 9a and the first gate electrode 7a is shown in the form of a metal-filled contact hole 14 in the insulation layer 12.
• An insulator layer 18 is provided on the second electrode 9b and the second gate electrode 7b is provided on the insulator layer.
• the conductive connection 8 of the first electrode 9a to the first gate electrode 7a is made by stacking one above the other and filled with metal in insulation layers 12 Contact holes 14, which allow contact through underlying metal planes 11, are produced.
• the embodiment of the memory cell 1 shown in FIG. 3 differs from the embodiment of the memory cell 1 shown in FIG. 2 by the type of its conductive connection 8.
• the organic layer 10 is located between two higher metal levels 11.
• the conductive Connection 8 consists of stacked and metal-filled contact holes 14 which are introduced into the insulation layers 12 provided between the metal levels 11 and which make contact through a plurality of conductor tracks 13 and metal holes 11 having contact holes 14.
• the memory cells 1 are arranged, for example, in rows and columns. Each in lines and
• Bit line 13b The other conductor track 13 connects the second gate electrodes 7b of the memory cells 1 adjacent in the columns and is also referred to as addressing line 13a. Both the bit line 13b and the addressing line 13a are each formed in a metal level 11.
• the source / drain regions 5 are Memory cells 1 are connected to one another in an electrically conductive manner by doped regions 16 in the semiconductor substrate 17. Only every 8 or 16 memory cells 1, for example, is a conductive connection 8 to the bit line 13b provided.
• FIG. 4 A section of the memory device 2 can be seen in FIG. 4.
• Crossed bit lines 13b and addressing lines 13a are shown.
• the row and column-arranged memory cells 1 are located at the intersections 15.
• the doped areas 16, which are designed as lines and which connect the source / drain areas 5 of adjacent memory cells 1 in a row, can be seen in the detail, as is the conductive one Connection 8 to bit line 13b.

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• 2003
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