WO2004047177A1 - 半導体集積装置及びその製造方法 - Google Patents
半導体集積装置及びその製造方法 Download PDFInfo
- Publication number
- WO2004047177A1 WO2004047177A1 PCT/JP2003/014516 JP0314516W WO2004047177A1 WO 2004047177 A1 WO2004047177 A1 WO 2004047177A1 JP 0314516 W JP0314516 W JP 0314516W WO 2004047177 A1 WO2004047177 A1 WO 2004047177A1
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- WO
- WIPO (PCT)
- Prior art keywords
- wiring
- light
- semiconductor integrated
- integrated device
- forming
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 238000000034 method Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000007789 sealing Methods 0.000 claims abstract description 6
- 238000003384 imaging method Methods 0.000 claims description 35
- 229910052782 aluminium Inorganic materials 0.000 claims description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 28
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 10
- 238000003860 storage Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
- H01L27/14623—Optical shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
Definitions
- the present invention relates to a semiconductor integrated device in which a solid-state imaging device is packaged and a method for manufacturing the same.
- chip size packages have been widely used to reduce the chip size of solid-state imaging devices.
- FIG. 10 is a plan view showing the structure of the solid-state imaging device.
- the solid-state imaging device basically includes a light receiving unit 200, a storage unit 202, a horizontal transfer unit 204, an output unit 206, and an output amplifier 208. It is.
- the light receiving section 200 a plurality of light receiving pixels are arranged in a matrix, and information charges generated by receiving light are accumulated in each light receiving pixel.
- the storage unit 202 is provided with a plurality of storage pixels according to the number of light receiving pixels of the light receiving unit 200, and takes in the information charge for one screen stored in the light receiving unit 200 and temporarily stores it. I do.
- the horizontal transfer unit 204 takes in information charges from the storage unit 202 in units of one line, and performs horizontal transfer one pixel at a time.
- the output unit 206 converts the information charge transferred from the horizontal transfer unit 204 into a voltage value for each pixel and outputs the converted voltage.
- the output amplifier 208 amplifies the voltage value output from the output unit 206 and outputs it as an image signal.
- the solid-state imaging device having such a structure includes a light-receiving section 200, a storage section 202, a horizontal transfer section 204, an output section 206, and a diffusion layer on a semiconductor substrate surface and electrodes on the substrate.
- An output amplifier 208 is formed, and finally, a light shielding film for blocking light is arranged in a portion other than the light receiving portion 200 (hatched area in the figure).
- Fig. 11 shows a semi-conductor cut at the position corresponding to X-X in Fig. 10. It is sectional drawing of a body integrated device.
- a P-type diffusion layer 302 is formed on the surface of the N-type semiconductor substrate 300, and an N-type diffusion layer 304 is formed in the P-type diffusion layer 302.
- a high-concentration P-type impurity is partially implanted into the N-type diffusion layer 304 to form a channel stopper (not shown).
- the transfer electrode 306 is formed on the semiconductor substrate 300 via the insulating film 305, and the solid-state imaging device is formed.
- An insulating film 308 is stacked on the transfer electrode 306, and a voltage supply line 310 and a pad electrode 322 are formed on the insulating film 308.
- the voltage supply line 310 and the pad electrode 322 are electrically connected to the transfer electrode 306 via a contact formed in the insulating film 308.
- an insulating film 312 is laminated on the voltage supply line 310 and the pad electrode, and an internal wiring 314 is formed on the insulating film 312.
- the internal wiring 3 14 is connected to the external wiring 110 arranged along the side surface of the package at its cross section.
- an insulating film 3 16 is laminated, and light is shielded on the insulating film 3 16 in a region covering the storage section 202, the horizontal transfer section 204 and the output section 206.
- a membrane 318 is placed.
- a surface protection film 320 is arranged so as to cover the light shielding film 318 and the insulating film 316. Disclosure of the invention
- the thickness of the voltage supply line 310 is about 1 zm, which is insufficient for direct connection to the external wiring 110, so that the internal wiring 3 Four had to be provided.
- the present invention has been made in view of the above-described problems of the related art, and has been made to solve at least one of the above-described problems, and is a semiconductor integrated device that can be easily formed without deteriorating element characteristics. And a method for producing the same.
- the present invention is directed to a pad having a light receiving portion for generating information charges by receiving light, and a transfer portion for transferring information charges accumulated in the light receiving portion on a semiconductor substrate, wherein the pad is arranged along one side of the semiconductor substrate
- a solid-state imaging device to which a voltage is supplied via an electrode; a light-shielding film formed on the semiconductor substrate, which shields at least a part of the transfer unit; a light-shielding film formed on the same layer as the light-shielding film;
- a first wiring whose other end extends to a side of the semiconductor substrate, and a second wiring which is arranged to bypass a side surface of the semiconductor substrate and is connected to the first wiring.
- a semiconductor integrated device comprising: a wiring; and a sealing member for sealing the solid-state imaging device.
- an end of the first wiring extends to a side of the solid-state imaging device, and the second wiring is arranged so as to bypass the side surface of the solid-state imaging device.
- Another embodiment of the present invention is directed to a semiconductor integrated circuit in which an end of an internal wiring extends to a side of a solid-state imaging device, and the internal wiring is connected to an external wiring arranged to bypass a side surface of the solid-state imaging device.
- a method for manufacturing a device comprising: forming a light receiving portion for generating information charges by receiving light and a transfer portion for transferring information charges accumulated in the light receiving portion to form the solid-state imaging device on a semiconductor substrate; Forming a pad electrode for supplying a voltage to the light receiving section and the transfer section, and forming a first internal wiring on the same layer as the pad electrode; and a second step of forming at least the transfer section.
- FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor integrated device according to an embodiment of the present invention.
- FIG. 2A is a perspective view showing an appearance of a package of the semiconductor integrated device according to the embodiment of the present invention.
- FIG. 3 is a flowchart showing a method of manufacturing a semiconductor integrated device according to the embodiment of the present invention.
- FIG. 4 is a diagram illustrating a manufacturing process of the semiconductor integrated device according to the embodiment of the present invention.
- FIG. 5 is a diagram showing a manufacturing process of the semiconductor integrated device according to the embodiment of the present invention.
- FIG. 6 is a diagram illustrating a manufacturing process of the semiconductor integrated device according to the embodiment of the present invention.
- FIG. 7 is a diagram illustrating a manufacturing process of the semiconductor integrated device according to the embodiment of the present invention. .
- FIG. 8 is a diagram illustrating a manufacturing process of the semiconductor integrated device according to the embodiment of the present invention.
- FIG. 9 is a diagram illustrating a manufacturing process of the semiconductor integrated device according to the embodiment of the present invention.
- FIG. 10 is a plan view showing a configuration of a conventional solid-state imaging device.
- FIG. 11 is a diagram showing a cross-sectional structure of a conventional semiconductor integrated device. BEST MODE FOR CARRYING OUT THE INVENTION
- FIGS. 2A and 2B are perspective views showing an example of a semiconductor integrated device in which a chip size package is applied to a solid-state imaging device.
- a solid-state imaging device chip 104 is sealed between the first and second glass substrates 100 and 102 via a resin film 106.
- a plurality of pole-shaped terminals 108 are arranged on the main surface of the second glass substrate 102, that is, on the back side of the device, and these ball-shaped terminals 108 are solid-state via external wiring 110.
- Imaging Connected to element chip 104. Wirings are drawn out from the solid-state imaging device chip 104 and connected to the plurality of external wirings 110, and contact with each pole-shaped terminal 108 is established.
- FIG. 1 is a cross-sectional view illustrating a cross-sectional structure of a semiconductor integrated device according to an embodiment of the present invention.
- FIG. 1 is a cross-sectional view of the semiconductor integrated device taken along a position corresponding to X--X in FIG. 10 and has the same configuration as those shown in FIGS. 2A, 2B, 10 and 11. Are denoted by the same reference numerals.
- a P-type diffusion layer 302 is formed on the surface of the N-type semiconductor substrate 300, and an N-type diffusion layer 304 is formed in the P-type diffusion layer 302.
- a high-concentration P-type impurity is partially implanted into the N-type diffusion layer 304 to form a channel stopper (not shown).
- the transfer electrode 303 is arranged on the semiconductor substrate 300 via the insulating film 305.
- an insulating film 308 is laminated.
- a voltage supply line 310 and a first internal wiring 407 are formed on 08. The voltage supply line 310 and the first internal wiring 407 are formed in the same layer, and the first internal wiring 407 is formed at the outer peripheral end of the package.
- the second internal wiring 414 extends from a predetermined position to the end of the package, and is formed to be connected to the first internal wiring 407 at the end of the package. Then, the second internal wiring 4 14 is connected to the external wiring 110 at a portion overlapping with the first internal wiring 4 07.
- the light-shielding film 418 is arranged so as to cover the areas of the storage section 202, the horizontal transfer section 204 and the output section 206, and the storage section 202, the horizontal transfer section 204 and the output section. Prevents light from entering 206.
- An insulating film 420 is stacked on the light-shielding film 4 18 and the second internal wiring 4 14, and a first glass substrate 100 is further formed thereon via a resin film 106. Is arranged.
- the connection strength between the external wiring 110 and the internal wiring can be improved.
- the second internal wiring 4 1 4 forming a part of the internal wiring is Since it is formed in the same layer as 18, the second internal wiring 4 14 can be simultaneously formed using the process of forming the light shielding film 4 18. For this reason, the connection strength between the external wiring 110 and the internal wiring can be improved without increasing the number of manufacturing steps.
- the materials of the voltage supply line 310, the pad electrode 3222, and the light shielding film 418 are generally used for semiconductor elements such as silver, gold, copper, aluminum, nickel, titanium, tantalum, and tungsten. The material used can be the main material.
- first internal wiring 407 and the second internal wiring 414 are susceptible to corrosion from the outside of the element at the ends thereof. It is more preferred to use aluminum containing in the range of at most atomic%.
- the thickness of the voltage supply line 310 and the pad electrode 3222 is based on the case where aluminum is the main material because the minimum processing line width of the electrode must be kept small and the electric resistance value must be kept sufficiently low. Is preferably 0.5 ⁇ m or more and 2 / zm or less. Further, it is more preferable that the thickness be 0.5 ⁇ or more and 1 ⁇ or less.
- the thickness of the light-shielding film 418 can be made larger than the voltage supply wiring layer because the minimum processing line width does not need to be so small and unnecessary light needs to be sufficiently shielded.
- the throughput of the manufacturing process when aluminum is used as the main material, it is preferable to be 1.5 ⁇ or more and 8 ⁇ or less. Furthermore, it is more preferable that the value be 2 / zm or more and 8 / xm or less.
- the total film thickness of the first internal wiring 407 and the second internal wiring 414 to be connected to the external wiring is at least 2 ⁇ m or more and 10 ⁇ m or less. With this, it is possible to improve the connection strength while maintaining the contact resistance when connected to the external wiring 110 on the side surface of the solid-state imaging device as low as the conventional internal wiring 3 14 .
- FIG. 3 is a flowchart illustrating the method of manufacturing a semiconductor integrated device according to the present invention
- FIGS. 4 to 9 are cross-sectional views of the semiconductor integrated device corresponding to each manufacturing process.
- step S10 a light receiving unit 200, a storage unit 202, a horizontal transfer unit 204, and an output unit 206, which are sensor units, are formed.
- P-type impurity ions are implanted and diffused into the surface of an N-type semiconductor substrate 300a in a wafer state to form a P-type semiconductor region 300.
- N-type impurity ions are implanted and diffused into the P-type semiconductor region 302 to form an N-type semiconductor region 304.
- an insulating film 305 and a transfer electrode 306 are formed on the semiconductor substrate 300a by appropriately combining a film forming technique such as sputtering and chemical vapor deposition and a photolithography technique. Then, P-type impurity ions are partially implanted into the semiconductor region 304 at a high concentration to form a channel stopper (not shown), and the state shown in FIG. 4 is obtained.
- a peripheral circuit of the output amplifier 208 is formed in a peripheral area of the sensor section.
- the peripheral circuit can be formed in the same manner as the conventional transistor forming process.
- a source region and a drain region are formed by using a doping technique such as thermal diffusion or ion implantation, and a thermal oxide film serving as a gate insulating film is formed by thermal oxidation. Then, a polysilicon layer or a metal film serving as a source electrode (not shown), a drain electrode (not shown), and a gate electrode is formed by combining photolithography technology and film forming technology such as chemical vapor deposition or sputtering. Film.
- step S14 as shown in FIG. 6, a voltage supply line 310 and a first internal wiring 407 are formed.
- a metal layer serving as a voltage supply line 310 for transmitting a supply voltage from the outside is formed.
- the first internal wiring 407 is formed using the metal layer.
- an interlayer insulating film 308 is formed on the semiconductor substrate 300 a on which the voltage supply line 310 and the first internal wiring 407 are formed, and then using photolithography technology or the like.
- An opening is provided in a necessary portion of the interlayer insulating film 308 by using a film forming technique such as sputtering and chemical vapor deposition, and a metal layer is formed. Then, the voltage supply line 310 and the first internal wiring 407 are formed by patterning the metal layer.
- a metal layer can be formed by sputtering aluminum.
- a voltage supply line 310 and a first internal wiring 407 having high corrosion resistance are formed by using aluminum containing 0.1 atomic% to 20 atomic% of copper as a target. can do.
- the voltage supply line 310 and the first internal wiring 407 can be formed by vapor deposition. At this time, aluminum containing copper in an amount of 0.1 atomic% or more and 20 atomic% or less is used. By using aluminum as a raw material, the voltage supply line 310 and the first internal wiring 407 having high corrosion resistance can be formed.
- the voltage supply line 310 and the first internal wiring 407 can be formed by using chemical vapor deposition. At this time, by adjusting the mixing ratio of the organic gas containing aluminum and the organic gas containing copper, it is possible to form a highly corrosion-resistant aluminum film containing copper in the range of 0.1 atomic% to 20 atomic%. it can.
- step S16 as shown in FIG. 7, the light-shielding film 418 and the second internal wiring 414 are formed.
- an interlayer insulating film 312 is formed.
- an opening is provided in a necessary portion on the sensor unit and the peripheral circuit by using a photolithography technique or the like, and a metal layer is formed by using a vapor deposition technique such as sputtering or chemical vapor deposition.
- the second internal wiring 414 and the light shielding film 418 are formed by patterning the metal layer.
- a metal layer is formed by sputtering, vapor deposition, or chemical vapor deposition, and highly corrosion-resistant aluminum containing 0.1 to 20 atomic% of copper is used. Is preferably formed.
- step S20 as shown in FIG. 8, the first and second glass substrates 100, 102 are bonded by a resin film 106.
- a glass plate is generally bonded using an epoxy resin.
- step S22 external wiring 110 is formed as shown in FIG.
- the second glass substrate 102 was cut from the side using a dicing saw with a taper to form an inverted V-shaped groove, and the first and second internal wirings 40 were formed on the inner surface of the groove. 7, 4 14 are exposed.
- a metal layer is formed on the inner surface of the groove by sputtering, vapor deposition, or chemical vapor deposition, and the metal layer is patterned to form an external wiring 110.
- a pole-shaped terminal 108 is formed on the surface of the second glass substrate 102 so as to be connected to the external wiring.
- step S24 the laminate formed in step S22 is diced along scribe lines, that is, along the boundaries of the individual imaging devices. Thereby, the semiconductor integrated device is completed.
- the step of forming the internal wiring can be omitted as compared with the conventional manufacturing method. Therefore, the manufacturing process can be simplified, and the solid-state imaging device package can be easily manufactured. Also, since the internal wiring is formed in two steps, such as the first and second internal wirings 407 and 414, and has a two-layer structure, the connection strength with the external wiring 110 is improved. It can be done.
- the manufacturing process can be simplified without impairing element characteristics.
- the frame transfer type is exemplified as the solid-state imaging device.
- the present invention is not limited to this.
- the present invention is sufficiently applicable to a semiconductor integrated device using an interline type or a frame interline type solid-state imaging device.
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/530,095 US7361525B2 (en) | 2002-11-19 | 2003-11-14 | Semiconductor integrated device having solid-state image sensor packaged within and production method for same |
US12/041,530 US7619292B2 (en) | 2002-11-19 | 2008-03-03 | Semiconductor integrated device having solid-state image sensor packaged within and production method for same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002334585A JP4401066B2 (ja) | 2002-11-19 | 2002-11-19 | 半導体集積装置及びその製造方法 |
JP2002-334585 | 2002-11-19 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10530095 A-371-Of-International | 2003-11-14 | ||
US12/041,530 Division US7619292B2 (en) | 2002-11-19 | 2008-03-03 | Semiconductor integrated device having solid-state image sensor packaged within and production method for same |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004047177A1 true WO2004047177A1 (ja) | 2004-06-03 |
Family
ID=32321734
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/014516 WO2004047177A1 (ja) | 2002-11-19 | 2003-11-14 | 半導体集積装置及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7361525B2 (ja) |
JP (1) | JP4401066B2 (ja) |
CN (1) | CN100373626C (ja) |
TW (1) | TWI236726B (ja) |
WO (1) | WO2004047177A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5348598B2 (ja) * | 2005-05-10 | 2013-11-20 | 日本電気硝子株式会社 | 半導体素子用ガラス基板およびそれを用いたチップスケールパッケージ |
JP2007005485A (ja) * | 2005-06-22 | 2007-01-11 | Fujifilm Holdings Corp | 半導体装置およびその製造方法 |
JP2007043056A (ja) * | 2005-07-06 | 2007-02-15 | Fujifilm Corp | 半導体装置およびその製造方法 |
JP4677311B2 (ja) * | 2005-09-14 | 2011-04-27 | 富士フイルム株式会社 | Mos型固体撮像装置及びその製造方法 |
JP4825538B2 (ja) | 2006-02-17 | 2011-11-30 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
DE102008058003B4 (de) * | 2008-11-19 | 2012-04-05 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleitermoduls und Halbleitermodul |
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JP2000077646A (ja) * | 1998-08-27 | 2000-03-14 | Sanyo Electric Co Ltd | 固体撮像素子及びその駆動方法 |
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JP2003347476A (ja) * | 2002-05-22 | 2003-12-05 | Sanyo Electric Co Ltd | 半導体集積装置及びその製造方法 |
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JP2809115B2 (ja) * | 1993-10-13 | 1998-10-08 | ヤマハ株式会社 | 半導体装置とその製造方法 |
US5461008A (en) * | 1994-05-26 | 1995-10-24 | Delco Electronics Corporatinon | Method of preventing aluminum bond pad corrosion during dicing of integrated circuit wafers |
US6152803A (en) * | 1995-10-20 | 2000-11-28 | Boucher; John N. | Substrate dicing method |
JP4027465B2 (ja) * | 1997-07-01 | 2007-12-26 | 株式会社半導体エネルギー研究所 | アクティブマトリクス型表示装置およびその製造方法 |
JP4271268B2 (ja) * | 1997-09-20 | 2009-06-03 | 株式会社半導体エネルギー研究所 | イメージセンサおよびイメージセンサ一体型アクティブマトリクス型表示装置 |
US6316287B1 (en) * | 1999-09-13 | 2001-11-13 | Vishay Intertechnology, Inc. | Chip scale surface mount packages for semiconductor device and process of fabricating the same |
JP4415443B2 (ja) | 2000-02-07 | 2010-02-17 | ヤマハ株式会社 | 集積回路装置とその製法、及び、半導体ウエハ乃至保護基板の積層体 |
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US7340181B1 (en) * | 2002-05-13 | 2008-03-04 | National Semiconductor Corporation | Electrical die contact structure and fabrication method |
ATE493760T1 (de) * | 2002-05-20 | 2011-01-15 | Imagerlabs Inc | Bilden einer integrierten mehrsegmentschaltung mit isolierten substraten |
TWI227550B (en) * | 2002-10-30 | 2005-02-01 | Sanyo Electric Co | Semiconductor device manufacturing method |
JP2004214588A (ja) * | 2002-11-15 | 2004-07-29 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP4544876B2 (ja) * | 2003-02-25 | 2010-09-15 | 三洋電機株式会社 | 半導体装置の製造方法 |
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JP4719597B2 (ja) * | 2006-03-16 | 2011-07-06 | 富士フイルム株式会社 | 光電変換素子及び固体撮像素子 |
-
2002
- 2002-11-19 JP JP2002334585A patent/JP4401066B2/ja not_active Expired - Fee Related
-
2003
- 2003-11-11 TW TW092131470A patent/TWI236726B/zh not_active IP Right Cessation
- 2003-11-14 CN CNB2003801001073A patent/CN100373626C/zh not_active Expired - Fee Related
- 2003-11-14 WO PCT/JP2003/014516 patent/WO2004047177A1/ja active IP Right Grant
- 2003-11-14 US US10/530,095 patent/US7361525B2/en active Active
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2008
- 2008-03-03 US US12/041,530 patent/US7619292B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000077646A (ja) * | 1998-08-27 | 2000-03-14 | Sanyo Electric Co Ltd | 固体撮像素子及びその駆動方法 |
JP2002198463A (ja) * | 2000-12-26 | 2002-07-12 | Canon Inc | チップサイズパッケージおよびその製造方法 |
JP2002329852A (ja) * | 2001-05-01 | 2002-11-15 | Fuji Film Microdevices Co Ltd | 固体撮像装置及びその製造方法 |
JP2003347476A (ja) * | 2002-05-22 | 2003-12-05 | Sanyo Electric Co Ltd | 半導体集積装置及びその製造方法 |
Also Published As
Publication number | Publication date |
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TWI236726B (en) | 2005-07-21 |
US7619292B2 (en) | 2009-11-17 |
CN100373626C (zh) | 2008-03-05 |
US20060022288A1 (en) | 2006-02-02 |
TW200415743A (en) | 2004-08-16 |
CN1685515A (zh) | 2005-10-19 |
JP2004172249A (ja) | 2004-06-17 |
US7361525B2 (en) | 2008-04-22 |
US20080203513A1 (en) | 2008-08-28 |
JP4401066B2 (ja) | 2010-01-20 |
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