WO2004021433A1 - Soiウエーハの製造方法 - Google Patents
Soiウエーハの製造方法 Download PDFInfo
- Publication number
- WO2004021433A1 WO2004021433A1 PCT/JP2003/010559 JP0310559W WO2004021433A1 WO 2004021433 A1 WO2004021433 A1 WO 2004021433A1 JP 0310559 W JP0310559 W JP 0310559W WO 2004021433 A1 WO2004021433 A1 WO 2004021433A1
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- Prior art keywords
- wafer
- soi
- wafers
- layer
- insulating layer
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Definitions
- the present invention relates to a method of manufacturing an SOI (Silicon on Insulator) wafer formed of an SOI layer, an insulating layer, and a support substrate, and more particularly to a method of manufacturing an SOI wafer by a bonding method (bonding method).
- SOI Silicon on Insulator
- the degree of integration of integrated circuits has increased remarkably, and accordingly, stricter conditions have been imposed on the processing accuracy such as the flatness and smoothness of the mirror-polished semiconductor single crystal wafer surface.
- the SOI wafer is an ideal dielectric separation substrate, so it is used mainly as a high-frequency and high-speed device mainly in mobile communication equipment and medical equipment, and large demand expansion is expected in the future.
- the SOI wafer 50 has an SOI layer 52 (also referred to as a semiconductor layer or an active layer) for forming an element such as a single-crystal silicon layer, and an insulating layer such as a silicon oxide film. 5 4 It has a structure formed on [buried (BOX) oxide film layer or simply oxide film layer].
- the insulating layer 54 is formed on a supporting substrate 56 (also referred to as a substrate layer), and has a structure in which an SOI layer 52, an insulating layer 54, and a supporting substrate 56 are sequentially formed.
- SIMOX Separatation by implanted oxygen
- oxygen ions are implanted into silicon single crystal at a high concentration, and then heat treatment is performed at high temperature to form an oxide film.
- bonding method bonding method that combines mirror-polished wafers without using an adhesive and makes one of the wafers thinner.
- the thickness of the active layer (SOI layer) 52 that becomes the device active region can be determined and controlled by the acceleration voltage at the time of oxygen ion implantation.
- the acceleration voltage at the time of oxygen ion implantation there is an advantage that 2 can be easily obtained, there are many problems such as the reliability of the buried (BOX) oxide film (insulating layer) 54 and the crystallinity of the active layer 52.
- the wafer bonding method involves forming an oxide film (insulating layer) 54 on at least one of two single-crystal silicon mirrors, and bonding them together without using an adhesive, followed by heat treatment (usually (1100 ° C to 1200 ° C) to strengthen the bond.After that, one of the wafers is thinned by grinding or wet etching, and then the surface of the thin film is mirror-polished. Since the layer 52 is formed, there is an advantage that the buried (BOX) oxide film (insulating layer) 54 has high reliability and the SOI layer 52 has good crystallinity. However, since the SOI wafer 50 thus bonded is mechanically worked by grinding or polishing to make it thinner, the thickness of the SOI layer 52 obtained and its uniformity are limited.
- a method of manufacturing a SOI wafer by combining and separating ion-implanted wafers is beginning to attract attention.
- This method is also referred to as an ion implantation separation method, in which an insulating layer is formed on at least one of the two wafers (bondue wafer), and hydrogen ions or rare gas ions are injected from the upper surface of the bond wafer.
- an insulating layer is formed on at least one of the two wafers (bondue wafer)
- hydrogen ions or rare gas ions are injected from the upper surface of the bond wafer.
- the surface into which the ions have been implanted is brought into close contact with the other wafer (base wafer) via the insulating layer, and then heat treatment is performed to remove a part of the bond wafer using the microbubble layer as a cleavage plane.
- FIG. 7 shows an example of the main steps of this ion implantation stripping method, which will be described in further detail.
- a base wafer 56 a to be a supporting substrate 56 and a bond wafer 52 a to be an SOI layer 52 are prepared as two raw materials, ie, wafers [FIG. 7 (a), step 100].
- wafers For example, mirror-polished silicon single crystal wafers are used as these wafers.
- These cleaning process is performed as necessary with respect Ueha (Step 1 0 1) c
- This Bondueha 5 buried after the 2 a surface of (B OX) an oxide film (insulating layer) oxide film 5 4 a [Fig. 7 (b), step 10]
- a silicon oxide film may be formed on the surface of the bonder 52a by subjecting the bonder 52a, which is a silicon single crystal wafer, to thermal oxidation.
- H 2 S 0 4 _H 2 0 may be carried out washed with 2 mixed solution (Step-up 1 0 5).
- H 2 S 0 4 - H 2 0 2 mixture in Yuck preparative washed Me art known stands for SPM (Sulfuric acid-Hydrogen peroxide Mixture ), a cleaning solution used for the removal of organic contaminants.
- SPM sulfuric acid-Hydrogen peroxide Mixture
- the base wafer 56a is brought into close contact with the base wafer 56a at room temperature through the oxide film 54a on the surface of the bond implant 52a on which the microbubble layer (encapsulation layer) 58 is formed. (d), Step 106).
- a heat treatment peeling heat treatment
- a part of the bond wafer 52a is peeled off from the encapsulation layer 58 to make the bond wafer 52a thinner [FIG. e)), step 108), and then bond heat treatment (FIG. 7 (f), step 110) to reduce the thickness of the bond wafer 52a and the base wafer 56a to the oxide film 54a.
- a wafer 50 having an SOI structure is produced by firmly bonding through the interface.
- the SOI wafer manufactured by the above-mentioned bonding method has an insulating film (layer) 54 and an SOI layer 52 separated and sequentially laminated on one main surface of the support substrate 56. Having a cross-sectional shape of the structure described. Also, there is a region called polishing sagging on the outer periphery of the surface of the two mirror-polished wafers to be bonded, and that portion is removed due to insufficient bonding, so that the insulating layer 54 and the SOI The diameter of the layer 52 is generally several mm smaller than that of the supporting substrate 56.
- the surface of the S ⁇ I layer 52 of the wafer having the S ⁇ I structure may be modified and the thickness of the S ⁇ I layer 52 may be controlled (step). 1 1 2).
- the surface (peeled surface) of the SOI layer 52 of the obtained SOI ⁇ wafer 50 having the SOI structure has damage left by hydrogen ion implantation, it is usually called polishing with a small polishing allowance called a touch polish. To remove the damaged layer.
- a heat treatment in an argon gas atmosphere is performed, a sacrificial oxidation process for performing thermal oxidation and oxide film removal to reduce the thickness of the SOI layer 52, or By appropriately combining the surface In some cases, an SOI wafer 50 having a thin S ⁇ I layer 52 with no damage is produced.
- a method of manufacturing silicon wafers such as silicon which is a raw material of SOI wafers, generally involves a slicing process in which a single crystal rod (ingot) manufactured by a single crystal manufacturing apparatus is sliced to obtain a thin disk-shaped wafer.
- a single crystal rod (ingot) manufactured by a single crystal manufacturing apparatus is sliced to obtain a thin disk-shaped wafer.
- the present invention has been made in view of the above-described problems of the related art, and it is an object of the present invention to provide a method for manufacturing an SOI wafer, which suppresses generation of a void when manufacturing an SOI wafer and has high productivity. Aim.
- the present inventors have conducted intensive studies and found that the quality of the raw material ⁇ a used as the bond Ia of the SOI ⁇ ⁇ aha has an influence on the occurrence of the above-mentioned voids. In particular, the pits on the surface of Bondueha were found to be a problem.
- pit clusters are defects in which small pits are gathered in an island shape, and the size of the aggregate is relatively large, for example, 0.5 ⁇ m or more.
- a pit cluster is a defect in which minute pits are gathered in an island shape, and the size of the aggregate is defined to be 0.5 ⁇ m or more. It is considered that the pit clusters are mainly caused by heavy metal contamination from the polishing process to the storage of the pit tank after polishing and the washing and drying processes.
- the method for producing an SOI wafer of the present invention is a raw material wafer.
- an insulating layer is formed on at least one of the wafers (bondue wafer), and the bond 18 is bonded to the other wafer (base wafer) without using an adhesive.
- the surface roughness of the insulating layer is set to a certain value or less, and the bond wafer and the base wafer are bonded together.
- the PV (Peak to Valley) value of the irregularities on the surface of the insulating layer (oxide film) is evaluated in an area of 10 m x 10 m, it is less than 1.5 nm, that is, more than 1.5 nm. It is necessary that the part does not exist. If the bonding between the bond wafer and the base wafer is performed in the state of the insulating layer having such a surface roughness, the occurrence of voids can be significantly reduced. .
- the PV value of the surface of the insulating layer be 1.5 nm or less by using a wafer having no pit cluster as the bond wafer.
- a wafer with no pit cluster is defined as a defect that is observed as an aggregate of microdefects that are not protruding when a defect of 0.08 / im or more is evaluated using, for example, a laser microscope with a confocal optical system. ⁇ ⁇ Not observed (not detected) in the eave plane. With this laser microscope with confocal optics, it is possible to detect whether the defect is a protrusion or a pit-like defect in the light and dark pattern of the defect depending on the method of measurement, and directly observe the distribution of the defect.
- the pit cluster generally consists of tens or more pit-like microdefects of about 0.2 to 0.08 m gathered in a size of 0.5 pm or more, for example, about 1 ⁇ m to 10 ⁇ m, Aggregates are formed and observed in the range of about 10 ⁇ m.
- an insulating layer is formed on at least one of the two wafers, ie, (bondue wafer). Hydrogen ions or rare gas ions are implanted from the upper surface of the bond wafer to form a microbubble layer inside the bond wafer. Then, the surface on which the ions are implanted is replaced with the insulating layer (oxide film). And then adhere to the other wafer (base wafer), and then apply heat treatment to separate the bond wafer using the microbubble layer as a cleavage plane to make the bonder wafer thinner. It is preferable to perform the bonding by firmly bonding the bonded wafer and the base wafer via the insulating layer.
- the cause of the void is considered as follows. In other words, if there is a pit cluster in which small pits are densely formed, if an oxide film is formed on this wafer, the characteristics of the oxide film are degraded, or the flatness (uniformity) of the oxide film itself is deteriorated. Deterioration of the surface roughness of the oxide film occurs, and the base wafer is bonded in this state, and the adhesion of the oxide film on the roughened surface of the oxide film is weak, resulting in voids. is there. Therefore, the generation of such voids is a problem peculiar to the method of manufacturing an SOI wafer by the bonding method (bonding method), and the generation of such a form does not occur in a method such as SIMOX.
- the method for detecting the pit clusters on the wafer surface is not particularly limited.For example, a defect of 0.08 ⁇ m or more is evaluated by a laser microscope of a confocal optical system, and the presence or absence of aggregates of minute defects is determined. Inspection is sufficient.
- pit clusters can be evaluated using atomic force microscopy (AFM).
- the generation of voids can be reduced.
- a mirror-polished wafer in an environment having a heavy metal concentration of 10 ppb or less as a bond a wafer.
- the main cause of the pit cluster is considered to be heavy metal contamination from the polishing process to the storage of the pit tank after polishing and the washing and drying processes. If contamination in this process is controlled and mirror polishing is performed, It is preferable to use a wafer as a raw material for producing an SOI wafer, which can produce a wafer having a small amount of water. Although it is preferable that there is no heavy metal contamination, the total amount of heavy metals such as Cu and Ni is preferably 10 ppb or less, more preferably 1 ppb or less.
- FIG. 1 is a schematic diagram showing an example of a process sequence of a method for manufacturing an SOI wafer according to the present invention. This is a flowchart shown together with 0.
- FIG. 2 is a map diagram showing the result of observation of the surface of the bonded bond wafer in Experimental Example 1 by a laser microscope for a confocal optical system.
- Fig. 3 shows the results of AFM observation of the bond surface before and after BOX oxidation in Experimental Example 1.
- (a) and (1) are schematic diagrams showing pit clusters on the bond surface before BOX oxidation and (a). (2) is a graph showing the depth of each pit,
- (b) and (1) are schematic diagrams showing the abnormal growth of the oxide film on the bondue surface after B ⁇ X oxidation, and
- (b) and (2) are It is a graph which shows the height of the abnormal growth part.
- Figure 4 shows the results of the same point observation of the confocal optical system with a laser microscope before and after lamination in Experimental Example 1, and (a) shows the portion of the bond wafer surface before the lamination after forming the BOX oxide film (1). 2) shows the surface state of the oxide film in (2), and (b) shows the enlarged surface state of the SII layer after bonding the parts corresponding to the above parts (1) and (2).
- FIG. 5 is a flowchart showing, together with a schematic diagram, the order of steps in the method for manufacturing an SOI wafer in Experimental Example 1.
- FIGS. 6A and 6B are explanatory diagrams showing an example of the structure of the SOI wafer, wherein FIG. 6A is a top explanatory diagram and FIG. 6B is a sectional explanatory diagram.
- FIG. 7 is a flowchart showing an example of a process sequence of a conventional method for manufacturing an SOI wafer together with a schematic diagram.
- FIG. 1 is a flowchart showing an example of a process sequence of a method for manufacturing an SOI wafer according to the present invention, together with a schematic diagram.
- FIG. 1 the same or similar members as those in FIG. 7 are denoted by the same reference numerals.
- the manufacturing flow of the SOI wafer of the present invention shown in FIG. 1 is basically the same as the manufacturing flow of the conventional SOI wafer shown in FIG. 7, so that the same steps will not be described again. Only the differences are described below.
- an insulating layer 54a is formed on at least one of the two wafers which are the raw material wafers, namely, the bonder 52a and the base wafer 56a, at least one of the bonders 52a.
- the PV value of the surface of the insulating layer 54 a formed on the bond heater 52 a Is smaller than 1.5 nm, in other words, the base wafer 56a and the bond wafer are in a state in which the PV value (evaluated with an error of ⁇ ⁇ ⁇ ⁇ m) is 1.5 nm or less. It is characterized in that the shellfish is occupied with 52a.
- Step 100a in order to form the insulating layer 54a having a low PV value, attention is paid to the quality of the silicon single crystal silicon used for the ponde wafer 52a. [FIG. 1 (a), Step 100a] can form an insulating layer 54a having a low PV value [FIG. 1 (a), Step 100a].
- Wafers without such pit clusters are manufactured with particular attention to heavy metal contamination after the polishing process. For example, a mirror polished and stored after polishing in an environment where the concentration of heavy metals is 10 ppb or less is used as a bond ea. For example, after polishing is completed, the wafer may be immersed in pure water or the like and stored while it is sent to the next process. The amount of heavy metals in the storage water is controlled.
- the process sequence after the BOX oxide film formation (step 102) is exactly the same as the process sequence of the conventional method of FIG. 7, but voids are generated in the obtained SOI wafer 50. It is possible to manufacture an SOI wafer 50 with a remarkably reduced yield and a good yield.
- FIG. 5 is a flowchart showing the order of steps in Experimental Example 1 together with a schematic diagram.
- a silicon wafer with a diameter of 300 mm, p-type, orientation ⁇ 100>, and a mirror-polished silicon wafer with a resistivity of 10 ⁇ cm Prepared as 52a [Fig. 5 (a), step 100].
- these wafers were washed (step 101).
- FIG. 9 is a schematic diagram showing the observation result of a confocal optical system on the surface of Doeha 52a with a laser microscope, as a map of the entire eha. Although an enlarged view of individual pit clusters PC is not shown, these pit clusters gather tens or more of pit-like microdefects of about 0.2 to 0.08 ⁇ m and 0.5 ⁇ m or more. For example, the defect formed an aggregate in a range of about 1 m to 10 m.
- a 150-nm-thick BOX oxide film 54a was formed by thermal oxidation on the surface of the bond wafer 52a where such a pit cluster PC exists [FIG. 5 (b), step 102]. Further, hydrogen ions were implanted to form an encapsulation layer 58 [FIG. 5 (c), step 104]. Next, SPM cleaning was performed (Step 105).
- FIG. 3 shows the results of AFM observation of the bond surface before and after B ⁇ X oxidation.
- A) and (1) are schematic diagrams showing pit clusters on the bond surface before BOX oxidation and (a). (2) is a graph showing the depth of each pit,
- (b) (1) is a schematic diagram showing the abnormal growth of the oxide film on the bondue surface after BOX oxidation, and
- (b) (2) is a graph showing the abnormalities. It is a graph which shows the height of a growth part.
- the abnormal growth X of a plurality of oxide films (the portion indicated by ⁇ in Figs.
- the surface into which the ion implantation of the bond 52a was implanted was brought into close contact with the base wafer 56a at room temperature [FIG. 5 (d), step 106]. More nitrogen A peeling heat treatment at 500 ° C. for 30 minutes is applied in an atmosphere to peel off a portion of the bonder 52 a to form a thin film on the bonder 52 a, thereby forming an SOI having a thickness of about 250 nm. The layer was obtained (FIG. 5 (e), step 108).
- the SOI layer 52 was firmly bonded by applying a bonding heat treatment at 110 ° C. for 2 hours in a nitrogen atmosphere, thereby producing a wafer 50 having an SOI structure (FIG. 5 (f)). 1 1 0].
- the SOI layer 52 is sacrificed, the silicon in the SOI layer 52 is oxidized to form an oxide film, and the oxide film is processed with hydrofluoric acid, so that the SOI layer 52 finally becomes about 150 A 50 nm thin film SOI wafer 50 was manufactured.
- FIG. 4 shows the results of the same point observation of the confocal optical system before and after bonding using a laser microscope.
- A shows the portion of the bond wafer surface after the formation of the BOX oxide film and before bonding (1)
- B shows the surface state of the oxide film
- b shows the enlarged surface state of the SOI layer after bonding the parts corresponding to the above parts (1) and (2).
- the oxide film becomes rough (abnormal growth) in the area where the pit cluster was present.
- void B with a diameter of 20 ⁇ m or more was observed in that part.
- Pondua 52a was manufactured under the same manufacturing conditions as in Experimental Example 1, and was inspected with a laser microscope with a confocal optical system.
- a heat treatment was performed in an argon gas atmosphere to remove the surface roughness and distortion of the SOI layer 52.
- This is a vertical heater heat treatment system (Batch furnace) and heat treatment at 1200 ° C for 1 hour under argon gas atmosphere.
- the roughness of the surface of the damage S I layer 52 caused by ion implantation is improved to some extent.
- the SOI layer 52 was polished by a CMP polishing apparatus. This was performed with a polishing allowance of about 40 nm.
- the SOI layer 52 is sacrificed, the silicon in the SOI layer 52 is oxidized to form an oxide film, and the oxide film is processed with hydrofluoric acid, so that the SOI layer 52 finally becomes about 150
- a thin film SOI wafer 50 nm of about nm was manufactured [FIG. 1 (g), step 1 12].
- the manufacturing process shown in the above embodiment is only an example, and if a manufacturing method of SOI having a laminating process, various processes such as cleaning, heat treatment, etc. may be added in addition thereto.
- the order of the steps can be partially changed, and the steps can be changed as appropriate according to the purpose, such as a step in which some steps such as CMP polishing for modifying the quality of the SOI layer and adjusting the thickness are omitted.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03791244A EP1548822A1 (en) | 2002-08-27 | 2003-08-21 | Method for manufacturing soi wafer |
US10/525,397 US20060154445A1 (en) | 2002-08-27 | 2003-08-21 | Method for manufacturing soi wafer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2002246422A JP2004087768A (ja) | 2002-08-27 | 2002-08-27 | Soiウエーハの製造方法 |
JP2002-246422 | 2002-08-27 |
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WO2004021433A1 true WO2004021433A1 (ja) | 2004-03-11 |
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PCT/JP2003/010559 WO2004021433A1 (ja) | 2002-08-27 | 2003-08-21 | Soiウエーハの製造方法 |
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US (1) | US20060154445A1 (ja) |
EP (1) | EP1548822A1 (ja) |
JP (1) | JP2004087768A (ja) |
KR (1) | KR20050047505A (ja) |
CN (1) | CN1675758A (ja) |
WO (1) | WO2004021433A1 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006216826A (ja) * | 2005-02-04 | 2006-08-17 | Sumco Corp | Soiウェーハの製造方法 |
TWI270928B (en) * | 2005-07-22 | 2007-01-11 | Sino American Silicon Products | Method of manufacturing composite wafer sructure |
FR2890489B1 (fr) * | 2005-09-08 | 2008-03-07 | Soitec Silicon On Insulator | Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant |
CN101341577B (zh) | 2005-12-19 | 2011-08-03 | 信越半导体股份有限公司 | Soi基板的制造方法及soi基板 |
JP5082299B2 (ja) * | 2006-05-25 | 2012-11-28 | 株式会社Sumco | 半導体基板の製造方法 |
JP2008066500A (ja) * | 2006-09-07 | 2008-03-21 | Sumco Corp | 貼り合わせウェーハおよびその製造方法 |
KR100828029B1 (ko) * | 2006-12-11 | 2008-05-08 | 삼성전자주식회사 | 스택형 반도체 장치의 제조 방법 |
EP2128891B1 (en) * | 2007-02-28 | 2015-09-02 | Shin-Etsu Chemical Co., Ltd. | Process for producing laminated substrate |
JP5125194B2 (ja) * | 2007-04-10 | 2013-01-23 | 信越半導体株式会社 | 貼り合わせウエーハの製造方法 |
JP2008263010A (ja) * | 2007-04-11 | 2008-10-30 | Shin Etsu Chem Co Ltd | Soi基板の製造方法 |
KR101111693B1 (ko) * | 2007-08-01 | 2012-02-14 | 김주영 | 태양전지용 다결정 실리콘 제조방법 |
JP2010021242A (ja) * | 2008-07-09 | 2010-01-28 | Sumco Corp | 貼り合わせ用ウェーハの欠陥検出方法 |
US8963337B2 (en) * | 2010-09-29 | 2015-02-24 | Varian Semiconductor Equipment Associates | Thin wafer support assembly |
CN103311172A (zh) | 2012-03-16 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | Soi衬底的形成方法 |
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JPH08264740A (ja) * | 1995-03-27 | 1996-10-11 | Shin Etsu Handotai Co Ltd | 結合ウェーハの製造方法及びこの方法により製造された結合ウェーハ |
JPH09232197A (ja) * | 1996-02-27 | 1997-09-05 | Sumitomo Sitix Corp | 貼り合わせ半導体ウエーハの製造方法 |
JPH10242015A (ja) * | 1997-02-27 | 1998-09-11 | Mitsubishi Materials Shilicon Corp | 張り合わせシリコン基板およびその製造方法 |
EP0926714A1 (en) * | 1997-12-25 | 1999-06-30 | Shin-Etsu Handotai Company Limited | Silicon wafer storage water and silicon wafer storage method |
JP2000030993A (ja) * | 1998-07-15 | 2000-01-28 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法およびsoiウェーハ |
US6060396A (en) * | 1997-12-17 | 2000-05-09 | Shin-Etsu Handotai Co., Ltd. | Polishing agent used for polishing semiconductor silicon wafers and polishing method using the same |
EP1052687A1 (en) * | 1998-02-02 | 2000-11-15 | Nippon Steel Corporation | Soi substrate and method for manufacturing the same |
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2002
- 2002-08-27 JP JP2002246422A patent/JP2004087768A/ja active Pending
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2003
- 2003-08-21 CN CNA03819578XA patent/CN1675758A/zh active Pending
- 2003-08-21 US US10/525,397 patent/US20060154445A1/en not_active Abandoned
- 2003-08-21 KR KR1020047020378A patent/KR20050047505A/ko not_active Application Discontinuation
- 2003-08-21 EP EP03791244A patent/EP1548822A1/en not_active Withdrawn
- 2003-08-21 WO PCT/JP2003/010559 patent/WO2004021433A1/ja not_active Application Discontinuation
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JPH02126625A (ja) * | 1988-11-05 | 1990-05-15 | Shin Etsu Handotai Co Ltd | 半導体ウエーハ接合方法 |
JPH07249599A (ja) * | 1994-03-14 | 1995-09-26 | Mitsubishi Materials Corp | 張り合わせ用半導体ウェーハの研磨表面粗さの管理方法 |
JPH08264740A (ja) * | 1995-03-27 | 1996-10-11 | Shin Etsu Handotai Co Ltd | 結合ウェーハの製造方法及びこの方法により製造された結合ウェーハ |
JPH09232197A (ja) * | 1996-02-27 | 1997-09-05 | Sumitomo Sitix Corp | 貼り合わせ半導体ウエーハの製造方法 |
JPH10242015A (ja) * | 1997-02-27 | 1998-09-11 | Mitsubishi Materials Shilicon Corp | 張り合わせシリコン基板およびその製造方法 |
US6060396A (en) * | 1997-12-17 | 2000-05-09 | Shin-Etsu Handotai Co., Ltd. | Polishing agent used for polishing semiconductor silicon wafers and polishing method using the same |
EP0926714A1 (en) * | 1997-12-25 | 1999-06-30 | Shin-Etsu Handotai Company Limited | Silicon wafer storage water and silicon wafer storage method |
EP1052687A1 (en) * | 1998-02-02 | 2000-11-15 | Nippon Steel Corporation | Soi substrate and method for manufacturing the same |
JP2000030993A (ja) * | 1998-07-15 | 2000-01-28 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法およびsoiウェーハ |
JP2000331899A (ja) * | 1999-05-21 | 2000-11-30 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法およびsoiウェーハ |
JP2002176155A (ja) * | 2000-12-08 | 2002-06-21 | Toshiba Ceramics Co Ltd | 貼り合わせsoiウエハの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1548822A1 (en) | 2005-06-29 |
JP2004087768A (ja) | 2004-03-18 |
KR20050047505A (ko) | 2005-05-20 |
CN1675758A (zh) | 2005-09-28 |
US20060154445A1 (en) | 2006-07-13 |
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