WO2004008512A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- WO2004008512A1 WO2004008512A1 PCT/JP2003/008736 JP0308736W WO2004008512A1 WO 2004008512 A1 WO2004008512 A1 WO 2004008512A1 JP 0308736 W JP0308736 W JP 0308736W WO 2004008512 A1 WO2004008512 A1 WO 2004008512A1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
- H01L29/365—Planar doping, e.g. atomic-plane doping, delta-doping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/931—Silicon carbide semiconductor
Definitions
- the present invention relates to a semiconductor device formed using a compound semiconductor layer, and more particularly to a semiconductor device suitable for applications such as high breakdown voltage and large current, and a method of manufacturing the same.
- power devices are semiconductor devices that pass a large current at high voltage resistance and are desired to have low loss.
- Si silicon
- compound semiconductors with wide band gaps such as silicon carbide (SiC)
- SiC silicon carbide
- silicon carbide semiconductors have a breakdown electric field one digit higher than that of silicon, and therefore can maintain relatively high reverse withstand voltage even if the depletion layer of the PN junction or Schottky junction is narrow. Therefore, it is expected to be a material for power devices with low on-resistance, high breakdown voltage, and low loss, because the thickness of the semiconductor layer can be reduced and the doping concentration can be increased.
- FIG. 2 is a cross-sectional view of a double injection type, storage type MISFET (ACCUFET) using i C.
- this conventional storage type MISFET is epitaxially grown on a low resistance SiC substrate 1001 and an SiC substrate 1001, and the SiC substrate 1001 is also P-type well region 1 003 formed by selective ion implantation on the surface region of high-resistance high-resistance Si C layer 1 002 and high-resistance Si C layer 1 002, p-type well region 1 003 (A storage channel layer 1 004 having five doped layers and a portion of the storage channel layer 1 004 formed on the surface region of the multiple layer and formed by alternately stacking a large number of high concentration (5 doped layers and an undoped layer) High concentration n-type formed by ion implantation And source region 1 006 containing impurities.
- a gate insulating film 1 008 is formed straddling a part of the storage channel layer 100 4 and the source region 1 006, and a gate electrode 1 0 10 is formed on the gate insulating film 1 008. It is formed. A portion of source region 1006 is removed to form a recess, and a portion of well region 1003 is exposed at the bottom of the recess. A contact layer 1005 containing a high concentration of p-type impurities is formed on the bottom of the recess, and a source electrode 1001 is filled on the contact layer 1005 and extends over the source region 1006. 1 is provided. The source electrode 101 is in ohmic contact with the resource region 1006 and the contact layer 1005 by heat treatment. Furthermore, on the back surface of the SiC substrate 1001, there is formed a drain electrode 102 which is in static contact with the Si substrate 1001.
- n-type dopant preparative concentration of the high-resistance S i C layer 1 002 is made from the normal 1 X 1 0 15 c m_ 3 3 X 1 0 16 cm- 3 or so.
- the dopant concentration depends on the desired breakdown voltage, that is, the higher the desired breakdown voltage, the higher the concentration.
- the impurity concentration of the accumulation type channel layer 1008 is high to some extent, the channel resistance becomes low, but in this case, the depletion layer on the surface of the high resistance Si C layer 1 002 does not spread, and the breakdown voltage decreases. That is, there is a trade-off between high withstand voltage and low loss, and therefore the concentration of the storage channel layer can not be increased.
- nickel is often used for the n-type silicon carbide semiconductor ohmic electrode, and heat treatment at 900 ° C. or higher in an inert gas atmosphere such as argon or nitrogen. Is formed to form nickel silicide (Ni 2 Si), which contributes to the reduction of contact resistance.
- the contact resistance of the ceramic electrode changes greatly depending on the doping concentration of silicon carbide, and it is described that it is difficult to obtain the ceramic electrode at a doping concentration of 10 17 cm -3 or less. Therefore, an n-type source region having an n-type impurity concentration of about 1 ⁇ 10 19 cm ⁇ 3 is formed.
- Contact layer 1 005 which is a high concentration P-type layer, is a portion for applying a bias to the well region 1 003. Therefore, the source electrode 1 0 1 1 is a contact layer 1 00 It is necessary to be in direct contact with 5. Therefore, in this example, a recess is formed in the source region 1 0 0 6 and a source electrode 1 0 0 1 1 is formed along the wall surface of the recess so that the source electrode 1 0 0 5 is formed. The voltage is applied directly from 1 1.
- Silicon carbide has high bonding energy between carbon and silicon, and recovery is difficult if crystal defects are caused by ion implantation.
- the implantation dose is large, and in particular defects become a problem. For this reason, it is necessary to keep the substrate at a high temperature of 500 ° C. or higher to carry out ion implantation, and to make the temperature of the activated aniline after the implantation a high temperature of 140 ° C. or higher. There is a problem that the cost is high.
- An object of the present invention is to realize a high breakdown voltage, low loss semiconductor device while keeping the contact resistance of the source electrode low without forming the source region by ion implantation.
- a semiconductor device includes: a substrate; an active region made of a compound semiconductor provided on the substrate, and at least one first semiconductor layer functioning as a carrier travel region; and the first semiconductor layer And an active region formed by alternately laminating at least two second semiconductor layers including a carrier impurity having a concentration higher than that of the first semiconductor layer and being thinner than the first semiconductor layer, and from the surface of the active region And at least one electrode made of a conductive material which penetrates into the active region and contacts at least the second semiconductor layers.
- the device further includes a gate insulating film provided on the active region, and a gate electrode provided on the gate insulating film, wherein the at least one electrode is at least one of a source electrode and a drain electrode.
- the semiconductor device functions as a MISFET. In that case, it can also function as a storage-type M I S F E T.
- the semiconductor device further comprises a Schottky gate electrode provided on the active region, and the at least one electrode is a source electrode and a drain electrode provided so as to sandwich the gate electrode, the semiconductor The device acts as a MESFET.
- the semiconductor device further includes a Schottky gate electrode in Schottky contact with the active region, and in the case where the electrode is a single ohmic electrode, the semiconductor device functions as a lateral Schottky diode.
- the compound semiconductor layer is a SiC layer
- the at least one electrode is preferably made of a conductor material containing at least nickel.
- a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device in which a part of a semiconductor layer provided on a substrate is used as an active region, and at least one first semiconductor layer is formed on the substrate.
- An active region is formed by alternately laminating at least two second semiconductor layers including a carrier impurity having a higher concentration than the first semiconductor layer and having a film thickness thinner than the first semiconductor layer.
- the compound semiconductor can be used to reduce the manufacturing cost of semiconductor devices with high performance such as high power and high breakdown voltage.
- the electrode and the at least second semiconductor layers be in ohmic contact with each other.
- the conductor film is a film containing at least nickel, and in the step (c), the heat treatment is preferably performed at a high temperature of 600 ° C. or more in an inert gas atmosphere.
- FIG. 1 is a cross-sectional view of a double injection type, storage type M I S F E T (A C C U F E T) using S i C according to the first embodiment of the present invention.
- FIG. 6 is a partial band diagram illustrating the shape of the conduction band edge along the line;
- FIGS. 3 (a) to 3 (f) are cross-sectional views showing the manufacturing steps of the semiconductor device of the first embodiment.
- FIG. 4 is a cross-sectional view showing a structure of a trench M I S F E T which is a semiconductor device of a second embodiment of the present invention.
- 5 (a) to 5 (f) are cross-sectional views showing the manufacturing steps of the semiconductor device of the second embodiment.
- FIG. 6 is a cross-sectional view showing a schematic structure of a horizontal n-channel M I S F E T T of the third embodiment.
- FIG. 7 is a cross-sectional view showing a structure of ACCUFET according to a fourth embodiment of the present invention.
- FIG. 8 is a cross-sectional view showing a schematic structure of a Schottky diode which is a power semiconductor device according to a fifth embodiment of the present invention.
- FIG. 9 is a cross-sectional view showing a schematic structure of a power semiconductor device MESF according to a sixth embodiment of the present invention.
- FIG. 10 is a cross-sectional view of a semiconductor device (semiconductor integrated circuit device) according to a seventh embodiment of the present invention.
- FIGS. 12 (a) and 12 (b) are cross-sectional views showing the steps from the formation of an insulating film to the formation of an electrode or a conductor film of each element in the manufacturing steps of the semiconductor device of the eighth embodiment.
- 3 (a) and (b) are cross-sectional views showing the steps from the formation of the upper electrode of the capacitor to the formation of the contact hole in the conductor of each element in the process of manufacturing the semiconductor device of the eighth embodiment. is there.
- FIG. 14 is a SEM picture showing the structure of the source electrode and the underlying Si C layer formed in the step shown in FIG. 3 (e).
- FIG. 15 is a cross-sectional view of a conventional double injection type storage-type M I S F E T (A C C U F E T) using S i C.
- FIG. 16 is a diagram showing I-V characteristic data of double injection type and storage type M I S F E T (A C C U F E T) using S i C according to the first embodiment of the present invention.
- FIG. 17 is a diagram showing I-V characteristic data of a double injection type, storage type M ACFT (ACCUFT) using a conventional structure of SiC. Best embodiment
- FIG. 1 is a cross-sectional view of a double injection-type, storage-type M I S F E T (A C C U F E T) using S i C according to the first embodiment of the present invention.
- the storage type MISFET of the first embodiment is epitaxially grown on a low resistance SiC substrate 101 and an SiC substrate 101.
- a high resistance SiC layer 102 having a resistance higher than 1 and a P type well region 103 formed by selective ion implantation on the surface region of the high resistance SiC layer 102;
- Territory N-type storage channel layer 104 having multiple ⁇ 5 doped layers (active regions) formed in the surface region of region 103 and a high concentration of p-type impurity implanted into well region 103 Provided with the contact layer 1 05.
- a gate insulating film 108 is formed on the storage channel layer 104, and a gate electrode 110 is formed on the gate insulating film 108.
- a drain electrode 112 that is in atomic contact with the Si substrate 101.
- the storage channel layer 104 is, as shown enlarged in the lower part of FIG. 1, an approximately 40 nm thick single layer 104 b (first semiconductor layer) made of undoped SiC single crystal; Layers of n-type impurities with a peak concentration of 5 ⁇ 10 17 cm- 3 and a thickness of about 10 nm (5 double layers 1 04 a (second semiconductor layer) are alternately laminated in two cycles. Furthermore, it has a structure in which an approximately 40 nm thick and single layer 104 b is stacked on top of that and (5 double layer 104 a is formed into an undoped layer 104 b by quantum effect. Such a thin layer is formed so thin as to allow penetration of the carrier.
- the feature of the present embodiment is that the source electrode 1 1 enters the storage channel layer 1 04 and the contact layer 1 05 by reaction with S i C and directly contacts the contact layer 10 5 The point is that 1 is provided. Then, conventionally, a source region which is formed by implanting a high concentration impurity into the storage channel layer 104 is not formed.
- the source electrode 1 1 1 is formed of a nickel silicide layer in which a nickel film is sequentially formed on the storage channel layer 104 and then nickel is reacted with SiC by heat treatment. During this heat treatment, mainly nickel diffuses into the storage channel layer 104 and the contact layer 105 by diffusion, so that the source electrode 1 1 1 is formed of ⁇ 5 dopant layers in the storage channel layer 104. In addition to being substantially in contact with a, contact layer 105 is also substantially in contact with a. The depth to which nickel penetrates after heat treatment is the thickness of the first nickel film and It can be controlled by heat treatment conditions.
- FIG. 6 is a partial band diagram showing the shape of the conduction band end.
- Fig. 2 (a) particularly high electron mobility can be obtained in the single layer because impurity ion scattering in the undoped layer is reduced.
- FIG. 2 (b) the conduction band edge of the entire active region is indicated by a broken line in FIG. 2 ((5 conduction band edge of the doped layer and conduction band edge of the undoped layer are connected.
- the quantum effect causes a quantum level to be generated in the (5 doped layer 1 04 a, and the wave function of the localized electron in the (5 doped layer 1 04 a becomes broadened to some extent.
- the potential of the multiple (5 doped layer is increased, and the quantum effect is If electrons spread from the 5 doped layer 104 a to the undoped layer 104 b, electrons are constantly supplied to the ⁇ 5 doped layer 104 a and the undoped layer 104 b. Since the electrons flow through the undoped layer 104 b with low impurity concentration, the impurity ion scattering can be reduced. On the other hand, in the off state, the entire multiple 6 doped layer is depleted, and no electrons exist in the storage channel layer 104. Therefore, the undoped layer 10 4 b with a low impurity concentration is obtained.
- the breakdown voltage is specified by the above, and a high breakdown voltage value can be obtained in the entire accumulation channel layer 104. Therefore, a configuration is made such that a large current flows between the source and drain using the accumulation channel layer 104. It is possible to simultaneously achieve high channel mobility and high breakdown voltage in the ACCUFET, and, naturally, in the state where the entire storage channel layer is depleted, it is possible to obtain the undoped layer and the drain layer. Since the carrier does not exist in the layer, high pressure resistance is exhibited.This function and effect are described in Japanese Patent Application No. 2 0 0 2-5 0 4 5 6, Japanese Patent No. 2 0 0 1-5 6 6 1 9 Listed in No. 3 etc. It is as you are.
- the manufacturing process can be simplified.
- S i C is a very hard material, and it is necessary to perform ion implantation with high energy and by changing the implantation energy in multiple stages, which requires a great deal of labor, but according to this embodiment resource region formation of It is possible to omit the ion implantation step to simplify the manufacturing process and reduce the manufacturing cost.
- a bias can be supplied from the source electrode 11 1 to the well region 103 via the contact region 105.
- S i C is a very hard material, and etching requires a great deal of time, but according to this embodiment, the etching step for forming the source electrode can be omitted, and the manufacturing process can be simplified and the manufacturing cost can be reduced. It can be reduced.
- the semiconductor device of the present embodiment unlike the conventional semiconductor device shown in FIG. 15, from the source electrode 11 1 directly to the source region, without passing through the source region. Because the carrier is supplied, there is no problem in the operation of the semiconductor device. Rather, the on-resistance can be further reduced.
- FIGS. 3 (a) to 3 (f) are cross-sectional views showing the manufacturing steps of the semiconductor device of the first embodiment.
- the dopant concentration of the high resistance Si C layer 102 is in the range of 1 ⁇ 10 15 cm- 3 to 11 1 O ie cm 3 , thickness It is desirable for the length to be 10 ⁇ m or more.
- ions of aluminum (AI) or boron (B), which are p-type impurities, are implanted into a part of the high resistance SiC layer 102 to form a well region 103.
- a silicon oxide film (not shown) having a thickness of about 3 m serving as an implantation mask is deposited on the high resistance Si C layer 102 by CVD or the like. For photolithography and dry etching Therefore, the portion of the silicon oxide film where the metal region 103 is to be formed is opened. Thereafter, AI or B ion implantation is performed with the substrate temperature kept at a high temperature of 500 ° C.
- Dopant Bok concentration Ueru region 1 03 is generally in the range of approximately 1 X 1 0 17 cm- 3 ⁇ 1 X 1 0 18 c m_ 3, its depth so as not to pinch off a 1 m before and after.
- a high concentration P-type impurity (AI or B) is ion-implanted on the surface of the well region 103 to form a p + -type contact region 1 Form 0 5
- the thickness of the contact region 105 is around 300 nm, and the doping concentration is 1 ⁇ 10 1 ⁇ cm 3 or more.
- the ion implantation at this time is performed in the same manner as in the well region 103.
- an activation amino acid is carried out at about 170 ° C. for about 30 minutes in an inert gas such as argon.
- multiple ⁇ dopants serving as the channel of the MISFET are formed on each surface of the high resistance Si C layer 102, the ring region 103 and the contact region 105.
- Layer 1 04 X is formed. Multiplexed 5 layer 1 04 X is a 40 nm thick undoped layer 1 04 b (first semiconductor layer) and n type dopant peak concentration 1 x 10 18 cm 3 and 10 nm thick ⁇ 5 doped layers 104 a (second semiconductor layers) are alternately stacked for two cycles, and further, an undoped layer 104 b with a thickness of 40 nm is stacked thereon.
- the crystal growth apparatus and crystal growth method disclosed in Patent Application Nos. 2001-5661193 are used. That is, a SiC substrate is placed in a thermal CVD reactor, hydrogen and argon are flowed as dilution gases, and propane gas and silane gas are introduced into the reactor as source gases. The pressure in the growth furnace is maintained at 0.0933 MP a, and the substrate temperature is controlled at 1 600 ° C. In this state, a 40 nm thick undoped layer is epitaxially grown. In addition to the above-mentioned dilution gas and source gas, nitrogen is supplied as a doping gas in the form of pulses to the growth reactor for the formation of the doped layer.
- the ⁇ 5 doped layer 1 04 a with a thickness of 1 O nm is epitaxially grown.
- the dopant concentration is controlled by adjusting the pulse on / off time width of the pulse valve and the duty ratio. In this way, three layers of — Alternately depositing a copper layer 104 b and two ⁇ -doped layers 104 a to form a multiple (5-doped layer 104 X).
- a silicon oxide film 108 X is formed by thermally oxidizing the surface of the multiple ⁇ 5 doped layer 104 X (undoped layer 104 b).
- a SiC substrate is placed in a quartz tube, and the published oxygen is introduced into the quartz tube at a flow rate of 2.5 (I in), and the substrate temperature is maintained at 110 ° C. for 3 hours.
- a thermal oxide film having a thickness of about 40 nm is formed.
- a drain electrode 112 made of a nickel film having a thickness of 200 nm is formed by vapor deposition.
- the heat treatment of the drain electrode 12 is performed after forming the source electrode later.
- a resist film (not shown) is formed on the silicon oxide film 108 X to form a region for forming a source electrode by photolithography.
- the silicon oxide film 108 X is patterned by hydrofluoric acid etching to form a gate insulating film 108 surrounding a region in which a source electrode is to be formed.
- a nickel film (Ni film) having a thickness of 200 nm is sequentially deposited on the substrate by vacuum evaporation or the like while leaving the resist film, and then lift-off is performed to form a nickel film 1 1 1 x Leave.
- the Ni film 111 X is subjected to a heat treatment under the conditions of a temperature of 100 ° C. for 2 minutes in an inert gas atmosphere such as nitrogen. During this heat treatment, mutual diffusion and reaction of nickel (Ni) and silicon carbide (Sic) occur to form a source electrode 111 made mainly of nickel silicide. Then, a portion of the multiple source layer 104 X that is not taken into the source electrode 111 is the accumulation channel layer 104.
- FIG. 14 is an SEM photograph showing the structure of the source electrode formed in the step shown in FIG. 3 (e) and the underlying Si C layer. As shown in the figure, it can be seen that the source electrode penetrates from the surface of the substrate to a portion about 200 nm deep. In the sample for which this SEM photograph was made, since the thickness of the multiple ⁇ -doped layer 104 X in this embodiment is 140 nm in the multiple (5 doped layer is not formed, It is sufficiently possible to bring the source electrode 1 1 1 made of silicon into contact with the contact area 1 0 5 It turns out that it is
- an aluminum film is deposited on the substrate by vapor deposition, and then the aluminum film is patterned by photo lithography and wet etching to form a gate insulating film.
- the gate electrode 110 is formed on the surface 108.
- the following processing is required. First, an implantation mask made of a silicon oxide film or the like in which a region other than the region for implanting n-type impurity ions is covered and a region for implanting n-type impurity ions is opened is formed on the substrate. Heat to a temperature of 800 ° C and perform ion implantation of nitrogen ions (N +) etc.
- first ion implantation conditions are an acceleration voltage 1 80 ke V, a dose of 1 5 xl 0 14 atoms -.
- second ion implantation conditions are an acceleration voltage 1 30 ke V, a dose Amount 1 x 1 0 1 "atoms ⁇ cm- 2 and the conditions for the third ion implantation are acceleration voltage 1 10 10 ke V, dose amount 5 1 0 , 3 atoms ⁇ c m _ 2 , 4 th ion
- the implantation conditions are an acceleration voltage of 100 ke V and a dose of 8 ⁇ 10 13 atoms ⁇ cm- 2 and the conditions of the fifth ion implantation are an acceleration voltage of 60 ke V and a dose of 6 ⁇ 10 13 atoms' cm -.
- 6th ion implantation conditions are an acceleration voltage 3 0 ke V, a dose of 5 x 1 0 13 atoms ⁇ cm- 2 the depth of the ion implantation is about 0.5 3 ⁇ m.
- the ion implantation process in this conventional manufacturing process also has the following problems. That is, when forming the opening in the implantation mask made of a silicon oxide film or the like, the underlying SiC layer is also etched slightly, so that only the source region is recessed to form a step in the source region. Then, the electric field may be concentrated on the gate oxide film on such a step, and the breakdown voltage may drop.
- FIG. 16 is a diagram showing measurement results of drain current (Id) -drain voltage (Vd) characteristics (1 characteristic) of an ACCUFET formed using the manufacturing method of the present embodiment.
- the data shown in FIG. 16 is a sample of a double injection type, storage type MISFET (AC CU FET) having a gate length of 2 m and a total gate width of 1.2 mm using the manufacturing method of this embodiment. It is obtained by making a prototype and measuring its characteristics. The distance between adjacent P-type well regions in the sample ACCUFET is 5 m.
- the MOS operation was certainly confirmed.
- FIG. 17 is a diagram showing the measurement results of the I-V characteristics of the double injection type, storage type M ACFT (A C C U F E T) of the conventional structure.
- the difference between the manufacturing process of the conventional A.sub.C.sub.C.sub.C U.sub.FT and the manufacturing process of the A.sub.C.sub.C F.sub.E.sub .-- T in this embodiment is only the presence or absence of the formation of the source region by ion implantation, and the other two processes are the same. Then, as can be seen by comparing FIG. 16 and FIG. 17, there is no significant change in the value of the drain current of the ACCUFET even without formation of the source region by ion implantation as in this embodiment, and provided directly in the channel. There was no increase in contact resistance between the source electrode and the channel.
- the breakdown voltage between the source and drain in the OFF state of the ACCUFET of this embodiment was 600 V.
- the storage channel layer 104 is formed of a multiple ⁇ 5 doped layer 1 04 X formed by laminating an extremely thin doped layer 1 04 a and a relatively thick undoped layer 1 04 b. It is done. Therefore, in the storage channel layer 104, the carriers exuded from the (5 doped layer 1 04 a travel through the undoped layer 1 04 b with high crystallinity and little impurity ion scattering due to quantum effects etc. Storage channel layer 104 is obtained.
- the source electrode 1 1 1 substantially contacts only the ⁇ 5 doped layer 1 04 a of the storage channel layer 1 04 but not the undoped layer 1 04 b
- the S-doped layer 1 04 a Since carriers are supplied to the layer 104 b, a sufficiently high drain current can be obtained.
- the impurity concentration of the channel layer is low, so even if the source electrode is brought into direct contact with the channel layer, it does not form an ohmic contact, but in the present invention, the S doped layer has high impurity concentration.
- the source electrode can be in ohmic contact with the S-doped layer.
- Carrier is supplied from (5 layers to 1 layer).
- FIG. 4 is a cross-sectional view showing a structure of a trench M I S F E T which is a semiconductor device of a second embodiment of the present invention.
- the trench MISFET according to the second embodiment is epitaxially grown on a low resistance SiC substrate 201 and an SiC substrate 201, and the SiC substrate 201 is formed.
- a P-type base layer 203 formed by selective ion implantation in the surface region of the high-resistance SiC layer 202; It has a multiple (5 doped layer (active region) formed along the wall surface of the trench which penetrates a part of the p-type base layer 2 0 3 and reaches the high resistance Si c layer 2 0 2
- An n-type channel layer 204 and a contact region 205 formed by implanting a high concentration p-type impurity into the p base layer 203 are also provided.
- a gate insulating film 2 0 8 is formed on top of the gate insulating film 2 0 8, and a gate electrode 2 10 0 is formed on the gate insulating film 2 0 8. Furthermore, the back surface of the Si C substrate 2 0 1 On the S i substrate 2 0 1 substantially Mikku drain electrodes 2 1 2 in contact is formed.
- the channel layer 24 is an undoped layer (low concentration layer) 24 of about 40 nm in thickness made of undoped Si single crystal, and an n-type impurity.
- the structure is a laminated structure of 40 nm and 250 nm.
- the n-type doped layer 2 0 4 a is formed as thin as possible to allow the carrier to penetrate to the 1st and 2 nd layers 2 0 4 b by the quantum effect.
- Such ⁇ -doping layers are described in the patent application 200 1-5 6 6 1 9 It is obtained using the crystal growth apparatus and crystal growth method disclosed in the specification and drawings of No. 3. The action and effect of having this multiple ⁇ 5 doped layer are as described in Japanese Patent Application No. 2 0 2 0 5 0 4 5 6 or the like.
- the feature of the present embodiment is that the source electrode 2 intrudes into the channel layer 24 and the contact region 205 by reaction with S i C and directly contacts the contact region 2 0 5 11 is the point provided. And, conventionally, the source region which has been formed by implanting a high concentration impurity into the channel layer 24 and the p-type base layer 203 is not formed.
- the source electrode 21 1 is formed of a nickel silicide layer and an aluminum alloy layer in which nickel and SiC react with each other by heat treatment. It is configured.
- the source electrode 2 1 1 is formed by: ⁇ 5 doped layer 2 in the channel layer 2 0 4 In addition to being substantially in contact with 0 4 a, it is also in contact with contact region 2 0 5.
- the manufacturing process can be simplified.
- S i C is a very hard material, and it is necessary to perform ion implantation with high energy and by changing the implantation energy in multiple stages, which requires a great deal of labor, but according to this embodiment resource region formation
- the ion implantation step for the ion implantation can be omitted, and the manufacturing process can be simplified and the manufacturing cost can be reduced.
- a bias can be supplied from the source electrode 21 1 to the base layer 23 via the contact region 205.
- S i C is a very hard material, and etching requires a great deal of work, but according to this embodiment, the etching step for forming the source electrode can be omitted, and the manufacturing process can be simplified and the manufacturing cost can be reduced. It is possible to reduce wrinkles.
- 5 (a) to 5 (f) are cross-sectional views showing the manufacturing steps of the semiconductor device of the second embodiment.
- a plane inclined by 8 ° in the ⁇ 1 1-2 0> direction from the (0 0 0 1) plane ((0 0 0 1) off-plane) Si C substrate 201 is prepared with doping concentration of n-type impurity (nitrogen) of about 1 ⁇ 10 18 cm- 3 to 5 10 19 cm 3 , and epitaxial growth of high resistance Si C layer 202 is performed.
- n-type impurity nitrogen
- Si C substrate 201 for example, using silane and propane as source gases, hydrogen as a carrier gas, and nitrogen gas as a dopant gas, the impurity having a concentration lower than that of the SiC substrate 201 by thermal CVD.
- a high resistance SiC layer 202 containing (dopant) is epitaxially grown.
- the dopant concentration of the high resistance Si C layer 202 is in the range of 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 16 cm 3.
- the thickness is preferably 10 ⁇ m or more.
- a p-type base layer 203 is epitaxially grown by thermal CV D using silane and propane as source gases, hydrogen as a carrier gas, and trimethylaluminum (TMA) as a dopant gas.
- TMA trimethylaluminum
- the dopant concentration in the base layer 203 be approximately 2 ⁇ 10 17 cm 3 and the thickness be approximately 2 / m.
- ion implantation of p-type impurity (Al) or boron (B) is performed on part of the base layer 203 to form a high-concentration p-type contact region.
- Form 205 In order to form the contact region 205, first, a silicon oxide film (not shown) having a thickness of about 3 j! M to be an injection mask is deposited on the base layer 203 by a CVD method or the like. A portion of the silicon oxide film to form the contact region 205 is opened by lithography and dry etching. Thereafter, in order to reduce implantation defects, AI or B ion implantation is performed with the substrate temperature maintained at a high temperature of 500 ° C.
- the depth of the contact region 205 is about 300 nm, and the dopant concentration is preferably about 1 ⁇ 10 18 cm ⁇ 3 .
- a trench 206 which penetrates the base layer 203 and reaches the high resistance Si C layer 202 is formed by reactive ion etching (RIE).
- multiple 5-doped layers 204 X serving as the channel of the MISFET are formed along the wall surfaces of the trenches 206, that is, on the surfaces of the high resistance Si C layer 202, the base layer 203 and the contact region 205.
- Multiple (5-doped layer 204 X) is a 40 nm thick undoped layer 204 b and an n-type dopant peak concentration of 1 ⁇ 10 18 cm 3 and a 1 O nm thick ⁇ -doped layer 204 a It has a structure in which two cycles of alternating cycles are alternately laminated, and further a 40 nm thick undoped layer 204b is laminated thereon.
- a crystal growth apparatus and a crystal growth method disclosed in the specification and drawings of Patent Application Nos. 2001 to 566193 are used. That is, a SiC substrate is placed in a thermal CVD reactor, hydrogen and argon are flowed as dilution gases, and propane gas and silane gas are introduced into the reactor as source gases. The pressure in the growth furnace is maintained at 0.993 M Pa, and the substrate temperature is controlled at 1 600 ° C. In this state, an epitaxial layer 204 b of 40 nm in thickness is epitaxially grown. In addition to the above-mentioned dilution gas and source gas, nitrogen is supplied as a doping gas in the form of pulses to the growth reactor in order to form the doped layer.
- an epitaxial layer 20 4 a of 1 O n m thick is epitaxially grown.
- the dopant concentration is controlled by adjusting the pulse valve on / off time width and the duty ratio.
- the surface of the multiple (S-doped layer 204 X (and-doped layer 204 b)) is oxidized to form a silicon oxide film 208 X.
- a SiC substrate is placed in the quartz tube, and the published oxygen is introduced into the quartz tube at a flow rate of 2.5 (I in), and the substrate temperature is maintained at 1100 ° C. for 3 hours By oxidation, a thermal oxide film of about 40 nm in thickness is formed.
- a gate electrode 210 is formed on the silicon oxide film 208 X.
- disilane and hydrogen as source gases dopant gas by LP CV D method.
- the polysilicon film is patterned by photolithography and dry etching to fill the trenches 206 Form a contact electrode 210.
- a drain electrode 212 made of a 200 nm thick nickel film is formed on the back surface of the SiC substrate 201 by a vapor deposition method.
- the heat treatment of the drain electrode 22 is performed after the formation of the source electrode later.
- a resist film (not shown) in which a region for forming a source electrode is opened on the silicon oxide film 20 8 X by photolithography.
- the silicon oxide film 208 X is patterned by hydrofluoric acid etching to form a gate insulating film 208.
- a 200 nm thick nickel film (N i film) is sequentially deposited on the substrate by vacuum evaporation or the like until the resist film is left, and then the Ni film 21 1 X is left by liftoff.
- the Ni film 21 1 X is heat-treated under conditions of a temperature of 1000 ° C. for 2 minutes in an inert gas atmosphere such as nitrogen. During this heat treatment, mutual diffusion and reaction of nickel (N i) and silicon carbide (S i C) occur to form a source electrode 21 1 mainly made of nickel silicide. Then, a portion of the multiple ⁇ doped layer 204 X which is not taken into the source electrode 21 1 is the channel layer 204. At this time, at the same time, the nickel film on the back surface of the SiC substrate 201 also becomes nickel silicide and a drain electrode 212 is formed.
- an inert gas atmosphere such as nitrogen.
- a trench MISFET with a gate length of 2 / m and a total gate width of 2.1 mm was fabricated on the basis of the manufacturing method of this embodiment, and its characteristics were measured. Gate voltage 5 V, drain and source voltage The characteristic of a drain current of 9.5 mA at 2 V was obtained. This value is about the same drain current as the conventional trench type M I S F E T that forms a resource region by ion implantation. In addition, the breakdown voltage between the source and drain in the off state was 600 V.
- the channel layer 204 is formed of a multiple ⁇ double layer 204 X formed by laminating an ultrathin double layer 204 a and a relatively thick double layer 204 b. ing. Therefore, in the channel layer 204, The carrier layer exuded from the ⁇ -doped layer 204 a travels through the undoped layer 204 b with high crystallinity and less impurity ion scattering, so that a channel layer 214 with high channel mobility is obtained. can get.
- the source electrode 21 1 is substantially in ohmic contact with only the ⁇ -doped layer 2 0 4 a of the channel layer 2 0 4, and is in ohmic contact with the undoped layer 2 0 4 b.
- the carrier is supplied from the (5) doped layer 204a to the undoped layer 204b, a sufficiently high drain current can be obtained.
- FIG. 6 is a cross-sectional view showing a schematic structure of a horizontal p-channel type MISFET of the third embodiment. As shown in the figure, an average concentration of about 1 is obtained on an n-type Si C substrate 301 doped with nitrogen (n-type impurity) at a concentration of 1 ⁇ 10 18 atoms cm ⁇ 3. x
- Three p-type doped layers with a thickness of about 10 nm including 1 x 10 18 atoms ⁇ cm- 3 ) aluminum (5 doped layers 3 04 a, undoped Si It is constructed by alternately laminating four undoped layers 3 0 4 b of about 4 O nm in thickness made of C single crystal, and the p-type doped layer 3 0 4 a is formed by an AND process by quantum effect. Since the layer is formed thin enough to allow carrier penetration into layer 304b, the effect as described in Japanese Patent Application No. 2 0 0 2-5 0 0 4 5 6 can be exhibited. it can.
- a source region and a drain region such as the MISFET (see FIG. 1 of the same document) disclosed in Japanese Patent Application No. 2 0 5 0 5 5 6 are provided.
- the source region and the drain region are formed.
- the Ni film is formed in the region where the source electrode and the drain electrode are to be formed on the substrate without performing the ion implantation process, and the Ni is diffused into the substrate by the heat treatment of the Ni film.
- the source electrode and drain electrode made of alloy film are formed.
- FIG. 7 is a cross-sectional view showing the structure of an ACCUFET according to a fourth embodiment of the present invention.
- a P-type Si C substrate 401 doped with aluminum (p-type impurity) at a concentration of 1 ⁇ 10 18 atoms cm ⁇ 3
- an average concentration of approximately 1 ⁇ 1 0 1 7 atoms ⁇ cm- 3 aluminum doped p-type lower region 402 and lower region 402 formed on average region approximately 1 x 1 0 1 7 atoms ⁇ cm _ 3
- Gate insulating film consisting of N-type multiple S doped layer 40 4 (active region) doped with nitrogen and SiO 2 formed on multiple (5 doped layer 40 4
- a gate electrode comprising a Ni alloy film formed on the gate insulating film and a Ni alloy in contact with the multiple ⁇ -doped layer and the lower region;
- a source electrode 4 1 1 a and a drain electrode 4 1 1 b made of a film, and a back surface electrode 4 1 2 made of an
- the thickness of the multiple (5-doped layer 404) containing nitrogen at a high concentration is approximately 1
- the thickness of the multiple (5-doped layer 404) containing nitrogen at a high concentration is approximately 1
- the thickness of the multiple (5-doped layer 404) containing nitrogen at a high concentration is approximately 1
- the undoped layers 404 b are alternately stacked.
- 55 doped layer 404 a is formed thin enough to allow penetration of the carrier to undoped layer 404 b by quantum effect, so that Japanese Patent Application No. 2 0 0 2 — 5 0 0
- the effects as described in 4 5 6 can be exhibited.
- a quantum level generates a quantum level in the ⁇ 5 doped layer 4 0 4 a due to the quantum effect, and the wave function of local electrons in the ⁇ 5 doped layer 4 0 4 a has a certain extent of spread.
- the electrons are distributed not only in the ⁇ -doped layer 404 a but also in the undoped layer 404 b.
- the breakdown voltage is determined by the layer 404b, and a high breakdown voltage value can be obtained over the entire multiple layer 54. Therefore, the source using the multiple layer ⁇ 54> is used. In ACCUFETs configured to carry large currents between drains, high And channel mobility, it is possible to realize a high breakdown voltage simultaneously.
- the ACCUFET of this embodiment is provided with a source region and drain region as in the ACCUFET disclosed in Japanese Patent Application No. 2 0 5 0 5 5 6 (see FIG. 7 of the same document). It is not done. Then, the source electrode 4 1 1 a and the drain electrode 4 1 1 b intrude into the substrate to form a substantially ohmic contact with the 5 drain layer 4 0 4 a. Similar to the embodiment, it is possible to exhibit the effect that the ion implantation step for forming the source region and the like is unnecessary.
- a Ni film is formed in a region where a source electrode and a drain electrode are to be formed on the substrate without performing the ion implantation step, and the Ni is diffused into the substrate by the heat treatment of the Ni film to form a nickel alloy film.
- Source electrode consisting of Form a source electrode.
- the present invention by applying the present invention to a lateral ACCUFET having a channel layer composed of multiple (five-doped layers), the ion implantation process for forming the source region and the drain region can be omitted.
- the fifth embodiment can reduce the manufacturing cost.
- FIG. 8 is a cross-sectional view showing a schematic structure of a Schottky diode which is a power semiconductor device according to a fifth embodiment.
- the SiC substrate 501 which is an n-type SiC substrate having an off surface as the main surface, as described in the first embodiment.
- the method is provided with multiple ⁇ -doped layers 504 (active region) formed by essentially the same method.
- Multiplex ⁇ 5 doped layer 504 the nitrogen concentration of about 5 X 1 0 15 atoms ⁇ c m_ 3 in a thickness of 40 eta m 3 single undoped layers 504 b (lightly doped layer), a peak concentration of nitrogen It is formed by alternately laminating three 5 doped layers 504 a (highly doped layers) each having 1 ⁇ 10 18 atoms ⁇ cm ⁇ 3 and a thickness of 1 O nm.
- the thickness of the SiC substrate 50 1 is about 100 m, and the SiC substrate 50 1 is not doped with impurities and is in a substantially semi-insulating state.
- Schottky electrodes 506 are provided not on the multiple S-doped layer 504 but on the side. That is, a trench is formed which digs in the multiple “5 doped layer 504 and reaches the SiC substrate 50 1, and on the side surface of this trench, multiple (5-doped layer 504 a of the 5-doped layer 504 and the undoped layer 5 04) A Schottky electrode 506 made of a Ni alloy is formed on each side of the b to make a Schottky contact with the Schottky alloy 506. Also, multiple ⁇ dosses are formed in a region separated from the Schottky electrode 506 by a certain distance.
- the layer 504 and the SiC substrate 50 1 are provided with an ohmic electrode 50 8 made of a Ni alloy film in contact with the substrate 501.
- the distance between the Schottky electrode 506 and the extraction doped layer 508 is about 10 / m. It is.
- the action of the Schottky diode of this embodiment is the same as that described in the description of the third embodiment in the specification of Japanese Patent Application No. 200 1-566 1 93, and multiple ⁇ double layers 50 4
- the overall resistance value can be kept small, and low power consumption and large current can be realized.
- the extraction doped layer (see FIG. 8 in the same document) provided in the Schottky diode described in Japanese Patent Application No. 2 0 0 1 5 6 It is unnecessary. That is, since the ion implantation step for forming the extraction doped layer is not necessary, the effect of reducing the manufacturing cost can be exhibited as in the first and second embodiments.
- the structure of the Schottky diode shown in FIG. 8 is formed by the following procedure. First, a semi-insulating SiC substrate 501 is placed in a crystallization apparatus, and the CVD described in the first embodiment is performed to obtain a thickness of about 400 nm on the Si substrate 501. By alternately epitaxially growing the n-type and p-type layers 504b and the five-doped layers 504a with a thickness of about 10 nm, multiple ⁇ -doped layers 54 are formed. Next, the multiple (5 doped layer 5 0 4 and the Si C substrate 5 0 1 are partially removed by dry etching to form a groove.
- the formation of the Ni film and the heat treatment cause multiple
- the ohmic electrode 5 0 8 made of N i alloy is formed on the ⁇ -doped layer 54 0.
- the Schottky electrode 5 0 6 made of Ni alloy is formed on the side wall of the groove.
- the formation method of the ceramic electrode 5 08 is as described in the first embodiment.
- FIG. 9 is a cross-sectional view showing a schematic structure of a power semiconductor device M E S F E T T according to a sixth embodiment.
- the first embodiment As shown in the figure, on the main surface of the S i C substrate 61 which is an n-type S i C substrate whose main surface is (0 0 0 1) off-plane, the first embodiment will be described.
- the method is provided with a multiple ⁇ -doped layer 64 (active region) formed by basically the same method as the method described above.
- the multiple ⁇ -doped layer 64 has a nitrogen concentration of approximately 5 ⁇ 10 15 atoms ⁇ cm ⁇ 3 and a thickness of 40 nm and three triple layers 64 b (lightly doped layer) and And three S-doped layers 6 0 4 a (high-concentration doped layers) with a peak concentration of nitrogen of 1 ⁇ 10 18 atoms ⁇ cm ⁇ 3 and a thickness of 1 O nm. It is formed.
- the thickness of the S i C substrate 601 is about 100 m, and the S i C substrate 6 0 1 is not doped with impurities and is approximately half. It is in an insulating state.
- a Ni alloy made of a Ni alloy in Schottky contact with the first layer 604 b on the uppermost undoped layer 604 b of the multiple 5 doped layer 64 is used.
- a source electrode 6 0 9 a and a drain electrode 6 0 9 b which are metallic electrodes made of Ni alloys facing each other with the gate electrode 6 0 8 being a gate electrode and the gate electrode 6 0 8 being interposed therebetween. And are provided.
- the gate length of the gate electrode 600 is about 1 ⁇ m.
- a quantum level is generated in the ⁇ 5 doped layer 6 0 4 a due to the quantum effect, and the wave function of electrons localized in the S doped layer 6 0 4 a is to some extent. It will be spread. As a result, a distribution state in which electrons are present in (not only the 5 doped layer 6 0 4 a but also in the single layer 6 0 4 b.
- the potential of the multiple ⁇ 5 doped layer 6 0 4 is
- the electrons are spread from the ⁇ -doped layer 6 0 4 a to the undoped layer 6 0 4 b by the quantum effect, the ⁇ 5 doped layer 6 0 4 a, and the 1 p layer 6 0 4 b are constantly Since the electrons flow through the low impurity concentration layer 6004 b, electrons are supplied, so that high electron mobility can be obtained by reducing impurity ion scattering.
- the withstand voltage is defined by the low impurity concentration undoped layer 604b, and the multiple ⁇ 5 doped layer is defined.
- a high withstand voltage value can be obtained for the entire device, so that multiple S The layers 6 0 4 Te M E S F E T odor that is configured to be take advantage a large current flows between the source and drain, and high channel mobility, it is possible to realize a high breakdown voltage simultaneously.
- each of the ⁇ 5 doped layers 604 of each of the ⁇ 5 doped layers 604 without forming a source region or a drain region by ion implantation. Since it can be done, a large current can be supplied while maintaining the manufacturing cost at a low price, and the value as a united device can be enhanced.
- the structure of MESFET shown in FIG. 9 is formed by the following procedure. First, a semi-insulating SiC substrate 601 is placed in a crystallizing apparatus, and the CVD described in the first embodiment is performed to form three undoped layers on the SiC substrate 601. By alternately epitaxially growing 0 4 b and two ⁇ -doped layers 6 0 4 a, multiple (5 doped layers 6 0 4 Form Next, an N i film is formed on the substrate. Then, heat treatment is performed under the conditions described in the first embodiment to form the source electrode 609 a and the drain electrode 609 b in contact with the multiple ⁇ 5 doped layer 604 and the SiC substrate 60 1.
- the source electrode 609 a and the drain electrode 609 b have an ohmic contact with each ⁇ 5 drain layer 604 a of the multiple S drain layer 604.
- a gate electrode 608 made of Ni alloy is formed on the substrate. After the formation of the gate electrode 608, the gate electrode 608 and the multiple (the topmost undoped layer 604b of the five-doped layer 604) are kept in Schottky contact with each other without performing the heat treatment as described above. Do.
- semiconductor devices integrated with active elements such as transistors and diodes disposed in each circuit of communication system equipment such as a base station and passive elements such as capacitors and inductors will be described.
- the semiconductor device of this embodiment can be disposed in each communication system equipment such as a base station disclosed in Japanese Patent Application No. 2001-350923, which is the invention of the present inventors.
- FIG. 10 shows a semiconductor device in which the Schottky diode, MESFET, MISFET, capacitor and inductor are integrated on the SiC substrate according to the seventh embodiment of the present invention.
- FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device).
- the SiC substrate 701 which is a 4H-SiC substrate
- a first lightly doped layer 75 containing a low concentration of n-type impurities (nitrogen) and a high concentration of n-type impurities (nitrogen).
- the first multiple (5 doped layer 71 2 (active region)) in which the S doped layer and the undoped layer are alternately stacked, and the second layer contains a low concentration P type impurity (aluminum).
- each lightly doped -An element isolation region 71 1 is formed by burying a silicon oxide film in the trench for partitioning the shield layers 7 15 and 7 16 into each element.
- Each of the lightly doped layers 7 15 and 7 16 may be an undoped layer.
- the thickness of the first multiple (5-doped layer 722) contains a high concentration of nitrogen (eg 1 ⁇ 10 18 atoms ⁇ cm ⁇ 3 )
- a high concentration of nitrogen eg 1 ⁇ 10 18 atoms ⁇ cm ⁇ 3
- Layers of two 5 doped layers 7 12 a of about 1 O nm and 2 layers of about 40 nm of 1 H consisting of a single 4 H-Si c single crystal are alternately stacked.
- the second multiple layer contains aluminum of high concentration (eg 1 x 10 atoms ⁇ cm- 3 ) and has a thickness of about 1 O nm
- Two p-type doped layers (5-doped layer 7 13 a, and 2 and 1 layer 7 13 b of about 40 nm thick consisting of a single 4 H—Si c single crystal)
- the ⁇ -doped layers 7 12 a and the p-type doped layers 7 13 a are both alternately laminated, and both have a quantum effect to the carriers to the undoped layers 7 12 b and 7 13 b. It is formed thin enough to allow penetration.
- the semiconductor device of the present embodiment is a stacked portion in which the ⁇ -doped layers 7 12 a and 7 13 a and the undoped layers 7 12 b and 7 13 b are alternately stacked (multiple (5 (5).
- the structure formed by alternately laminating such a highly doped layer ( ⁇ 5 doped layer) and a lightly doped layer (doped layer) is described in the patent application, as will be described later. It is obtained by using a crystal growth apparatus and a crystal growth method disclosed in the specification and drawings of the patent application No. 2000-0 5964 and the patent application No. 2000-06010.
- the dopant gas supply used (referred to as “pulsed gas”) and the supply of the source gas are performed simultaneously, and the epitaxial growth method by in-situ doping is used.
- a Schottky diode 7 20 rectifying element
- an MESFET 7 3 0 Power amplifier the second multiple (5 doped layer 7 1 3 on the top of the Si C substrate 7 0 1) is provided with an n MISFET 7 40 (switching element).
- a capacitor 750, and an inductor 760 induction element, that is, the MESFET, diode, capacitor, and inductor that make up the main amplifier that handles high frequency signals in the communication circuit.
- a MISFET disposed in a signal processing unit or the like is provided in one S i C substrate 70 1.
- the Schottky diode 7 20 comprises a Schottky electrode 72 1 made of a nickel (N i) alloy in Schottky contact with the first multiplex 5 doped layer 72 1, and a first multiplex ⁇ diode It has a ceramic electrode 723 made of a nickel (Ni) alloy in which an atomic contact is made to the (5 dope layer 7 12 a of the layer 7 1 2).
- the MESFET 730 described above comprises a Schottky electrode 732 made of a Ni alloy film in Schottky contact with the undoped layer 712a which is the uppermost layer of the first multiple ⁇ 5 doped layer 722. And the first multiple ⁇ 5 doped layers 71 2 provided on the regions located on both sides of the gate electrode 73 2 and each of the first multiple (5 doped layers 7 12 5 doped layers) A source electrode 734 and a drain electrode 735 in ohmic contact with the electrode 712 a are provided.
- the above-mentioned ⁇ ⁇ ISFET film 40 is formed of a gate insulating film 7 4 1 made of Si O z formed on a second multiple (5 double layer 7 13) and a gate insulating film 7 4 1
- a gate electrode 7 42 consisting of a Ni alloy film formed on the top, and a Ni alloy film having an ohmic contact with each of the second multiple ⁇ 5 doped layers 7 13 3 p-type doped layers 7 13 a Source electrode 7 44 and drain electrode 7 45.
- an insulating gate electrode, a source / drain electrode, etc. are formed in a region in the first multiple (5 doped layer 72). It goes without saying that the p MISFET can be provided.
- the capacitor 750 is provided on the underlying insulating film 751 formed of a SiON film provided on the second multiple ⁇ 5 doped layer 713, and on the underlying insulating film 751.
- a lower electrode 7 52 made of a platinum (P t) film, a capacitive insulating film 7 53 made of a high dielectric film such as BST provided on the lower electrode 75 2, and a lower portion sandwiching the capacitive insulating film 7 53
- an upper electrode 754 consisting of a platinum (P t) film facing the electrode 7 5 2.
- the inductor 760 has a dielectric film 761 formed of a SiON film provided on the second multiple 5-doped layer 713, and a spiral shape formed on the dielectric film 761.
- the conductor film 762 made of Cu film.
- the width of the conductor film 762 is about 9 /
- the thickness is about 4 m
- the gap between the conductor films 76 2 is about 4 m.
- the Si C substrate 70 1 has high heat resistance and high thermal conductivity.
- the conductor film 722 can be miniaturized, and a finer pattern, for example, a shape with a width of 1 to 2 m and a gap of about 1 to 2 m is also possible.
- an interlayer insulating film 7 made of a silicon oxide film is formed on the substrate, and an interconnection made of an aluminum alloy film, a Cu alloy film, etc. is formed on the interlayer insulating film 770 (see FIG. Not shown) is provided.
- the conductor part of each of the elements 7 2 0 0, 7 3 0, 7 4 0, 7 5 0, 7 6 0 is made of an aluminum alloy film or the like which fills the contact hole formed in the interlayer insulating film 7 7 0 It is connected to the wiring through contacts 7 7 1, and each circuit in communication system equipment such as base station is configured.
- each circuit in the communication system equipment can be miniaturized, and the total thickness is only the sum of the thickness of the SiC substrate and the thickness of the laminated film and the interlayer insulating film.
- the entire communication system equipment has an extremely thin structure. That is, the size of the communication system equipment can be reduced.
- the Schottky diode has a horizontal structure, and MESFET, Schottky diode, MISFET, etc. can be provided on one SiC substrate, facilitating integration. became.
- passive elements such as inductors and capacitors can be mounted on a common SiC substrate.
- the doped layer formed by ion implantation into the SiC layer is not provided as much as possible as a whole of the semiconductor integrated circuit device, the ion implantation step into the SiC layer, which requires a great deal of labor, is especially required. This can be omitted and the manufacturing cost can be reduced.
- the MESFET or Schottky diode formed on the SiC substrate is positive. Since the temperature at which normal operation can be secured is around 400 ° C., the severe upper temperature limit of 150 ° C. is assumed, as in the case of a FET provided on a conventional Si substrate. The various constraints imposed by That is, in the present embodiment, since the heat resistance of the MESFET and Schottky diode on the SiC substrate is high, even if all elements are arranged close to each other, almost no failure due to the heat resistance occurs.
- the circuit can be downsized significantly, the degree of freedom of placement in the base station can be secured high, and since the SiC substrate has high thermal conductivity and good heat dissipation, the circuit It is possible to easily avoid that each element in the unit is adversely affected by the heat dissipation of the component amplifier.
- the dielectric film 6 1 of the inductor 60 is formed by a BCB film (benzocyclobutene film).
- the BCB film is a film containing BCB in the structure obtained by dissolving and coating BCB-DVS monomer in a solvent and then baking it.
- the BCB film is characterized in that the relative dielectric constant is as small as about 2.7, and a thick film of about 30 ⁇ m can be easily formed by one application.
- the tan 6 of the B CB film is about one hundredth smaller than that of SiO 2 at about 60 GH z, which makes the BCB film excellent as a dielectric film constituting an inductor and a microstrip line. It can exhibit the characteristics.
- FIGS. 11 (a) to (c) are cross-sectional views showing the steps from the formation of the first and second laminated portions to the formation of the element isolation region in the manufacturing steps of the semiconductor device of this embodiment. is there.
- FIGS. 12 (a) and 12 (b) are cross-sectional views showing the steps from the formation of an insulating film to the formation of an electrode or a conductor film of each element in the manufacturing steps of the semiconductor device of this embodiment.
- Figures 13 (a) and (b) are cross-sectional views showing the steps from the formation of the upper electrode of the capacitor to the formation of the contact hole in the conductor of each element in the process of manufacturing the semiconductor device of this embodiment. is there.
- the crystal growth apparatus and the crystal growth method in the present embodiment are based on the structure or method disclosed in the specification and drawings of patent application 2000-58964 or patent application 2000-06210. .
- a p-type SiC substrate 701 is prepared.
- a 4H-SiC substrate having an orientation whose main surface matches the ⁇ 1 1-20 0 ⁇ plane (eight planes) is used as the SiC substrate 70 1.
- the SiC substrate 700 is thermally oxidized at 1100 ° C. for 3 hours, and the surface has a thickness of about 40 nm.
- hydrogen gas of flow rate 2 (I min) and argon gas of flow rate 1 (I in) are supplied as dilution gas (carrier gas) into the chamber 1, and the pressure in the chamber 1 is set at 0.903 3 MP a As the substrate temperature The degree is controlled to about 16000C.
- propane gas with a flow rate of 2 (m I / min) as a source gas and silane gas with a flow rate of 3 (m I / min) To introduce.
- the source gas is diluted with hydrogen gas at a flow rate of 50 (m IZ min).
- the first lightly doped layer 15 having a thickness of about 120 nm is formed by epitaxial growth.
- nitrogen is contained in the high pressure cylinder as the doping gas, and a pulse valve is provided between the high pressure cylinder and the doping gas supply piping.
- the doping gas can be supplied in a pulse shape directly on the SiC substrate 70 1 in the chamber.
- a single layer may be formed instead of the first lightly doped layer 75.
- a ⁇ -doped layer 71 2 a (highly doped layer) having a thickness of about 10 nm is formed on the first lightly doped layer 7 15 by epitaxial growth.
- the pulse valve opening period (pulse width) is shortened, and when forming the 5 doped layer 7 12 a, the pulse valve is opened.
- the difference in impurity concentration can be easily realized by lengthening the period (pulse width).
- the pulse valve is opened and closed at the same time, and the doping gas is introduced to form the 5-doped layer 72a, and only the source gas is supplied without supplying the doping gas.
- the first multiplex formed by alternately laminating (5 doped layers 7 12 a and undoped layers 7 12 b) ⁇ 5 Form a doped layer 7 1 2.
- an undoped layer 7 12 b is formed, and the thickness thereof is made about 10 nm thicker than the other and single layers 7 1 2 b.
- the average nitrogen concentration in the first multiple ⁇ doped layer 72 is about 1 ⁇ 10 “atoms cm ⁇ 3 , and the total thickness of the first multiple ⁇ doped layer 72 is about It is 190 nm.
- the first multiple (5-doped layer 72) is formed.
- a lightly doped layer 716 having a thickness of about 120 nm is formed, where, as a doping gas, for example, a dimethyl gas (a hydrogen gas containing about 10% of AI 2 (CH 2) is used.
- a doping gas for example, a dimethyl gas (a hydrogen gas containing about 10% of AI 2 (CH 2) is used.
- the source gas is supplied, and at the same time the pulse valve is opened and closed to obtain a doping gas (a hydrogen gas containing trimethylaluminum).
- a doping gas a hydrogen gas containing trimethylaluminum.
- an undoped layer 7 13 b is formed on the uppermost layer, and the thickness thereof is made about 10 nm thicker than the other undoped layers 7 13 b.
- the average aluminum concentration in the second multiple 5 doped layer 7 13 is approximately 1 ⁇ 10 17 atoms S ⁇ cm ⁇ 3 , and the second multiple 5 doped layer 7 1 3 after thermal oxidation
- the thickness of the tall is about 190 nm.
- the selective etching is performed to form the second multiple ⁇ -doped layer 7 13 and the second lightly doped layer 16 among the short-cut ones.
- the area to form a single diode 7 20 and the area to form a short hole 7 3 0 is removed, and the area to form a Schottky diode 7 20 and a MESFET 7 3 0 is formed. Expose the heavily doped ⁇ 712 layer.
- a trench for forming an element isolation region is formed on the substrate, and a silicon oxide film is embedded in the trench to form an element isolation region 7 11.
- a Si N film having a thickness of about 0.4 ⁇ m is formed by the plasma CVD method, and then the Si i An N film is patterned to form an underlying insulating film 7 5 1 and a dielectric film 7 on a region to form a capacitor 7 50 and an inductor 7 6 0 in the second multiple ⁇ -doped layer 7 13.
- a gate insulating film 7 4 1 made of a thermal oxide film of about 20 nm in thickness is formed.
- the portion to form the source electrode and the drain electrode is removed to form an opening, and the opening is provided with the source electrode 74 4 and the drain electrode 7 4 5 by vacuum evaporation.
- an ohmic electrode 7 is also formed on the first multiple layer ⁇ 5 doped layer 7 12 of the Schottky diode 720.
- a nickel (Ni) alloy film is vapor-deposited on the gate insulating film 741 to form a gate electrode 742 having a gate length of about 1 ⁇ m made of a nickel alloy film.
- nickel (N i) is vapor-deposited on the region where the first multiple ⁇ -doped layer 72 12 is formed to form a Schottky diode 720 and a MESFET 730 to form nickel.
- the lower electrode made of platinum is formed by depositing platinum (P t) on the underlying insulating film 751 of the capacitor 750 while forming the contact electrode 721 and the Schottky gate electrode 722.
- a resist film having a spiral opening is formed in a region where an inductor 760 is to be formed, a Cu film having a thickness of about 4 m is deposited thereon, and liftoff is performed.
- the spiral conductive film 7 62 is left on the dielectric film 7 6 1.
- the conductor film may be made of an aluminum alloy film instead of the Cu film. . In that case, after depositing an aluminum alloy film, the aluminum alloy film is patterned by R ⁇ ⁇ ⁇ ⁇ E dry etching using CI gas and BCI gas to form a spiral conductor film 762.
- a platinum (P t) film is formed on the BST film by evaporation. Form. Then, the platinum film and the BST film are patterned into a predetermined shape to form an upper electrode 754 and a capacitive insulating film 753.
- an interlayer insulating film 730 consisting of a silicon oxide film is deposited on the substrate, and a Schottky diode 720 is exposed to the interlayer insulating film 730.
- Contact hole 774 is formed.
- one Schottky diode, ME SFET, MISFET, resistance element, inductor, etc. can be easily removed while performing the ion implantation step into the SiC layer as little as possible. It can be installed on a SiC substrate.
- MESFETs, Schottky diodes, and other active devices have a vertical structure, and MESFETs and Schottky diodes can be provided in a common SiC substrate, so integration is possible. It became easier.
- passive elements such as inductors to be mounted on a common SiC substrate, further miniaturization can be achieved.
- a heavily doped layer of multiple ⁇ -doped layers consisting of S i C In addition to Ni films, electrodes that diffuse into glass and form ohmic contact were formed from Ni films, but in addition to Ti films, Ti films, W films, Ti W films, Ti N films, AI films, AIN films , T i AI film etc. can be used. Note that for complete ohmic contact, multiple (if the 5 doped layer is n-type layer, N i film, T i, T i film, W film, T i W film, T film as an electrode) It is preferable to use an i N film, etc.
- an AI film, an AIN i film, a Ti AI film or the like as an electrode when multiple (5-doped layer is a p-type layer). Even if it is not an ohmic contact, low resistance may be obtained in practice, so it is not limited to the above combinations.
- nickel diffuses from the Ni film to form a nickel silicide layer, but when the source electrode is formed of another material, for example, a gold film, titanium is not preferable. It is thought that titanium carbide is formed by diffusion into the SiC layer. By diffusion of metal in the SiC layer, it is thought that some alloy or mixture is formed, but practically, it has the property that metal diffuses in multiple S-doped layers, and low resistance Any metal film may be used as long as it is a material that can obtain a positive electrode.
- the active element is used which operates using the SiC substrate as the substrate and with the SiC layer acting as the active layer.
- the present invention is not limited to the semiconductor device provided on the SiC substrate.
- all semiconductor devices provided on a compound semiconductor substrate made of Ga N, I P P etc. The active layer is made of Ga N, AIG a N, I n G a N, I n AIG a N, etc.
- the active layer is made of Ga N, AIG a N, I n G a N, I n AIG a N, etc.
- an AuGe film or the like can be used as a conductor film for an electrode.
- a TiZPtZAu laminated film, an Au u ⁇ / ⁇ laminated film, etc. can be used as a conductor film for an electrode.
- the channel mobility is improved and the breakdown voltage is provided by providing a laminated portion in which the ⁇ 5 doped layer and the lightly doped layer (including the doped layer) are laminated below the gate insulating film.
- the source / drain region and the doped layer for In each of the above embodiments, the number of the multiple (the heavily doped layer doped layer in the five doped layers) may be at least two in the above embodiments. At least one lightly doped layer should be provided.
- the active region formed as a multilayer (five drain layers) and the surface of the active region may penetrate into the active region and at least (at least in five drain layers). Since the electrodes in contact are provided, it is possible to use a compound semiconductor to reduce the manufacturing cost of semiconductor devices with high performance such as high power and high withstand voltage.
- the semiconductor device of the present invention can be used particularly for a power device for high power, a MOSFET, a Schottky diode, an inductor, etc. in a high frequency device.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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EP03764156A EP1450394B1 (en) | 2002-07-11 | 2003-07-09 | Semiconductor device and method for manufacturing same |
DE60325690T DE60325690D1 (de) | 2002-07-11 | 2003-07-09 | Halbleiterbauelement und verfahren zu seiner herstellung |
US10/494,705 US7507999B2 (en) | 2002-07-11 | 2003-07-09 | Semiconductor device and method for manufacturing same |
Applications Claiming Priority (4)
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JP2002202527 | 2002-07-11 | ||
JP2002-202527 | 2002-07-11 | ||
JP2003021692A JP4463482B2 (ja) | 2002-07-11 | 2003-01-30 | Misfet及びその製造方法 |
JP2003-021692 | 2003-01-30 |
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WO2004008512A1 true WO2004008512A1 (ja) | 2004-01-22 |
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PCT/JP2003/008736 WO2004008512A1 (ja) | 2002-07-11 | 2003-07-09 | 半導体装置及びその製造方法 |
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US (1) | US7507999B2 (ja) |
EP (2) | EP1968104A3 (ja) |
JP (1) | JP4463482B2 (ja) |
CN (1) | CN100353498C (ja) |
DE (1) | DE60325690D1 (ja) |
WO (1) | WO2004008512A1 (ja) |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US7473929B2 (en) * | 2003-07-02 | 2009-01-06 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
US7846828B2 (en) | 2003-07-02 | 2010-12-07 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
WO2005104232A1 (en) * | 2004-04-27 | 2005-11-03 | Koninklijke Philips Electronics N.V., | Semiconductor device and method of manufacturing such a device |
US8084829B2 (en) | 2004-04-27 | 2011-12-27 | Nxp B.V. | Semiconductors device and method of manufacturing such a device |
KR101205115B1 (ko) | 2004-04-27 | 2012-11-26 | 엔엑스피 비 브이 | 반도체 디바이스 및 그 제조 방법 |
US9048196B2 (en) * | 2004-09-13 | 2015-06-02 | International Rectifier Corporation | Power semiconductor package |
US9620471B2 (en) | 2004-09-13 | 2017-04-11 | Infineon Technologies Americas Corp. | Power semiconductor package with conductive clips |
WO2011027525A1 (ja) * | 2009-09-02 | 2011-03-10 | パナソニック株式会社 | 半導体素子およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20050173739A1 (en) | 2005-08-11 |
EP1450394B1 (en) | 2009-01-07 |
DE60325690D1 (de) | 2009-02-26 |
CN100353498C (zh) | 2007-12-05 |
EP1968104A2 (en) | 2008-09-10 |
EP1968104A3 (en) | 2008-11-05 |
CN1592950A (zh) | 2005-03-09 |
EP1450394A4 (en) | 2005-03-16 |
US7507999B2 (en) | 2009-03-24 |
EP1450394A1 (en) | 2004-08-25 |
JP4463482B2 (ja) | 2010-05-19 |
JP2004096061A (ja) | 2004-03-25 |
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