CN107331603B - 一种碳化硅mosfet单胞结构的制造方法 - Google Patents

一种碳化硅mosfet单胞结构的制造方法 Download PDF

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CN107331603B
CN107331603B CN201710541462.8A CN201710541462A CN107331603B CN 107331603 B CN107331603 B CN 107331603B CN 201710541462 A CN201710541462 A CN 201710541462A CN 107331603 B CN107331603 B CN 107331603B
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silicon carbide
ion implantation
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CN107331603A (zh
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黄润华
柏松
陶永洪
汪玲
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CETC 55 Research Institute
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Abstract

本发明公开了一种碳化硅MOSFET单胞结构的制造方法，将垂直导电沟道区设计成弯曲状，这样能够有效增大垂直导电沟道区的总长度，从而降低沟道电阻在导通电阻中所占的比例。

Description

一种碳化硅MOSFET单胞结构的制造方法
技术领域
本发明涉及半导体器件领域，特别是涉及一种碳化硅MOSFET单胞结构的制造方法。
背景技术
SiC材料禁带宽度大、击穿电场高、饱和漂移速度和热导率大，这些材料优越性能使其成为制作高功率、高频、耐高温、抗辐射器件的理想材料。碳化硅MOSFET器件具有击穿电压高、电流密度大、驱动电路与硅IGBT近似的一系列优点，因此发展前景非常广泛。同时碳化硅是唯一可以通过自身氧化实现高质量栅氧化层的宽禁带半导体材料，但目前碳化硅热氧化技术尚不成熟，形成的沟道迁移率非常低，进而导致沟道电阻在电流流通路径上所占电阻比例非常大，这严重制约了器件的导通性能提高。
发明内容
发明目的：本发明的目的是提供一种能够有效降低沟道电阻在导通电阻中所占比例的碳化硅MOSFET单胞结构的制造方法。
技术方案：本发明所述的碳化硅MOSFET单胞结构的制造方法，包括以下步骤：
S1：在碳化硅外延层表面制作离子注入掩膜，去除PWELL掺杂区的离子注入掩膜，保留垂直导电沟道区的离子注入掩膜，垂直导电沟道区为弯曲状；
S2：对全片进行第一类型离子注入，形成PWELL注入区；所述第一类型离子为P型离子；
S3：制作N区注入掩膜：在碳化硅外延层表面制作离子注入掩膜，去除N掺杂区的离子注入掩膜；
S4：对全片进行第二类型离子注入，形成N注入区，沟道区分为第一沟道区、第二沟道区和第三沟道区，并且沟道长度依次降低；所述第二类型离子为N型离子；第一沟道区沟道长度需要保证足够以抵抗阻断电压，由于相邻第一沟道区的夹断作用，第二沟道区和第三沟道区可采用短沟道，并且能够保证器件具有足够的阻断性能。
S5：制作N+区注入掩膜：在碳化硅外延层表面制作离子注入掩膜，去除N+掺杂区的离子注入掩膜；
S6：对全片进行第二类型离子注入，形成N+注入区；
S7：制作P+区注入掩膜：在碳化硅外延层表面制作离子注入掩膜，去除P+掺杂区的离子注入掩膜；
S8：对全片进行第一类型离子注入；
S9：通过高温激活退火完成注入杂质激活；
S10：去除欧姆接触区栅介质；
S11：制作欧姆接触金属层；
S12：退火同时形成P型和N型欧姆接触；
S13：在栅电极区制作栅电极，覆盖全部沟道区；
S14：进行栅源隔离和金属加厚。
进一步，在相邻第一沟道区之间加入第四沟道区，这样能够增强单胞结构的阻断能力。
进一步，所述P+掺杂区包括多个菱形的P+掺杂单元，所有P+掺杂单元排列成一条直线，且相邻两个P+掺杂单元通过顶点相连。这样可以有效降低电流路径，从而降低导通电阻。并且，由于相邻两个P+掺杂单元之间不存在距离，P+掺杂区边缘与欧姆接触区边缘之间也不存在距离，因此降低了加工的难度。
进一步，所述第一沟道区的长度为0.5um～1.5um。
进一步，所述第二沟道区的长度为0.2um～1.5um。
进一步，所述第三沟道区的长度为0.1um～1.5um。
进一步，所述第四沟道区的长度为0.1um～1.5um。
进一步，所述N注入区掺杂浓度为1e16～5E19cm-2，N+注入区掺杂浓度为1e18～1E21cm-2。
有益效果：本发明公开了一种碳化硅MOSFET单胞结构的制造方法，将垂直导电沟道区设计成弯曲状，这样能够有效增大垂直导电沟道区的总长度，同时能够采用短沟道而不必担心短沟道穿通导致的器件过早击穿，从而降低沟道电阻。
附图说明
图1为本发明具体实施方式的PWELL离子注入示意图；
图2为本发明具体实施方式的N离子注入示意图；
图3为本发明具体实施方式的N+离子注入示意图；
图4为本发明具体实施方式的P+离子注入示意图；
图5为本发明具体实施方式的欧姆接触示意图；
图6为本发明具体实施方式的沟道分解示意图；
图7为本发明具体实施方式的增加了第四沟道区的结构示意图；
图8为现有技术中的方形P+区示意图；
图9为本发明具体实施方式的菱形P+区示意图。
具体实施方式
S1：如图1所示，在碳化硅外延层表面制作离子注入掩膜，去除PWELL掺杂区1的离子注入掩膜，保留垂直导电沟道区的离子注入掩膜，垂直导电沟道区为如图1所示的弯曲状；
S2：对全片进行第一类型离子注入，形成PWELL区，第一类型离子为P型离子；
S3：如图2所示，在碳化硅外延层表面制作离子注入掩膜，去除N掺杂区2的离子注入掩膜；
S4：对全片进行第二类型离子注入，形成N注入区，沟道区分为第一沟道区6、第二沟道区7和第三沟道区8，并且沟道长度依次降低；第二类型离子为N型离子；
S5：如图3所示，在碳化硅外延层表面制作离子注入掩膜，去除N+掺杂区3的离子注入掩膜；
S6：对全片进行第二类型离子注入，形成N+注入区；
S7：如图4所示，在碳化硅外延层表面制作离子注入掩膜，去除P+掺杂区4的离子注入掩膜；
S8：对全片进行第一类型离子注入；
S9：通过高温激活退火完成注入杂质激活；
S10：如图5所示，制作栅介质，并去除N型欧姆接触区5和P型欧姆接触区4介质的栅介质；
S11：在N型欧姆接触区5和P型欧姆接触区4上制作金属层；
S12：退火同时形成金属层和N型欧姆接触区5和P型欧姆接触区4之间的P型和N型欧姆接触；
S13：在栅电极区制作栅电极，覆盖全部沟道区；
S14：进行栅源隔离和金属加厚。
其中，“P+掺杂区”就是“P型欧姆接触区”。
现有技术中的P+掺杂区4如图8所示，P+掺杂区4包括多个正方形的P+掺杂单元，且相邻两个P+掺杂单元之间存在一定距离，P+掺杂单元的上边缘与N型欧姆接触区5的上边缘之间、P+掺杂单元的下边缘与N型欧姆接触区5的下边缘之间均存在一定距离。并且，如图8所示，电流沿着正方形的相邻两条边流动，电流路径较长，导通电阻较大。同时N型欧姆接触区5的宽度要大于P+掺杂区4的宽度，并且考虑到电流的流通和光刻误差，宽度的差值要保证足够大。
为了解决现有技术中的问题，本具体实施方式的P+掺杂区4如图9所示，包括多个菱形的P+掺杂单元，所有P+掺杂单元排列成一条直线，且相邻两个P+掺杂单元通过顶点相连。如图9所示，电流沿着菱形的一条边流动，这样可以有效减少电流路径，从而降低导通电阻。并且，由于相邻两个P+掺杂单元之间不存在距离，P+掺杂区4边缘与N型欧姆接触区5边缘之间也不存在距离，因此降低了加工的难度。不会造成如图8所示结构工艺误差造成的电流横向通路电阻变化。
如图4、图5、图6和图7所示，P+掺杂区4包括多个菱形的P+掺杂单元，所有P+掺杂单元排列成一条直线，且相邻两个P+掺杂单元通过顶点相连。这样可以有效降低电流路径，从而降低导通电阻。并且，由于不需要保留N+区域沿着水平方向的电流路径，欧姆接触区与P+掺杂区4之间不需要保留足够的冗余。
此外，在相邻第一沟道区6之间还可以加入第四沟道区9，如图7所示，以增强器件阻断能力。

Claims (8)

1.一种碳化硅MOSFET单胞结构的制造方法，其特征在于：包括以下步骤：
S1：在碳化硅外延层表面制作离子注入掩膜，去除PWELL掺杂区的离子注入掩膜，保留垂直导电沟道区的离子注入掩膜，垂直导电沟道区为弯曲状；
S2：对全片进行第一类型离子注入，形成PWELL注入区；所述第一类型离子为P型离子；
S3：制作N区注入掩膜：在碳化硅外延层表面制作离子注入掩膜，去除N掺杂区的离子注入掩膜；
S4：对全片进行第二类型离子注入，形成N注入区，沟道区分为第一沟道区、第二沟道区和第三沟道区，并且沟道长度依次降低；所述第二类型离子为N型离子；
S5：制作N+区注入掩膜：在碳化硅外延层表面制作离子注入掩膜，去除N+掺杂区的离子注入掩膜；
S6：对全片进行第二类型离子注入，形成N+注入区；
S7：制作P+区注入掩膜：在碳化硅外延层表面制作离子注入掩膜，去除P+掺杂区的离子注入掩膜；
S8：对全片进行第一类型离子注入；
S9：通过高温激活退火完成注入杂质激活；
S10：去除欧姆接触区栅介质；
S11：制作欧姆接触金属层；
S12：退火同时形成P型和N型欧姆接触；
S13：在栅电极区制作栅电极，覆盖全部沟道区；
S14：进行栅源隔离和金属加厚。
2.根据权利要求1所述的碳化硅MOSFET单胞结构的制造方法，其特征在于：在相邻第一沟道区之间加入第四沟道区。
3.根据权利要求1所述的碳化硅MOSFET单胞结构的制造方法，其特征在于：所述P+掺杂区包括多个菱形的P+掺杂单元，所有P+掺杂单元排列成一条直线，且相邻两个P+掺杂单元通过顶点相连。
4.根据权利要求1所述的碳化硅MOSFET单胞结构的制造方法，其特征在于：所述第一沟道区的长度为0.5um～1.5um。
5.根据权利要求1所述的碳化硅MOSFET单胞结构的制造方法，其特征在于：所述第二沟道区的长度为0.2um～1.5um。
6.根据权利要求1所述的碳化硅MOSFET单胞结构的制造方法，其特征在于：所述第三沟道区的长度为0.1um～1.5um。
7.根据权利要求2所述的碳化硅MOSFET单胞结构的制造方法，其特征在于：所述第四沟道区的长度为0.1um～1.5um。
8.根据权利要求1所述的碳化硅MOSFET单胞结构的制造方法，其特征在于：所述N注入区掺杂浓度为1e16～5E19cm-2，N+注入区掺杂浓度为1e18～1E21cm-2。
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