WO2003015248A3 - Dispositifs de suppression de tension transitoire bidirectionnels a penetration a faible tension dotes d'une protection contre le claquage de surface et leurs procedes de production - Google Patents

Dispositifs de suppression de tension transitoire bidirectionnels a penetration a faible tension dotes d'une protection contre le claquage de surface et leurs procedes de production Download PDF

Info

Publication number
WO2003015248A3
WO2003015248A3 PCT/US2002/021953 US0221953W WO03015248A3 WO 2003015248 A3 WO2003015248 A3 WO 2003015248A3 US 0221953 W US0221953 W US 0221953W WO 03015248 A3 WO03015248 A3 WO 03015248A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
type conductivity
junctions
mesa trench
semiconductor layer
Prior art date
Application number
PCT/US2002/021953
Other languages
English (en)
Other versions
WO2003015248A2 (fr
Inventor
Willem G Einthoven
Anthony Ginty
Aidan Walsh
Original Assignee
Gen Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Semiconductor Inc filed Critical Gen Semiconductor Inc
Priority to EP02794642A priority Critical patent/EP1405347A4/fr
Priority to KR1020047000359A priority patent/KR100957796B1/ko
Priority to JP2003520054A priority patent/JP4358622B2/ja
Priority to AU2002355597A priority patent/AU2002355597A1/en
Publication of WO2003015248A2 publication Critical patent/WO2003015248A2/fr
Publication of WO2003015248A3 publication Critical patent/WO2003015248A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66121—Multilayer diodes, e.g. PNPN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8618—Diodes with bulk potential barrier, e.g. Camel diodes, Planar Doped Barrier diodes, Graded bandgap diodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/912—Displacing pn junction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/965—Shaped junction formation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un dispositif de suppression de tension transitoire bidirectionnel. Ledit dispositif comprend : (a) une couche inférieure de semi-conducteur présentant une conductivité de type p ; (b) une couche supérieure de semi-conducteur présentant une conductivité de type p ; (c) une couche médiane de semi-conducteur présentant une conductivité de type n adjacente aux couches inférieures et supérieures et disposée entre ces dernières de sorte que des jonctions p-n supérieures et inférieures soient formées ; (d) une tranchée mesa s'étendant dans la couche supérieure, dans la couche médiane et dans au moins une partie de la couche inférieure, de sorte que la tranchée mesa définisse une zone active pour le dispositif ; et (e) une couche d'oxyde recouvrant au moins des parties des parois de ladite tranchée mesa qui correspondent aux jonctions supérieures et inférieures, de sorte que la distance entre les jonctions supérieures et inférieures soit augmentée sur les parois. L'intégrale de la concentration de dopage nette de la couche médiane dudit dispositif, lorsqu'elle est prise sur la distance entre les jonctions, est telle que le claquage, lorsqu'il se produit est un claquage destructif plutôt qu'un claquage par avalanche. L'invention concerne en outre un procédé de production dudit dispositif consistant à : (a) mettre à disposition un substrat semi-conducteur de type p ; (b) déposer de manière épitaxiale une couche inférieure de semi-conducteur présentant une conductivité de type p ; (c) déposer de manière épitaxiale une couche médiane de semi-conducteur présentant une conductivité n sur ladite couche inférieure ; (d) déposer de manière épitaxiale une couche supérieure à semi-conducteur présentant une conductivité de type p sur la couche médiane ; (e) chauffer le substrat, la couche inférieure épitaxiale, la couche épitaxiale médiane et la couche épitaxiale supérieure ; (f) attaquer la tranchée mesa qui s'étend dans la couche supérieure, la couche médiane, et au moins dans une partie de la couche inférieure de telle sorte que la tranchée mesa définisse une zone active pour le dispositif ; et (g) faire accroître de façon thermique une couche d'oxyde sur au moins une desdites parties des parois de ladite tranchée mesa qui correspondent aux jonctions supérieures et inférieures dudit dispositif.
PCT/US2002/021953 2001-07-11 2002-07-11 Dispositifs de suppression de tension transitoire bidirectionnels a penetration a faible tension dotes d'une protection contre le claquage de surface et leurs procedes de production WO2003015248A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP02794642A EP1405347A4 (fr) 2001-07-11 2002-07-11 Dispositifs de suppression de tension transitoire bidirectionnels a penetration a faible tension dotes d'une protection contre le claquage de surface et leurs procedes de production
KR1020047000359A KR100957796B1 (ko) 2001-07-11 2002-07-11 표면 브레이크다운 보호 기능을 갖는 저전압 펀치스루양방향 과도 전압 억압 디바이스 및 이를 제조하는 방법
JP2003520054A JP4358622B2 (ja) 2001-07-11 2002-07-11 低電圧パンチスルー双方向過渡電圧抑制素子及びその製造方法
AU2002355597A AU2002355597A1 (en) 2001-07-11 2002-07-11 Low-voltage punch-through bi-directional transient-voltage suppression devices having surface breakdown protection and methods of making the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/903,107 US6600204B2 (en) 2001-07-11 2001-07-11 Low-voltage punch-through bi-directional transient-voltage suppression devices having surface breakdown protection and methods of making the same
US09/903,107 2001-07-11

Publications (2)

Publication Number Publication Date
WO2003015248A2 WO2003015248A2 (fr) 2003-02-20
WO2003015248A3 true WO2003015248A3 (fr) 2003-05-30

Family

ID=25416947

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/021953 WO2003015248A2 (fr) 2001-07-11 2002-07-11 Dispositifs de suppression de tension transitoire bidirectionnels a penetration a faible tension dotes d'une protection contre le claquage de surface et leurs procedes de production

Country Status (8)

Country Link
US (2) US6600204B2 (fr)
EP (1) EP1405347A4 (fr)
JP (1) JP4358622B2 (fr)
KR (1) KR100957796B1 (fr)
CN (1) CN100416836C (fr)
AU (1) AU2002355597A1 (fr)
TW (1) TWI257697B (fr)
WO (1) WO2003015248A2 (fr)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6781161B1 (en) * 2003-04-09 2004-08-24 Teccor Electronics, Lp Non-gated thyristor device
WO2006048732A1 (fr) * 2004-11-02 2006-05-11 Nissan Motor Co., Ltd. Element d'accumulateur bipolaire et ensemble accumulateur pour vehicules
US7244970B2 (en) * 2004-12-22 2007-07-17 Tyco Electronics Corporation Low capacitance two-terminal barrier controlled TVS diodes
US20060220168A1 (en) * 2005-03-08 2006-10-05 Monolithic Power Systems, Inc. Shielding high voltage integrated circuits
EP1866970A1 (fr) * 2005-03-22 2007-12-19 University College Cork-National University of Ireland, Cork Structure de diode
US20060216913A1 (en) * 2005-03-25 2006-09-28 Pu-Ju Kung Asymmetric bidirectional transient voltage suppressor and method of forming same
US20070077738A1 (en) * 2005-10-03 2007-04-05 Aram Tanielian Fabrication of small scale matched bi-polar TVS devices having reduced parasitic losses
US7596718B2 (en) * 2006-05-07 2009-09-29 Applied Materials, Inc. Ranged fault signatures for fault diagnosis
US7587296B2 (en) * 2006-05-07 2009-09-08 Applied Materials, Inc. Adaptive multivariate fault detection
US7737533B2 (en) * 2006-08-10 2010-06-15 Vishay General Semiconductor Llc Low voltage transient voltage suppressor with tapered recess extending into substrate of device allowing for reduced breakdown voltage
US7554839B2 (en) * 2006-09-30 2009-06-30 Alpha & Omega Semiconductor, Ltd. Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch
US8010321B2 (en) * 2007-05-04 2011-08-30 Applied Materials, Inc. Metrics independent and recipe independent fault classes
US7765020B2 (en) * 2007-05-04 2010-07-27 Applied Materials, Inc. Graphical user interface for presenting multivariate fault contributions
US7538395B2 (en) * 2007-09-21 2009-05-26 Semiconductor Components Industries, L.L.C. Method of forming low capacitance ESD device and structure therefor
US7579632B2 (en) * 2007-09-21 2009-08-25 Semiconductor Components Industries, L.L.C. Multi-channel ESD device and method therefor
US7666751B2 (en) * 2007-09-21 2010-02-23 Semiconductor Components Industries, Llc Method of forming a high capacitance diode and structure therefor
CN101557103B (zh) * 2008-04-11 2011-09-14 上海韦尔半导体股份有限公司 瞬态电压抑制器二极管及其制造方法
US7842969B2 (en) 2008-07-10 2010-11-30 Semiconductor Components Industries, Llc Low clamp voltage ESD device and method therefor
JP5454945B2 (ja) * 2008-09-05 2014-03-26 株式会社東芝 記憶装置
US7955941B2 (en) * 2008-09-11 2011-06-07 Semiconductor Components Industries, Llc Method of forming an integrated semiconductor device and structure therefor
CN101930975B (zh) * 2008-10-01 2014-04-16 万国半导体有限公司 在低电容瞬时电压抑制器(tvs)内整合控向二极管的优化配置
US8089095B2 (en) 2008-10-15 2012-01-03 Semiconductor Components Industries, Llc Two terminal multi-channel ESD device and method therefor
US7812367B2 (en) * 2008-10-15 2010-10-12 Semiconductor Components Industries, Llc Two terminal low capacitance multi-channel ESD device
US8338854B2 (en) * 2009-03-31 2012-12-25 Alpha And Omega Semiconductor Incorporated TVS with low capacitance and forward voltage drop with depleted SCR as steering diode
US8288839B2 (en) * 2009-04-30 2012-10-16 Alpha & Omega Semiconductor, Inc. Transient voltage suppressor having symmetrical breakdown voltages
FR2953062B1 (fr) * 2009-11-24 2011-12-16 St Microelectronics Tours Sas Diode de protection bidirectionnelle basse tension
KR100971460B1 (ko) * 2010-01-15 2010-07-22 주식회사 오디텍 양방향 브레이크다운 보호기능을 갖는 저전압 과도전압 억압디바이스 및 그 제조방법
FR2960097A1 (fr) * 2010-05-11 2011-11-18 St Microelectronics Tours Sas Composant de protection bidirectionnel
US8730629B2 (en) 2011-12-22 2014-05-20 General Electric Company Variable breakdown transient voltage suppressor
US9059324B2 (en) * 2013-06-30 2015-06-16 Texas Instruments Incorporated Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate
US9997507B2 (en) 2013-07-25 2018-06-12 General Electric Company Semiconductor assembly and method of manufacture
US9633843B2 (en) * 2014-06-25 2017-04-25 Global Wafers Co., Ltd Silicon substrates with compressive stress and methods for production of the same
KR101649222B1 (ko) 2014-10-17 2016-08-19 주식회사 시지트로닉스 비대칭 활성영역 조절에 의한 양방향 정전기, 전자기 간섭 및 서지 방호용 반도체 소자 및 그 제조 방법
KR101628754B1 (ko) 2015-02-17 2016-06-10 주식회사 시지트로닉스 양방향 대칭 항복전압을 갖는 듀얼 모드 방호소자의 제조 방법
CN104851919B (zh) 2015-04-10 2017-12-19 矽力杰半导体技术(杭州)有限公司 双向穿通半导体器件及其制造方法
CN108520874B (zh) * 2018-03-28 2021-04-06 南京矽力微电子技术有限公司 半导体器件及其制造方法
TWI653759B (zh) 2018-04-12 2019-03-11 世界先進積體電路股份有限公司 半導體結構及其形成方法
US10658228B2 (en) 2018-07-11 2020-05-19 Vanguard International Semiconductor Corporation Semiconductor substrate structure and semiconductor device and methods for forming the same
CN109449152B (zh) * 2018-10-31 2020-12-22 深圳市巴达木科技有限公司 一种抑制芯片及其制备方法
CN110504324B (zh) * 2019-08-12 2021-06-01 电子科技大学 一种高压瞬态电压抑制二极管
CN112687736B (zh) * 2020-12-05 2024-01-19 西安翔腾微电子科技有限公司 一种用于esd保护的基区变掺杂晶体管
CN116169181B (zh) * 2022-09-30 2023-07-18 富芯微电子有限公司 一种低漏电低压tvs器件及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4286279A (en) * 1976-09-20 1981-08-25 Hutson Jearld L Multilayer semiconductor switching devices
US5880511A (en) * 1995-06-30 1999-03-09 Semtech Corporation Low-voltage punch-through transient suppressor employing a dual-base structure

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4047196A (en) * 1976-08-24 1977-09-06 Rca Corporation High voltage semiconductor device having a novel edge contour
US4980315A (en) 1988-07-18 1990-12-25 General Instrument Corporation Method of making a passivated P-N junction in mesa semiconductor structure
US5166769A (en) 1988-07-18 1992-11-24 General Instrument Corporation Passitvated mesa semiconductor and method for making same
US5430595A (en) * 1993-10-15 1995-07-04 Intel Corporation Electrostatic discharge protection circuit
US5610434A (en) * 1995-11-07 1997-03-11 General Instrument Corporation Of Delaware Mesa semiconductor structure
JP2002541682A (ja) * 1999-04-08 2002-12-03 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ パンチスルーダイオード及び同ダイオードを製造する方法
US6549133B2 (en) * 2001-01-18 2003-04-15 Tri-Tronics, Inc. Remote transmitter and method
US6489660B1 (en) * 2001-05-22 2002-12-03 General Semiconductor, Inc. Low-voltage punch-through bi-directional transient-voltage suppression devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4286279A (en) * 1976-09-20 1981-08-25 Hutson Jearld L Multilayer semiconductor switching devices
US5880511A (en) * 1995-06-30 1999-03-09 Semtech Corporation Low-voltage punch-through transient suppressor employing a dual-base structure

Also Published As

Publication number Publication date
JP2005502190A (ja) 2005-01-20
CN100416836C (zh) 2008-09-03
KR100957796B1 (ko) 2010-05-13
EP1405347A2 (fr) 2004-04-07
CN1605127A (zh) 2005-04-06
JP4358622B2 (ja) 2009-11-04
KR20040017288A (ko) 2004-02-26
TWI257697B (en) 2006-07-01
US6600204B2 (en) 2003-07-29
EP1405347A4 (fr) 2009-08-19
WO2003015248A2 (fr) 2003-02-20
US20030205775A1 (en) 2003-11-06
US20030010995A1 (en) 2003-01-16
US6858510B2 (en) 2005-02-22
AU2002355597A1 (en) 2003-02-24

Similar Documents

Publication Publication Date Title
WO2003015248A3 (fr) Dispositifs de suppression de tension transitoire bidirectionnels a penetration a faible tension dotes d'une protection contre le claquage de surface et leurs procedes de production
EP0763259B1 (fr) Transistor a effet de champ et a zone de per age
EP1710834B1 (fr) Isolation pour dispositif à semiconducteur par double tranchée
US8035158B2 (en) Semiconductor device
EP0405045B1 (fr) Circuit intégré utilisant une technologie mixte comprenant des structures CMOS et des transistors bipolaires latéraux à haut rendement ayant une tension "early" accrue et sa fabrication
US6875650B2 (en) Eliminating substrate noise by an electrically isolated high-voltage I/O transistor
WO2012082840A1 (fr) Dispositifs à semi-conducteurs à isolation de surface arrière
CN102723360A (zh) 半绝缘外延的碳化硅及相关的宽带隙晶体管
JP2004064063A (ja) 高電圧縦型ｄｍｏｓトランジスタ及びその製造方法
JP4649006B2 (ja) 半導体装置
CN102856387A (zh) 使用选择性外延生长制造的半导体器件
TWI613712B (zh) 半導體裝置及其製造方法
CN107527922A (zh) 半导体装置以及半导体装置的制造方法
US6551937B2 (en) Process for device using partial SOI
US20020060339A1 (en) Semiconductor device having field effect transistor with buried gate electrode surely overlapped with source region and process for fabrication thereof
US20020140033A1 (en) SOI type semiconductor device and method of forming the same
CN103715211A (zh) 注入隔离器件及其形成方法
US7517742B2 (en) Area diode formation in SOI application
US6670255B2 (en) Method of fabricating lateral diodes and bipolar transistors
WO2002049118A3 (fr) Redresseur de barriere schottky a tranchee et son procede de fabrication
US5930660A (en) Method for fabricating diode with improved reverse energy characteristics
US10665703B2 (en) Silicon carbide transistor
WO2002045173A1 (fr) Dispositif semi-conducteur et son procede de production
EP1225624A3 (fr) Procédé pour la fabrication d'un transistor à canal vertical à haute mobilité par dépôt sélectif de SiGe ou de puits quantiques multiples
US7339203B2 (en) Thyristor and method of manufacture

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BY BZ CA CH CN CO CR CU CZ DE DM DZ EC EE ES FI GB GD GE GH HR HU ID IL IN IS JP KE KG KP KR LC LK LR LS LT LU LV MA MD MG MN MW MX MZ NO NZ OM PH PL PT RU SD SE SG SI SK SL TJ TM TN TR TZ UA UG UZ VN YU ZA ZM

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ UG ZM ZW AM AZ BY KG KZ RU TJ TM AT BE BG CH CY CZ DK EE ES FI FR GB GR IE IT LU MC PT SE SK TR BF BJ CF CG CI GA GN GQ GW ML MR NE SN TD TG

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2002794642

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 20028139097

Country of ref document: CN

Ref document number: 1020047000359

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2003520054

Country of ref document: JP

WWP Wipo information: published in national office

Ref document number: 2002794642

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642