CN116169181B - 一种低漏电低压tvs器件及其制造方法 - Google Patents
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Abstract
本发明公开了一种低漏电低压TVS器件，包括P型半导体衬底P0，所述P型半导体衬底P0上下两侧局部区域开设有N型扩散区N11和N12，位于P型半导体衬底P0上下两侧还开设有N型扩散区N21和N22，N型扩散区N21位于N型扩散区N11的两侧，N型扩散区N22位于N型扩散区N12的两侧，N型扩散区N11和N12的结深比N型扩散区N21和N22的结深深，本发明基于两个并联的PN结，较大面积的PN结击穿电压较高，漏电流较低，决定整个器件击穿电压的PN结面积较小，因而整个器件的漏电流大大降低，同时由于焊接区域的PN结结深较深，抵抗焊接应力的能力得以大大提升。
Description
技术领域
本发明涉及半导体防护器件技术领域，具体涉及一种低漏电低压TVS器件及其制造方法。
背景技术
TVS器件是一种瞬态过压浪涌防护器件，TVS器件通常并联在被保护的电路中，当被保护电路端口出现超过TVS击穿电压的瞬态过电压时，TVS器件就会开始动作，以ns级的响应速度将瞬态浪涌过电压钳位在一个较低的电压，从而保护电路免受瞬态过压浪涌损坏，TVS具有响应时间快、击穿电压偏差小、钳位精准等优点，因此广泛应用于各种电子线路中。
TVS器件的主要参数有瞬态浪涌功率PPP、反向工作电压VRWM、击穿电压VBR和反向漏电流IR，随着电子电路的低功耗化以及节能减排的推进，要求TVS器件的静态功耗越来越低，即要求TVS器件有较低的反向漏电流IR。
高电压TVS器件（击穿电压大于8V）利用的是雪崩击穿机理，因此反向漏电流通常较低，一般小于1μA；击穿电压较低（击穿电压6-7.5V）的低电压TVS器件利用的是齐纳击穿的机理，反向漏电流通常较大，一般达到几百μA级别，在电路中产生较大的静态功耗。
传统的低压TVS器件采用如图9或图10的结构，在P型衬底两面扩散N型掺杂区与衬底形成PN结，然后用氧化层或者沟槽玻璃保护PN结，采用这种结构的低压TVS，利用的是齐纳击穿机理，漏电流较大，并且漏电流与PN结面积成正比，PN结较大的高功率低压TVS器件漏电流甚至达到mA级别，严重限制了低压TVS器件的应用。
传统低压TVS的另外一个不足在于：为了得到较低的击穿电压，PN结结深通常做的较浅，承受焊接应力的能力较弱，因此封装良率和长期使用可靠性较低。
发明内容
本发明的目的在于提供一种低漏电低压TVS器件，包括P型半导体衬底P0，所述P型半导体衬底P0上下两侧局部区域开设有N型扩散区N11和N12，位于P型半导体衬底P0上下两侧还开设有N型扩散区N21和N22，N型扩散区N21位于N型扩散区N11的两侧，N型扩散区N22位于N型扩散区N12的两侧，N型扩散区N11和N12的结深比N型扩散区N21和N22的结深深，本发明基于两个并联的PN结，较大面积的PN结击穿电压较高，漏电流较低，决定整个器件击穿电压的PN结面积较小，因而整个器件的漏电流大大降低；同时由于焊接区域的PN结结深较深，抵抗焊接应力的能力得以大大提升。
本发明的目的可以通过以下技术方案实现：
一种低漏电低压TVS器件，包括P型半导体衬底P0，所述P型半导体衬底P0上下两侧局部区域开设有N型扩散区N11和N12，位于P型半导体衬底P0上下两侧还开设有N型扩散区N21和N22；
其中，N型扩散区N21位于N型扩散区N11的两侧，N型扩散区N22位于N型扩散区N12的两侧；
所述N型扩散区N11和N12的结深比N型扩散区N21和N22的结深深。
作为本发明进一步的方案：所述P型半导体衬底P0左右两侧且靠近上下表面的位置处均开设有玻璃钝化沟槽。
作为本发明进一步的方案：所述P型半导体衬底P0的上表面设置有金属层M1，金属层M1形成低漏电低压TVS的电极T1。
作为本发明进一步的方案：所述P型半导体衬底P0的下表面设置有金属层M2，金属层M2形成低漏电低压TVS的电极T2。
作为本发明进一步的方案：所述N型扩散区N11和N12与P型半导体衬底P0形成PN结J1，所述N型扩散区N21和N22与P型半导体衬底P0形成PN结J2，J1结的结深比J2结深，J1结的击穿电压比J2结高。
作为本发明进一步的方案：所述PN结J1在P型半导体衬底P0上位于焊接金属区域下方。
作为本发明进一步的方案：所述PN结J2在P型半导体衬底P0上位于金属外侧以及玻璃钝化沟槽之间。
作为本发明进一步的方案：所述P型半导体衬底P0上的N型掺杂区N11、N12、N21、N22用扩散方式形成。
作为本发明进一步的方案：所述P型半导体衬底P0上的N型掺杂区N11、N12、N21、N22用离子注入方式形成。
一种低漏电低压TVS器件的制造方法，工艺流程包括：衬底准备、抛光、氧化、一次光刻、磷扩散一、氧化层去除、磷扩散二、沟槽光刻及钝化、引线孔光刻、金属蒸发、金属反刻和合金。
本发明的有益效果：本发明低漏电低压TVS器件具有两个并联的PN结，较大面积的PN结击穿电压较高，漏电流较低，决定整个器件击穿电压的PN结面积较小，因而整个器件的漏电流大大降低；
同时由于焊接区域的PN结结深较深，抵抗焊接应力的能力得以大大提升。
附图说明
下面结合附图对本发明作进一步的说明。
图1为本发明的低漏电低压TVS器件结构示意图；
图2为本发明的低漏电低压TVS衬底完成抛光后的结构示意图；
图3为本发明的低漏电低压TVS完成氧化后的结构示意图；
图4为本发明的低漏电低压TVS完成第一次磷扩散后的结构示意图；
图5为本发明的低漏电低压TVS完成第二次磷扩散后的结构示意图；
图6为本发明的低漏电低压TVS完成沟槽光刻和钝化后的结构示意图；
图7为本发明的低漏电低压TVS完成接触孔光刻后的结构示意图；
图8为本发明的低漏电低压TVS完成金属蒸发和金属光刻后的结构示意图；
图9为传统平面结构低压TVS结构示意图；
图10为传统台面结构低压TVS结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
请参阅图1-图8所示，本发明为一种低漏电低压TVS器件，包括P型半导体衬底P0和位于P型半导体衬底P0上下两侧局部区域的N型扩散区N11和N12；
还包括位于P型半导体衬底P0上下两侧的N型扩散区N21和N22，N型扩散区N11和N12的结深比N型扩散区N21和N22的结深深。
在一个具体实施例中，本发明的低漏电低压TVS器件还包括位于P型半导体衬底P0左右两侧靠近上下表面的玻璃钝化沟槽G31、G32、G33和G34；
其中，还包括位于P型半导体衬底P0上下表面的金属层M1和M2，金属层M1和M2形成低漏电低压TVS器件的两个电极T1和T2。
具体的：P型半导体衬底P0上下两侧局部区域的N型扩散区N11和N12与P型半导体衬底P0形成PN结J1，P型半导体衬底P0上下两侧的N型扩散区N21和N22与P型半导体衬底P0形成PN结J2，J1的结深比J2深，J1结的击穿电压比J2结高；
优选的，J1结的结深为15-20μm，击穿电压在8-9V，J2结的结深为8-12μm，击穿电压在6-7.5V。
其中，金属层M1或金属层M2与P型半导体衬底P0的连接区域为焊接金属区域；
其中，P型半导体衬底P0上的N型掺杂区N11、N12、N21、N22用扩散方式形成；
在另一个实施例中，P型半导体衬底P0上的N型掺杂区N11、N12、N21、N22也能够用离子注入方式形成。
一种低漏电低压TVS器件的制造方法，工艺步骤包括：衬底准备、抛光、氧化、一次光刻、第一次磷扩散、氧化层去除、第二次磷扩散、沟槽光刻及钝化、引线孔光刻、金属蒸发、金属反刻和合金；
具体工艺步骤为：
一、衬底材料
P型硅单晶片，电阻率ρ：0.001-0.010Ω·cm、片厚：240-280μm；
二、抛光
用抛光机将P型衬底双面抛光至厚度为200-240μm，要求表面无脏污、无划痕、无麻点，抛光完成后的结构如图2所示；
三、氧化
采用氢氧合成的工艺在硅片表面生长一层二氧化硅层，温度T=1100±5℃，时间t=3.5h，二氧化硅层厚度Tox≥1.5μm，氧化完成后的结构如图3所示；
四、一次光刻
采用双面对准曝光方式，利用一次光刻区光刻版，经过匀胶、曝光、显影、腐蚀工步在硅片的上下两面形成一次磷扩散掺杂区窗口；
五、第一次磷扩散
S1、磷预沉积：利用三氯氧磷做为扩散掺杂源，在硅片表面形成一定表面浓度的掺杂区，沉积温度1030℃-1130℃，时间60min-180min，通源量0.5L/min-1.5L/min，沉积方块电阻0.6Ω-1.6Ω；
S2、推结:先用HF：去离子水=1:10的漂洗液漂掉硅片表面的磷硅玻璃，再进行推结，推结温度T=1250±5℃,时间t=5-10h，推结结深15-20μm,一次磷扩散完成后的结构如图4所示。
六、第二次磷扩散
W1、磷预沉积：先用氢氟酸漂光表面的氧化层，然后利用三氯氧磷做为扩散掺杂源，在硅片表面形成一定表面浓度的掺杂区，沉积温度1100℃-1150℃，时间30min-60min，通源量0.5L/min-1.5L/min，沉积方块电阻0.6Ω-0.9Ω；
W2、推结:先用HF：去离子水=1:10的漂洗液漂掉硅片表面的磷硅玻璃，再进行推结，推结温度T=1150±5℃,时间t=2-6h，推结结深8-12μm，推结后在硅片表面生长一层氧化层，厚度15000±500Å,二次磷扩散完成后的结构如图5所示;
七、沟槽光刻及钝化
利用沟槽区光刻版在硅片上形成沟槽区图案，然后用硅腐蚀液腐蚀出沟槽，槽深20-50μm，并在沟槽内形成钝化层,沟槽钝化完成后的结构如图6所示;
八、引线孔光刻
利用引线孔光刻版，经过匀胶、曝光、显影、腐蚀、去胶工步在硅片的上下两面形成金属接触区窗口，引线孔完成后的结构如图7所示。
九、钛镍银蒸发
利用电子束蒸发方式，在硅片的两面各蒸发钛镍银层，钛厚度为1000±200Å，镍厚度为5000±1000Å，银厚度为20000±2000Å;
十、金属反刻
利用金属区光刻版，经过匀胶、曝光、显影、金属腐蚀、去胶工步在硅片的上下两面形成金属接触区，金属反刻后的结构如图8所示;
十一、合金
采用真空合金工艺使得钛镍银与硅形成良好的欧姆接触，温度500±5℃，时间t=30min。
以上对本发明的一个实施例进行了详细说明，但所述内容仅为本发明的较佳实施例，不能被认为用于限定本发明的实施范围。凡依本发明申请范围所作的均等变化与改进等，均应仍归属于本发明的专利涵盖范围之内。
Claims (9)
1.一种低漏电低压TVS器件，包括P型半导体衬底P0，其特征在于，所述P型半导体衬底P0上下两侧局部区域开设有N型扩散区N11和N12，位于P型半导体衬底P0上下两侧还开设有N型扩散区N21和N22；
其中，N型扩散区N21位于N型扩散区N11的两侧，N型扩散区N22位于N型扩散区N12的两侧；
所述N型扩散区N11和N12的结深比N型扩散区N21和N22的结深深；
所述N型扩散区N11和N12与P型半导体衬底P0形成PN结J1，所述N型扩散区N21和N22与P型半导体衬底P0形成PN结J2，J1结的结深比J2结深，J1结的击穿电压比J2结高。
2.根据权利要求1所述的一种低漏电低压TVS器件,其特征在于，所述P型半导体衬底P0左右两侧且靠近上下表面的位置处均开设有玻璃钝化沟槽。
3.根据权利要求1所述的一种低漏电低压TVS器件,其特征在于，所述P型半导体衬底P0的上表面设置有金属层M1，金属层M1形成低漏电低压TVS的电极T1。
4.根据权利要求3所述的一种低漏电低压TVS器件,其特征在于，所述P型半导体衬底P0的下表面设置有金属层M2，金属层M2形成低漏电低压TVS的电极T2。
5.根据权利要求1所述的一种低漏电低压TVS器件,其特征在于，所述PN结J1在P型半导体衬底P0上位于焊接金属区域下方。
6.根据权利要求1所述的一种低漏电低压TVS器件,其特征在于，所述PN结J2在P型半导体衬底P0上位于金属外侧以及玻璃钝化沟槽之间。
7.根据权利要求1所述的一种低漏电低压TVS器件,其特征在于，所述P型半导体衬底P0上的N型掺杂区N11、N12、N21、N22用扩散方式形成。
8.根据权利要求1所述的一种低漏电低压TVS器件,其特征在于，所述P型半导体衬底P0上的N型掺杂区N11、N12、N21、N22用离子注入方式形成。
9.一种根据权利要求1-8任一项所述的低漏电低压TVS器件的制造方法,其特征在于，工艺流程包括：衬底准备、抛光、氧化、一次光刻、磷扩散一、氧化层去除、磷扩散二、沟槽光刻及钝化、引线孔光刻、金属蒸发、金属反刻和合金。
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Denomination of invention: A Low Leakage Low Voltage TVS Device and Its Manufacturing Method Effective date of registration: 20231225 Granted publication date: 20230718 Pledgee: Anhui pilot Free Trade Zone Hefei area sub branch of Huishang Bank Co.,Ltd. Pledgor: FU XIN MICROELECTRONICS CO.,LTD. Registration number: Y2023980074110 |