WO2023045393A1 - Tvs芯片及其生产方法 - Google Patents

Tvs芯片及其生产方法 Download PDF

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WO2023045393A1
WO2023045393A1 PCT/CN2022/096369 CN2022096369W WO2023045393A1 WO 2023045393 A1 WO2023045393 A1 WO 2023045393A1 CN 2022096369 W CN2022096369 W CN 2022096369W WO 2023045393 A1 WO2023045393 A1 WO 2023045393A1
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silicon substrate
area
production method
junction
tvs chip
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PCT/CN2022/096369
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English (en)
French (fr)
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汪良恩
李建利
汪曦凌
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安徽芯旭半导体有限公司
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    • H01L29/8613—
    • H01L29/0638—
    • H01L29/0684—
    • H01L29/66136—

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  • the invention relates to the technical field of semiconductors, in particular to a TVS chip and a production method thereof.
  • Transient Voltage Suppressor for short is a high-efficiency protection device in the form of a diode.
  • TVS diode When the two poles of the TVS diode are impacted by reverse transient high energy, it can change the high impedance between its two poles to low impedance at a speed of 10 minus 12 seconds, absorbing surge power up to several thousand watts , so that the voltage between the two poles is clamped at a predetermined value, effectively protecting the precision components in the electronic circuit from being damaged by various surge pulses.
  • the electrical performance of TVS is realized by the movement of electrons and holes in PN.
  • the depth of PN junction is directly related to the level of breakdown voltage, that is, the shallower the PN junction, the lower the breakdown voltage. The lower the voltage.
  • the breakdown voltage is to be very low, the PN junction must be made very shallow.
  • mesa-type TVS chips generally adopt a diffusion process. After the silicon wafer is doped on the substrate and polished, and after diffusion, certain lattice defects will be formed on the surface, and the closer to the surface of the silicon wafer, this There will be more defects.
  • the invention provides a TVS chip and a production method thereof, which solves the technical problem of large leakage current of the existing mesa-type TVS chip below 10V.
  • the present application provides a TVS chip production method, the method comprising:
  • the silicon substrate is oxidized after cleaning to form an oxide film
  • the surface of the oxide film is coated with photoresist, and the oxide film in the area that needs to be diffused is removed by photolithography to form a ditching area;
  • a diffusion source is attached to the surface of the silicon substrate, which is diffused in the shallow trench to form an outer deep junction layer;
  • a diffusion source is attached to the surface area of the silicon substrate, and all areas on the surface of the silicon substrate are diffused to form an inner shallow junction layer.
  • the method also includes:
  • the silicon substrate includes boron-doped silicon or phosphorus silicon, and its resistivity is less than 0.01 ⁇ m.
  • said S3 includes:
  • the trenching area is chemically corroded for 1 to 5 minutes by corrosive liquid to form a shallow trench with a depth of 10 to 20 ⁇ m.
  • said S5 includes:
  • said S7 includes:
  • said S8 includes:
  • the oxide layer formed by diffusion is removed by etching solution, cleaned, and dried; the second photolithography is carried out to leave an etching area in the center of the shallow trench area, and the area of the etching area S and the upper surface area M of the shallow trench area relationship is Drop the etching solution on the etching area, etch for 10-30 minutes to form a deep trench with an etching depth of 50 ⁇ m-150 ⁇ m, and clean and dry it.
  • the present application provides a TVS chip, and the TVS chip is made by the TVS chip production method as described above.
  • the invention provides a TVS chip and a production method thereof. Compared with the prior art, it has the following beneficial effects:
  • two PN junction layers are formed by two diffusions, and the deep junction of the outer layer can protect the shallow junction of the inner layer, thereby effectively strengthening the protection of the PN junction and reducing the ability of lattice defect pollution. reduce leakage current.
  • the diffusion source is positioned through the shallow trench, which facilitates subsequent operations and production.
  • Fig. 1 is the flowchart of a kind of TVS chip production method of an embodiment
  • Fig. 2 is the chip schematic diagram of cutting money of a kind of TVS chip production method in an embodiment
  • FIG. 3 is a schematic structural diagram of a TVS chip according to an embodiment of the present invention.
  • the embodiment of the present application provides a TVS chip and its production method, which solves the technical problem of excessive leakage current of the existing mesa-type TVS chip with a breakdown voltage of less than 10V, and realizes that the deep junction of the outer layer can protect the shallow junction of the inner layer. junction, reducing leakage current.
  • the protection circuit is to prevent the key sensitive components in the circuit from being damaged by overcurrent, overvoltage, overheating and other impacts.
  • the pros and cons of the protection circuit are crucial to the quality and life of electronic products.
  • TVS is a high-efficiency circuit protection device commonly used in the world at present. Its circuit symbol is the same as that of ordinary Zener diodes, and its shape is no different from that of ordinary diodes. Its main feature is that under reverse application conditions, when subjected to a high-energy large pulse, its working impedance immediately drops to an extremely low conduction value, thereby allowing a large current to pass, while clamping the voltage at a predetermined level. The response time is only 10 -12 seconds, so it can effectively protect the precision components in the electronic circuit.
  • the embodiment of the present invention forms two PN junction layers through two diffusions.
  • the deep junction of the outer layer can protect the shallow junction of the inner layer, thereby effectively strengthening the ability of PN junction protection and reducing impurity pollution, and reducing leakage current. .
  • an embodiment of the present invention provides a TVS chip production method, which is used to produce the TVS chip in the first aspect. As shown in Figure 1, the method includes the following steps:
  • the surface of the oxide film is coated with photoresist, and the oxide film in the area that needs to be diffused is removed by photolithography to form a ditching area;
  • a diffusion source is attached to the surface of the silicon substrate, which is diffused in the shallow trench to form an outer deep junction layer;
  • a diffusion source is attached to the surface area of the silicon substrate, and all areas are diffused to form an inner shallow junction layer;
  • the deep junction of the outer layer can protect the shallow junction of the inner layer, thereby effectively strengthening the ability of PN junction protection and reducing impurity pollution, and reducing leakage. current.
  • the diffusion source is positioned through the shallow trench, which facilitates subsequent operations and production.
  • step S1 the silicon substrate is cleaned and then oxidized to add an oxide film on its surface.
  • the specific implementation process is as follows:
  • the silicon substrate After the silicon substrate is cleaned, it is placed in a mixed gas of N2 , O2 and water vapor under high temperature conditions to form a silicon dioxide oxide film on the surface of the silicon substrate.
  • the production method of the TVS chip whose breakdown voltage is less than 10V is aimed at, because the breakdown voltage is very low, so the doping concentration of the silicon substrate will be relatively high.
  • the higher the doping concentration of the substrate the slower the diffusion rate of the phosphorus source or boron source inside the silicon wafer, which is more conducive to controlling the junction depth of the PN junction formed by diffusion.
  • the silicon substrate is boron-doped silicon or phosphorus-doped silicon, and its resistivity is ⁇ 0.01 ⁇ m.
  • step S2 the surface of the oxide film is coated with photoresist, and the oxide film is removed in the area to be diffused by photolithography to form a ditching area.
  • the specific implementation process is as follows:
  • the photoresist coated on both sides of the silicon substrate is pre-baked, exposed, and developed, and the silicon dioxide in the area that needs to be diffused is removed in a mixed solution composed of HF, NH 4 F, and H 2 O to form a trench. district.
  • step S3 the trenched silicon substrate is put into an etching solution to form a shallow trench.
  • the specific implementation process is as follows:
  • the silicon substrate after trenching is placed in an anti-corrosion flower basket, and then the flower basket is placed in an etching tank filled with corrosive liquid.
  • the corrosive solution is a mixture of nitric acid, hydrofluoric acid and other corrosive solutions, chemically corrodes the ditching area for 1 to 5 minutes at a temperature of -10°C to 0°C, and forms a shallow trench with a depth of 10-20 ⁇ m .
  • step S4 the photoresist is removed, and the silicon substrate is cleaned.
  • the specific implementation process is as follows:
  • step S5 a diffusion source is attached to the surface of the silicon substrate, and is diffused in the shallow trench to form an outer deep junction layer.
  • the specific implementation process is as follows:
  • step S6 the oxide film is removed, and the silicon substrate is cleaned.
  • the specific implementation process is as follows:
  • the oxide film and the oxide layer formed by the first diffusion are removed by etching solution, and the silicon substrate is cleaned.
  • the composition of the etching solution is the same as that of the etching solution in step S3.
  • step S7 a diffusion source is attached to the surface area of the silicon substrate, and all areas are diffused to form an inner shallow junction layer.
  • the specific implementation process is as follows:
  • Attach a boron or phosphorus liquid source on the surface of the silicon substrate diffuse at a temperature of 1100°C to 1300°C for 2 to 5 hours, and form an inner shallow junction layer, which is a shallow junction with a depth of 10-20 ⁇ m.
  • step S8 the oxide layer formed by diffusion is removed, and then a second photolithography is performed to form an etching area in the center of the shallow trench area, and the etching area is etched to form a deep trench.
  • the specific implementation process is as follows:
  • the oxide layer on the surface is removed by corrosive solution (same composition as that of the corrosive solution in step S3), cleaned and spin-dried.
  • Carrying out the second photolithography, leaving an etching area in the center of the shallow trench area, the relationship between the etching area S and the upper surface M of the shallow trench area is Drop the etching solution on the etching area, etch for 10-30 minutes to form a deep trench with an etching depth of 50 ⁇ m-150 ⁇ m, and clean and dry it.
  • the function of deep trenching is to expose the PN junction layer, so as to facilitate subsequent protection of the PN junction layer through glass passivation. At the same time, deep trenching can effectively reduce the thickness of the silicon substrate and facilitate subsequent cutting.
  • step S9 passivation, surface metallization, and dicing into individual TVS chips are performed after the deep trenching is completed.
  • the specific implementation process is as follows:
  • passivation methods There are two passivation methods, one is to passivate the oxide film, and the other is to passivate the glass.
  • the passivation of the oxide film is to mix oxygen and chlorine-containing gas to form an oxide layer through high-temperature oxidation. This oxide layer has a passivation effect. .
  • Surface metallization is to deposit the nickel in the nickel solution on the surface of the silicon wafer through a reducing agent and a catalyst by means of electroless nickel plating, and then form an alloy between the nickel and the silicon wafer through sintering, so that the silicon surface has solderability.
  • the nickel-plated silicon wafer is the finished wafer, which is cut along the groove of the wafer by a blade or laser-related equipment. As shown in Figure 2, the cutting line is the center of the deep groove. In this way, the wafer is divided into individual chips.
  • an embodiment of the present invention provides a TVS chip, and the TVS chip is manufactured by the above TVS chip production method.
  • the chip has a convex mesa structure as a whole, including a silicon substrate 1 , an inner shallow junction layer 2 , an outer deep junction layer 3 , an oxide layer 4 , a passivation glass layer 5 , and a metal surface 6 .
  • the silicon substrate 1 is a boss substrate, including a top layer, a middle layer and a bottom layer, wherein the middle layer is located between the top layer and the bottom layer, and is the corner of the boss substrate.
  • the inner shallow junction layer 2 is located on the top layer of the silicon substrate 1 and is formed by diffusing a diffusion source to the silicon substrate 1 .
  • the outer deep junction layer 3 is located on both sides of the inner shallow junction layer 2 , in the middle layer of the silicon substrate 1 , and is formed by diffusion from a diffusion source to the silicon substrate 1 .
  • the oxide layer 4 is attached to the surface of the outer deep junction layer 3 and the surface of the joint between the outer deep junction layer 3 and the inner shallow junction layer 2 , and the composition of the oxide layer 4 is silicon dioxide.
  • the passivation glass layer 5 is attached to the surface of the oxide layer 4 .
  • the metal surface 6 is attached to the surface of the inner shallow junction layer 2 not covered by the passivation glass layer 5 .
  • the deep junction of the outer layer can protect the shallow junction of the inner layer, thereby effectively strengthening the ability of PN junction protection and reducing impurity pollution, and reducing leakage current.
  • the boss substrate can form very good visual coordinates during the generation process, which can easily find which area is expanded by two nodes, which area is expanded by one node, that is, it is convenient to locate the diffusion source during the production process, thus forming Two layers of knots inside and outside.
  • the TVS chip and its production method according to the embodiment of the present invention because two PN junction layers are formed by two diffusions, the deep junction of the outer layer can protect the shallow junction of the inner layer, thereby effectively strengthening the protection of the PN junction and reducing the risk of impurity pollution capability, reducing leakage current.
  • the diffusion source is positioned through shallow grooves, which facilitates subsequent operations and production.
  • the chip of the embodiment of the present invention does not need an epitaxial layer, can effectively reduce production costs, and can be produced in batches to realize commercial sales.
  • the substrate used in the embodiment of the present invention is a silicon substrate with a high doping concentration, which can effectively reduce the diffusion rate of the boron or phosphorus liquid source inside the silicon wafer, and is more conducive to controlling the junction depth of the PN junction.

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Abstract

本发明提供一种TVS芯片及其生产方法，涉及半导体领域。本发明通过硅衬底清洗后进行氧化，形成氧化膜；氧化膜表面涂覆光刻胶，采用光刻的方式将需要扩散的区域氧化膜去除，形成开沟区；将开沟后的硅衬底放入腐蚀液，形成浅沟；去光刻胶，对硅衬底进行清洗；硅衬底表面附扩散源，浅沟内被扩散，形成外层深结层；去除氧化膜，并清洗硅衬底；硅衬底表面区域附上扩散源，所有区域被扩散，形成内层浅结层。本发明因为两次扩散形成了两个PN结层，外层的深结可以保护内层的浅结，从而有效加强PN结保护和降低晶格缺陷污染的能力，降低漏电流。同时，通过浅沟对扩散源进行定位，能方便后续操作，方便生产。

Description

TVS芯片及其生产方法
相关申请
本专利申请要求于2021年9月27日提交的专利申请号2021111390769、专利名称为TVS芯片及其生产方法的中国专利申请的优先权，专利申请号2021111390769这个中国专利申请的公开内容以引用方式全文并入于此。
技术领域
本发明涉及半导体技术领域，具体涉及一种TVS芯片及其生产方法。
背景技术
瞬态电压抑制二极管(Transient Voltage Suppressor)简称TVS，是一种二极管形式的高效能保护器件。当TVS二极管的两极受到反向瞬态高能量冲击时，它能以10的负12次方秒量级的速度，将其两极间的高阻抗变为低阻抗，吸收高达数千瓦的浪涌功率，使两极间的电压箝位于一个预定值，有效地保护电子线路中的精密元器件，免受各种浪涌脉冲的损坏。
TVS的电性能是通过PN的电子和空穴的移动来实现的，在衬底浓度不变的情况下，PN结深度和击穿电压的高低有直接的关联，即PN结越浅，击穿电压越低。反过来说，击穿电压如果要做的很低，就必须将PN结做的很浅。以台面型的TVS为例，台面型TVS芯片一般采 用扩散工艺，硅片在衬底掺杂后磨片，以及扩散后，表面会形成一定的晶格缺陷，而且离硅片表面越近，这种缺陷就会越多。击穿电压10V以下的产品，由于本身低压低，所以要求在工艺设计的时候，必须要将PN结深度降低，这样，距离硅片表面就很近，所以在芯片通电时，PN结延展区有晶格缺陷存在，从而使漏电流过大。
发明内容
(一)解决的技术问题
针对现有技术的不足，本发明提供了一种TVS芯片及其生产方法，解决了现有的10V以下的台面型TVS芯片漏电流较大的技术问题。
(二)技术方案
为实现以上目的，本发明通过以下技术方案予以实现：
第一方面，本申请提供一种TVS芯片生产方法，所述方法包括：
S1、硅衬底清洗后进行氧化，形成氧化膜；
S2、氧化膜表面涂覆光刻胶，采用光刻的方式将需要扩散的区域氧化膜去除，形成开沟区；
S3、将开沟后的硅衬底放入腐蚀液，形成浅沟；
S4、去光刻胶，对硅衬底进行清洗；
S5、硅衬底表面附扩散源，浅沟内被扩散，形成外层深结层；
S6、去除氧化膜，并清洗硅衬底；
S7、硅衬底表面区域附上扩散源，硅衬底表面所有区域被扩散，形成内层浅结层。
优选的，所述方法还包括：
S8、去除扩散形成的氧化层，再进行第二次光刻，在浅沟区域中心形成蚀刻区域，对蚀刻区域进行腐蚀，形成深开沟；
S9、钝化、表面金属化、切割，形成TVS芯片。
优选的，所述硅衬底包括掺硼硅或磷硅，其电阻率小于0.01Ω·m。
优选的，所述S3包括：
在温度条件为-10℃～0℃的条件下通过腐蚀液对开沟区化学腐蚀1～5min，形成深度为10～20μm的浅沟。
优选的，所述S5包括：
在硅衬底表面附硼或者磷液态源，在温度为1200℃～1300℃条件下扩散5～30h，形成深度在30～50μm的外层深结层。
优选的，所述S7包括：
在硅衬底表面附硼或者磷液态源，在温度为1100℃～1300℃条件下扩散2～5h，形成深度为10～20μm内层浅结层。
优选的，所述S8包括：
通过腐蚀液去除扩散形成的氧化层，并进行清洗，甩干；进行第二次光刻，在浅沟区域中心内留下蚀刻区域，所述蚀刻区域面积S和浅沟区域上表面面积M的关系为
Figure PCTCN2022096369-appb-000001
在蚀刻区域滴上腐蚀液，腐蚀10～30min，形成腐蚀深度50μm～150μm的深开沟，并清洗甩干。
第二方面，本申请提供一种TVS芯片，所述TVS芯片通过如上述所述的TVS芯片生产方法制成。
(三)有益效果
本发明提供了一种TVS芯片及其生产方法。与现有技术相比，具 备以下有益效果：
本发明的TVS芯片及其生产方法，因为两次扩散形成了两个PN结层，外层的深结可以保护内层的浅结，从而有效加强PN结保护和降低晶格缺陷污染的能力，降低漏电流。同时，通过浅沟对扩散源进行定位，能方便后续操作，方便生产。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例一种TVS芯片生产方法的流程图；
图2为一实施例中一种TVS芯片生产方法的切割钱的芯片示意图；
图3为本发明实施例一种TVS芯片的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请实施例通过提供一种TVS芯片及其生产方法，解决了现有 的击穿电压小于10V的台面型TVS芯片漏电流过大的技术问题，实现外层的深结可以保护内层的浅结，降低漏电流。
本申请实施例中的技术方案为解决上述技术问题，总体思路如下：
对于电子产品而言，保护电路是为了防止电路中的关键敏感型器件受到过流、过压、过热等冲击的损害。保护电路的优劣对电子产品的质量和寿命至关重要。TVS是目前国际上普遍使用的一种高效能电路保护器件，其电路符号和普通稳压二极管相同，外形也与普通二极管无异。它的主要特点是在反向应用条件下，当承受一个高能量的大脉冲时，其工作阻抗立即降至极低的导通值，从而允许大电流通过，同时把电压钳制在预定水平，其响应时间仅为10 -12秒级，因此可有效地保护电子线路中的精密元器件。然而，使用传统的磷硼扩散工艺备制TVS芯片，磷硼扩散会产生较多的晶格缺陷，而10V以下的产品因为PN深度较浅，当晶格缺陷离PN结比较近时，容易发生IR偏大或者失效。为了解决上述问题，本发明实施例通过两次扩散形成了两个PN结层，外层的深结可以保护内层的浅结，从而有效加强PN结保护和降低杂质污染的能力，降低漏电流。
为了更好的理解上述技术方案，下面将结合说明书附图以及具体的实施方式对上述技术方案进行详细的说明。
第一方面，本发明实施例提供一种TVS芯片生产方法，该生产方法用于生产第一方面的TVS芯片。如图1所示，该方法包括以下步骤：
S1、硅衬底清洗后进行氧化，使其表面增加氧化膜；
S2、氧化膜表面涂覆光刻胶，采用光刻的方式将需要扩散的区域 氧化膜去除，形成开沟区；
S3、将开沟后的硅衬底放入腐蚀液，形成浅沟；
S4、去光刻胶，对硅衬底进行清洗；
S5、硅衬底表面附扩散源，浅沟内被扩散，形成外层深结层；
S6、去除氧化膜，并清洗硅衬底；
S7、硅衬底表面区域附上扩散源，所有区域被扩散，形成内层浅结层；
S8、去除扩散形成的氧化层，再进行第二次光刻，在浅沟区域中心形成蚀刻区域，对蚀刻区域进行腐蚀，形成深开沟；
S9、钝化、表面金属化、切割，形成TVS芯片。
本发明实施例的TVS芯片生产方法，因为两次扩散形成了两个PN结层，外层的深结可以保护内层的浅结，从而有效加强PN结保护和降低杂质污染的能力，降低漏电流。同时，通过浅沟对扩散源进行定位，能方便后续操作，方便生产。
下面对各个步骤进行详细说明：
在步骤S1中，硅衬底清洗后进行氧化，使其表面增加氧化膜。具体实施过程如下：
将硅衬底清洗后在高温条件下，置于N 2和O 2以及水蒸气的混合气体中，在硅衬底表面生成二氧化硅氧化膜。
需要说明的是，在本发明实施例中，是针对击穿电压小于10V的TVS芯片的生产方法，因为击穿电压很低，所以硅衬底掺杂就会浓度较高。衬底掺杂浓度越高，那么磷源或者硼源在硅片内部扩散的速率 就会越慢，更有利于控制扩散形成的PN结的结深。在本发明实施例中，硅衬底为掺硼硅或掺磷硅，其电阻率＜0.01Ω·m。
在步骤S2中，氧化膜表面涂覆光刻胶，采用光刻的方式将需要扩散的区域氧化膜去除，形成开沟区。具体实施过程如下：
在硅衬底两面分别涂上的光刻胶，进行前烘、曝光、显影，在HF、NH 4F和H 2O组成的混合溶液中以去除需要扩散的区域的二氧化硅，形成开沟区。
在步骤S3中，将开沟后的硅衬底放入腐蚀液，形成浅沟。具体实施过程如下：
将开沟后的硅衬底放在抗腐蚀的花篮中，然后花篮放到装满腐蚀液的蚀刻槽中进行的。腐蚀液是由硝酸、氢氟酸等多种腐蚀液混合而成，在温度条件为-10℃～0℃的条件下对开沟区化学腐蚀1～5min，形成深度为10-20μm的浅沟。
在步骤S4中，去光刻胶，对硅衬底进行清洗。具体实施过程如下：
再将硅衬底放入硫酸溶液中，去除硅衬底表面的光刻胶，然后再清洗，甩干。
在步骤S5中，硅衬底表面附扩散源，浅沟内被扩散，形成外层深结层。具体实施过程如下：
在硅衬底表面附硼或者磷液态源，在温度为1200℃～1300℃条件下扩散5-30h，形成深度在30～50μm的外层深结层(深结)，该深结起到保护作用。
在步骤S6中，去除氧化膜，并清洗硅衬底。具体实施过程如下：
通过腐蚀液去除氧化膜以及第一次扩散形成的氧化层，并清洗硅衬底。该腐蚀液的成分和步骤S3中的腐蚀液相同。
在步骤S7中，硅衬底表面区域附上扩散源，所有区域被扩散，形成内层浅结层。具体实施过程如下：
在硅衬底表面附硼或者磷液态源，在温度为1100℃～1300℃条件下扩散2～5h，形成内层浅结层，内层浅结层为深度为10-20μm的浅结。
需要说明的是，本发明实施例中，扩散完成后，需投料小样，试制电压不足的，再次进行加时扩散。
在步骤S8中，去除扩散形成的氧化层，再进行第二次光刻，在浅沟区域中心形成蚀刻区域，对蚀刻区域进行腐蚀，形成深开沟，具体实施过程如下：
通过腐蚀液(和步骤S3中的腐蚀液成分相同)去除表面氧化层，并进行清洗，甩干。进行第二次光刻，在浅沟区域中心内留下蚀刻区域，所述蚀刻区域S和浅沟区域上表面M的关系为
Figure PCTCN2022096369-appb-000002
在蚀刻区域滴上腐蚀液，腐蚀10～30min，形成腐蚀深度50μm～150μm的深开沟，并清洗甩干。深开沟的作用在于暴露PN结层，方便后续通过玻璃钝化对PN结层进行保护。同时，深开沟能有效降低硅衬底的厚底，方便后续切割。
在步骤S9中，深开沟结束后再做钝化、表面金属化、切割成单个TVS芯片。具体实施过程如下：
钝化有两道，一道是进行氧化膜钝化，一道是玻璃钝化，氧化膜钝化是通过氧气和含氯气体进行混合，通过高温氧化形成氧化层，这 个氧化层是有钝化作用的。氧化层钝化之后，再通过玻璃浆涂覆，再通过高温进行烧结，从而形成玻璃结晶，即钝化玻璃层，对PN结进行进一步保护，进一步提高芯片的钝化能力，提升可靠性。
表面金属化，是通过化学镀镍的方式，将镍液中的镍通过还原剂和催化剂，沉积到硅片表面，再通过烧结将镍和硅片形成合金，从而使硅表面具有可焊性。
镀镍后的硅片即为成品的晶圆，通过的刀片或者激光相关的设备，沿着晶圆的沟道进行切割，如图2所示，切割的切割线为深开沟的中心处，从而使晶圆分割成一颗颗的芯片。
第二方面，本发明实施例提供一种TVS芯片，该TVS芯片通过如上述的TVS芯片生产方法制成。如图3所示，该芯片整体呈凸形台面结构，包括硅衬底1，内层浅结层2，外层深结层3，氧化层4，钝化玻璃层5，金属面6。
其中，所述硅衬底1为凸台衬底，包括顶层、中层和底层，其中，中层处于顶层和底层之间，为凸台衬底的拐角处。所述内层浅结层2位于硅衬底1顶层，由扩散源扩散至硅衬底1形成。所述外层深结层3位于内层浅结层2的两侧，处于硅衬底1的中层，由扩散源扩散至硅衬底1形成。所述氧化层4附着在外层深结层3表面、以及外层深结层3和内层浅结层2的衔接处表面，氧化层4的成分为二氧化硅。所述钝化玻璃层5附着在氧化层4表面。所述金属面6附着在内层浅结层2未被钝化玻璃层5覆盖的表面。本发明实施例的TVS芯片，外层的深结可以保护内层的浅结，从而有效加强PN结保护和降低杂质污染 的能力，降低漏电流。同时凸台衬底在生成过程中能形成很好的视觉坐标，能方便找到哪个区域是扩了两个结，哪个区域是扩了一个结，即方便生产过程中对扩散源进行定位，从而形成内外两层结层。
综上所述，与现有技术相比，具备以下有益效果：
1、本发明实施例的TVS芯片及其生产方法，因为两次扩散形成了两个PN结层，外层的深结可以保护内层的浅结，从而有效加强PN结保护和降低杂质污染的能力，降低漏电流。
2、本发明实施例通过浅沟对扩散源进行定位，能方便后续操作，方便生产。
3、本发明实施例的芯片无需外延层，能有效降低生产成本，且能批量化生产，实现商业化销售。
4、本发明实施例采用的衬底为掺杂浓度高的硅衬底，能有效减小硼或者磷液态源在硅片内部扩散的速率，更有利于控制PN结的结深。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (8)

  1. 一种TVS芯片生产方法，所述方法包括：
    S1、硅衬底清洗后进行氧化，形成氧化膜；
    S2、氧化膜表面涂覆光刻胶，采用光刻的方式将需要扩散的区域氧化膜去除，形成开沟区；
    S3、将开沟后的硅衬底放入腐蚀液，形成浅沟；
    S4、去光刻胶，对硅衬底进行清洗；
    S5、硅衬底表面附扩散源，浅沟内被扩散，形成外层深结层；
    S6、去除氧化膜，并清洗硅衬底；
    S7、硅衬底表面区域附上扩散源，硅衬底表面所有区域被扩散，形成内层浅结层。
  2. 如权利要求1所述的TVS芯片生产方法，所述方法还包括：
    S8、去除扩散形成的氧化层，再进行第二次光刻，在浅沟区域中心形成蚀刻区域，对蚀刻区域进行腐蚀，形成深开沟；
    S9、钝化、表面金属化、切割，形成TVS芯片。
  3. 如权利要求1所述TVS芯片生产方法，所述硅衬底包括掺硼硅或磷硅，其电阻率小于0.01Ω·m。
  4. 如权利要求1所述TVS芯片生产方法，所述S3包括：
    在温度条件为-10℃～0℃的条件下通过腐蚀液对开沟区化学腐蚀1～5min，形成深度为10～20μm的浅沟。
  5. 如权利要求1～4任一所述TVS芯片生产方法，所述S5包括：
    在硅衬底表面附硼或者磷液态源，在温度为1200℃～1300℃条件下 扩散5～30h，形成深度在30～50μm的外层深结层。
  6. 如权利要求1～4任一所述TVS芯片生产方法，所述S7包括：
    在硅衬底表面附硼或者磷液态源，在温度为1100℃～1300℃条件下扩散2～5h，形成深度为10～20μm内层浅结层。
  7. 如权利要求2所述TVS芯片生产方法，所述S8包括：
    通过腐蚀液去除扩散形成的氧化层，并进行清洗，甩干；进行第二次光刻，在浅沟区域中心内留下蚀刻区域，所述蚀刻区域面积S和浅沟区域上表面面积M的关系为
    Figure PCTCN2022096369-appb-100001
    在蚀刻区域滴上腐蚀液，腐蚀10～30min，形成腐蚀深度50μm～150μm的深开沟，并清洗甩干。
  8. 一种TVS芯片，所述TVS芯片通过如权利要求1～7所述的TVS芯片生产方法制成。
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