WO2020220664A1 - 一种可并联组合的整流二极管芯片的制造工艺 - Google Patents

一种可并联组合的整流二极管芯片的制造工艺 Download PDF

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WO2020220664A1
WO2020220664A1 PCT/CN2019/121777 CN2019121777W WO2020220664A1 WO 2020220664 A1 WO2020220664 A1 WO 2020220664A1 CN 2019121777 W CN2019121777 W CN 2019121777W WO 2020220664 A1 WO2020220664 A1 WO 2020220664A1
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doping
silicon wafer
wafer substrate
regions
film layer
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French (fr)
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吴念博
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苏州固锝电子股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66128—Planar diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes

Definitions

  • the invention relates to a diode manufacturing process, in particular to a manufacturing process of a rectifier diode chip that can be combined in parallel.
  • Diodes are widely used in various circuits. It can be said that there are diodes wherever there is a circuit, using its unidirectional characteristic to convert alternating current into direct current, so that the terminal parts of the circuit can obtain stable direct current input.
  • the existing manufacturing method of the rectifier diode is based on the N-type ⁇ 111> crystal orientation monocrystalline silicon wafer. The upper surface of the silicon wafer is doped with boron once to form a flat P region, and then the lower surface is formed by a phosphorus diffusion. The flat N area is then subjected to processes such as photolithography, metallization, and alloying, and finally the PN structure and electrode metal of the diode are formed to make a rectifier diode chip (also known as a "die” in the industry).
  • the existing diode structure has side wall leakage current, and the device reliability is low;
  • the purpose of the present invention is to provide a manufacturing process of a rectifier diode chip that can be combined in parallel.
  • a manufacturing process of rectifier diode chips that can be combined in parallel; select a silicon wafer substrate, and then operate according to the following steps:
  • a lower diffusion region is formed on the lower surface of the silicon wafer substrate by first doping
  • a silicon dioxide film layer is formed on both the upper surface and the lower surface of the silicon wafer substrate;
  • the silicon dioxide film layer on the upper surface of the silicon wafer substrate is masked by photoresist to remove the peripheral area outside the two spaced areas, and the photoresist is used as a mask layer to etch and remove the exposed The two spaced regions on the silicon dioxide film layer;
  • second doping is performed on the two spacer regions, so that an upper diffusion region is formed in the two spacer regions respectively, and the upper diffusion region is spaced apart from the lower diffusion region in the vertical direction;
  • trenches are formed in the edge regions of the two upper diffusion regions, and the depth of the trenches is 20-40um;
  • the silicon dioxide film layer on the upper surface of the silicon wafer substrate is removed, and the upper surface of the silicon wafer substrate and the trench are cleaned, and then a polysilicon passivation composite film layer is formed ;
  • a glass passivation layer is formed on the surface of the polysilicon passivation composite film layer in the trench;
  • the eighth step is to remove the polysilicon passivation composite film layers on the surfaces of the two upper diffusion regions to expose the two upper diffusion regions; at the same time, remove the thin film layers on the lower surface of the silicon wafer substrate to expose the lower diffusion regions;
  • metal layers are respectively deposited on the surfaces of the two upper diffusion regions and the lower diffusion regions to form metal electrodes.
  • the distance between the two upper diffusion regions is 200-300um.
  • the silicon wafer substrate has an N-type ⁇ 111> crystal orientation
  • the first doping is phosphorus impurity doping or arsenic impurity doping
  • the lower diffusion region is an N+ region, which is doped
  • the concentration is at least 10 21 atm/cm 3 , and the diffusion depth is 30-50 ⁇ m
  • the second doping is boron impurity doping or gallium impurity doping
  • the upper diffusion region is a P+ region
  • the doping concentration is at least 10 21 atm /cm 3
  • the diffusion depth is 50 ⁇ 70 ⁇ m.
  • the silicon wafer substrate has a P-type ⁇ 111> crystal orientation
  • the first doping is boron impurity doping or gallium impurity doping
  • the lower diffusion region is a P+ region.
  • the concentration is at least 10 21 atm/cm 3 , and the diffusion depth is 30-50 ⁇ m
  • the second doping is phosphorus impurity doping or arsenic impurity doping
  • the upper diffusion region is an N+ region
  • the doping concentration is at least 10 21 atm /cm 3
  • the diffusion depth is 50 ⁇ 70 ⁇ m.
  • the process conditions for the formation of the silicon dioxide film layer are as follows: in the furnace tube at 1150 ⁇ 0.5°C, first pass through an oxygen atmosphere for 30 ⁇ 5 minutes, and then pass through water vapor for 480 ⁇ 10 minutes Atmosphere, and finally an oxygen atmosphere for 30 ⁇ 5 minutes.
  • the process conditions of the phosphorus impurity doping are as follows: first, in the furnace tube at 1100°C ⁇ 0.5°C, the time is 2 ⁇ 0.05 hours, and the atmosphere is phosphorus oxychloride; after the furnace is soaked in hydrofluoric acid 30 ⁇ 5 Minutes, then, in a furnace tube at 1250 ⁇ 0.5°C for 4 ⁇ 0.05 hours, and the atmosphere is N 2 to form the N+ zone through the diffusion of phosphorus atoms.
  • the process conditions of the boron impurity doping are as follows: firstly, the liquid boron source is coated, and the time is 2 ⁇ 0.05 hours in the furnace tube at 1150 ⁇ 0.5°C, and the atmosphere is nitrogen; ⁇ 5 minutes, then, in a furnace tube at 1250 ⁇ 0.5°C for 18 ⁇ 0.05 hours, and the atmosphere is nitrogen, so as to form the P+ zone through the diffusion of boron atoms.
  • step 6 the polysilicon passivation composite thin film layer is deposited and formed by a CVD process, and the process conditions are as follows: First, pass silane gas and nitrous oxide at a temperature of 650 ⁇ 1°C Gas, the time is 25 ⁇ 1 minutes, wherein the flow rate of the silane gas is 130 ⁇ 5ml per minute, and the flow rate of the nitrous oxide gas is 30 ⁇ 2ml per minute; then, under the temperature condition of 780 ⁇ 1°C Continue to pass silane gas and nitrous oxide gas for 15 ⁇ 0.5 minutes, and the flow rates of the two gases are 25 ⁇ 5ml per minute for SiH 4 and 80 ⁇ 5ml per minute for N 2 O; finally a layer containing oxygen is formed The polysilicon passivation composite film layer of a polysilicon passivation film and a silicon dioxide film.
  • step 7 the process conditions for forming the glass passivation layer in the trench are: filling the trench with glass paste with a thickness of 25-35 ⁇ m, and then forming a dense glass through high-temperature sintering
  • the glass passivation layer has a temperature of 830 ⁇ 10°C and a time of 30 ⁇ 5 minutes.
  • a rectifier diode chip that can be combined in parallel, comprising a silicon wafer substrate, the lower surface of the silicon wafer substrate is formed by a first doping to form a lower diffusion region, and the upper surface of the silicon wafer substrate is formed by a second doping Two upper diffusion areas arranged horizontally, and the upper diffusion area and the lower diffusion area are arranged at intervals in the vertical direction;
  • grooves are opened at the edge regions of the two upper diffusion regions
  • the upper surface of the silicon wafer substrate is covered with a polysilicon passivation composite film layer on the peripheral area of the two upper diffusion regions and the surface of the trench; the trench is also filled with glass glue and sintered at high temperature A dense glass passivation layer is formed; a metal layer is deposited on the surfaces of the lower diffusion zone and the two upper diffusion zones to form metal electrodes respectively.
  • the depth of the groove is 20-40um.
  • the thickness of the glass glue is 25-35 ⁇ m.
  • the distance between the two upper diffusion zones is 200-300um.
  • the silicon wafer substrate has an N-type ⁇ 111> crystal orientation
  • the first doping is phosphorus impurity doping or arsenic impurity doping
  • the lower diffusion region is an N+ region, which is doped
  • the concentration is at least 10 21 atm/cm 3 , and the diffusion depth is 30-50 ⁇ m
  • the second doping is boron impurity doping or gallium impurity doping
  • the upper diffusion region is a P+ region
  • the doping concentration is at least 10 21 atm /cm 3
  • the diffusion depth is 50 ⁇ 70 ⁇ m.
  • the silicon wafer substrate has a P-type ⁇ 111> crystal orientation
  • the first doping is boron impurity doping or gallium impurity doping
  • the lower diffusion region is a P+ region.
  • the concentration is at least 10 21 atm/cm 3 , and the diffusion depth is 30-50 ⁇ m
  • the second doping is phosphorus impurity doping or arsenic impurity doping
  • the upper diffusion region is an N+ region
  • the doping concentration is at least 10 21 atm /cm 3
  • the diffusion depth is 50 ⁇ 70 ⁇ m.
  • the silicon wafer substrate with N-type ⁇ 111> crystal orientation can be used as chip A
  • the silicon wafer substrate with P-type ⁇ 111> crystal orientation can be used as chip B
  • chip A+B It can be assembled into a rectifier bridge by leading out.
  • the polysilicon passivation composite thin film layer is deposited and formed by a CVD process.
  • the process conditions are as follows: First, pass silane gas and nitrous oxide gas at a temperature of 650 ⁇ 1°C for a time of 25 ⁇ 1 minute, wherein the flow rate of the silane gas is 130 ⁇ 5ml per minute, and the flow rate of the nitrous oxide gas is 30 ⁇ 2ml per minute; then, continue to pass the silane gas under the temperature condition of 780 ⁇ 1°C And nitrous oxide gas, the time is 15 ⁇ 0.5 minutes, and the flow rates of the two gases are 25 ⁇ 5ml per minute for SiH 4 and 80 ⁇ 5ml per minute for N 2 O; finally a layer of oxygen-containing polysilicon passivation film and The polysilicon passivation composite film layer of the silicon dioxide film.
  • the present invention is a manufacturing process of a rectifier diode chip that can be combined in parallel; the steps include:
  • the lower diffusion zone is formed on the lower surface of the silicon wafer substrate by the first doping; 2.
  • the silicon dioxide film layer is formed on both the upper and lower surfaces of the silicon wafer substrate; 3.
  • the upper surface silicon dioxide film layer is etched and removed The two spacer regions; 4.
  • the second doping of the two spacer regions respectively forms the upper diffusion region, which is spaced apart from the lower diffusion region; 5.
  • Trenches are formed in the edge regions of the two upper diffusion regions; 6.
  • the silicon wafer substrate The silicon dioxide film layer on the upper surface is removed, cleaned and formed a polysilicon passivation composite film layer; 7.
  • a glass passivation layer is formed in the trench; 8.
  • the polysilicon passivation composite film layer on the surface of the two upper diffusion regions is removed and exposed Two upper diffusion regions are formed; the thin film layer on the lower surface of the silicon wafer substrate is removed at the same time, and the lower diffusion region is exposed; 9. A metal layer is deposited on the surfaces of the two upper and lower diffusion regions to form metal electrodes.
  • the advantages of the present invention include:
  • the U-shaped PN junction is formed by selective diffusion, which increases the effective area of the PN junction and significantly reduces the power consumption of the diode when it is used in the circuit;
  • a single chip can be manufactured by connecting two diodes with different crystal orientations in parallel and used as a half bridge directly in the circuit, or two chips The direct combination is a bridge pile.
  • the present invention is different from the conventional planar process on the one hand.
  • the conventional planar process can generally only achieve 600V. If it needs to reach 800 or more than 1000V, a complicated process is required, that is, it is realized by multiple voltage divider rings, and a larger chip is required. Area and complex process, the processing cost needs to be at least doubled to complete; on the other hand, it is different from the conventional trench process of 100-140um.
  • the conventional trench process requires more than 3 times the chemical corrosion of the deep trench.
  • the area of the glass passivation method increases the chance of contamination by impurities, resulting in high leakage current.
  • deep trenches can also cause problems such as warpage of the silicon wafer and increased process fragmentation rate.
  • the present invention can greatly simplify the packaging, thereby reducing material costs and labor costs, which is beneficial to reduce the processing cost of large-scale diode semiconductor devices, and realizes that the processing cost can be reduced by up to 30%, and Can improve the production efficiency per unit time. It can also reduce the energy consumption of the client, which is more conducive to reducing the waste of resources (eliminating the consumption of resin, solder, copper leads and other materials), and contributes to environmental protection.
  • Figure 1 is a schematic diagram of the first step of the embodiment of the utility model
  • Figure 2 is a schematic diagram of the principle of the second step of the embodiment of the utility model
  • Figure 3 is a schematic diagram of the principle of the third step of the embodiment of the utility model
  • Figure 4 is a schematic diagram of the principle of the fourth step of the embodiment of the utility model
  • Figure 5 is a schematic diagram of the fifth step of the embodiment of the utility model
  • Figure 6 is a schematic diagram of the principle of the sixth step of the embodiment of the utility model
  • Fig. 7 is a schematic diagram of the principle of the seventh step of the embodiment of the utility model.
  • Figure 8 is a schematic diagram of the principle of the eighth step of the embodiment of the utility model.
  • Fig. 9 is a schematic diagram of the principle of the ninth step of the embodiment of the utility model.
  • FIG. 10 is a schematic diagram of the structure of the silicon wafer substrate of the embodiment of the utility model with a P-type ⁇ 111> crystal orientation;
  • FIG. 11 is a schematic diagram of two diodes with different crystal orientations assembled in parallel to form a rectifier bridge according to an embodiment of the present invention.
  • Embodiment Refer to Figures 1-9, a manufacturing process of a rectifier diode chip that can be combined in parallel; select a silicon wafer substrate 1, and perform the following steps:
  • a lower diffusion region 2 is formed on the lower surface of the silicon wafer substrate 1 by first doping; if the silicon wafer substrate 1 has an N-type ⁇ 111> crystal orientation, The first doping is phosphorus impurity doping or arsenic impurity doping, and the lower diffusion region 2 is an N+ region 3 with a doping concentration of at least 10 21 atm/cm 3 and a diffusion depth of 30-50 ⁇ m;
  • the process conditions of the phosphorus impurity doping are as follows: firstly in the furnace tube at 1100°C ⁇ 0.5°C, the time is 2 ⁇ 0.05 hours, and the atmosphere is phosphorus oxychloride; after the furnace is soaked in hydrofluoric acid for 30 ⁇ 5 minutes, then at 1250 In the ⁇ 0.5°C furnace tube, the time is 4 ⁇ 0.05 hours, and the atmosphere is N 2 to form the N+ zone 3 through the diffusion of phosphorus atoms.
  • a silicon dioxide film layer 4 is formed on both the upper surface and the lower surface of the silicon wafer substrate 1; the process conditions are: 1150 ⁇ 0.5°C inside the furnace tube, first pass 30 ⁇ 5 minutes of oxygen atmosphere, then 480 ⁇ 10 minutes of water vapor atmosphere, and finally 30 ⁇ 5 minutes of oxygen atmosphere.
  • the silicon dioxide film layer 4 on the upper surface of the silicon wafer substrate 1 is masked by a photoresist to remove the peripheral regions other than the two spacer regions 5, and the photoresist is used as Mask layer, etching and removing the two spacer regions 5 on the exposed silicon dioxide film layer 4;
  • the two spacer regions 5 are subjected to second doping, so that an upper diffusion region 6 is formed in the two spacer regions 5, and the distance between the two upper diffusion regions 6 is 200-300um, and the upper diffusion region 6 is spaced apart from the lower diffusion region 2 in the vertical direction;
  • the second doping is boron impurity doping or gallium impurity doping, and the upper diffusion region 6 is a P+ region 7 ,
  • the doping concentration is at least 10 21 atm/cm 3 , and the diffusion depth is 50-70 ⁇ m;
  • the process conditions of the boron impurity doping are as follows: first coat liquid boron source in a furnace tube at 1150 ⁇ 0.5°C for 2 ⁇ 0.05 hours, and the atmosphere is nitrogen; after leaving the furnace, soak in hydrofluoric acid for 30 ⁇ 5 minutes, then, In the furnace tube at 1250 ⁇ 0.5°C, the time is 18 ⁇ 0.05 hours, and the atmosphere is nitrogen, so that the P+ zone 7 is formed by the diffusion of boron atoms.
  • a trench 8 is opened in the edge area of the two upper diffusion regions 6, and the depth of the trench 8 is 20-40um;
  • the damage layer on the surface of the silicon wafer substrate 1 can be removed to reduce the leakage current of the device; on the other hand, under the protection of the polysilicon passivation composite film layer 9 in step 6, the leakage current can be reduced. To improve reliability.
  • the silicon dioxide film layer 4 on the upper surface of the silicon wafer substrate 1 is removed, and the upper surface of the silicon wafer substrate 1 and the trench 8 are cleaned. Then a layer of polysilicon passivation composite thin film layer 9 is formed; the polysilicon passivation composite thin film layer 9 is deposited and formed by a CVD process (chemical vapor deposition process), and the process conditions are: first, at a temperature of 650 ⁇ 1°C Pass silane (SiH 4 ) gas and nitrous oxide (N 2 O) gas for 25 ⁇ 1 minutes, wherein the flow rate of the silane (SiH 4 ) gas is 130 ⁇ 5ml per minute, and the dinitrogen monoxide (N 2 O) gas The flow rate of nitrogen (N 2 O) gas is 30 ⁇ 2ml per minute; then, continue to pass in silane (SiH 4 ) gas and nitrous oxide (N 2 O) gas at a temperature of 780 ⁇ 1°C for a time of 15 ⁇ 0.5 minutes
  • a glass passivation layer 10 is formed on the surface of the polysilicon passivation composite film layer 9 in the trench 8;
  • the process conditions for forming the glass passivation layer 10 in the trench 8 are: filling the trench 8 with glass paste with a thickness of 25-35 ⁇ m, and then sintering at a high temperature to form the dense glass passivation layer 10, The temperature is 830 ⁇ 10°C, and the time is 30 ⁇ 5 minutes.
  • the eighth step remove the polysilicon passivation composite film layer 9 on the surfaces of the two upper diffusion regions 6 to expose the two upper diffusion regions 6; at the same time, remove two of the lower surface of the silicon wafer substrate 1.
  • the silicon oxide film layer 4 exposes the lower diffusion region 2.
  • a metal layer 11 is deposited on the surfaces of the two upper diffusion regions 6 and the lower diffusion region 2 to form metal electrodes.
  • a rectifier diode chip that can be combined in parallel includes a silicon wafer substrate 1.
  • the lower surface of the silicon wafer substrate 1 forms a lower diffusion region 2 through a first doping, and the upper surface of the silicon wafer substrate 1 passes through a first doping.
  • Two doping forms two upper diffusion regions 6 arranged horizontally, the distance d between the two upper diffusion regions 6 is 200-300um, and the upper diffusion region 6 and the lower diffusion region 2 are spaced in the vertical direction Set up
  • trenches 8 are opened at the edge regions of the two upper diffusion regions 6, and the depth of the trenches 8 is 20-40um.
  • the upper surface of the silicon wafer substrate 1 is covered with a layer of polysilicon passivation composite film layer 9 on the peripheral area of the two upper diffusion regions 6 and the surface of the trench 8; the trench 8 is also filled with glass glue ,
  • the thickness of the glass glue is 25-35 ⁇ m, and a dense glass passivation layer 10 is formed by high-temperature sintering;
  • a metal layer 11 is deposited on the surfaces of the lower diffusion region 2 and the two upper diffusion regions 6 to form metal electrodes, respectively.
  • the silicon wafer substrate 1 has an N-type ⁇ 111> crystal orientation
  • the first doping is phosphorus impurity doping or arsenic impurity doping
  • the lower diffusion region 2 is an N+ region 3.
  • the doping concentration is at least 10 21 atm/cm 3 , and the diffusion depth is 30-50 ⁇ m
  • the second doping is boron impurity doping or gallium impurity doping
  • the upper diffusion region 6 is a P+ region 7, which The doping concentration is at least 10 21 atm/cm 3 , and the diffusion depth is 50-70 ⁇ m.
  • the silicon wafer substrate 1 has a P-type ⁇ 111> crystal orientation
  • the first doping is boron impurity doping or gallium impurity doping
  • the lower diffusion region 2 is a P+ region 7.
  • the doping concentration is at least 10 21 atm/cm 3 , and the diffusion depth is 30-50 ⁇ m
  • the second doping is phosphorus impurity doping or arsenic impurity doping
  • the upper diffusion region 6 is the N+ region 3, which is doped
  • the concentration is at least 10 21 atm/cm 3 and the diffusion depth is 50-70 ⁇ m.
  • the silicon wafer substrate 1 with N-type ⁇ 111> crystal orientation can be used as chip A
  • the silicon wafer substrate with P-type ⁇ 111> crystal orientation can be used as chip B
  • chip A+ B can be assembled into a rectifier bridge by leading out.
  • the polycrystalline silicon passivation composite thin film layer 9 is deposited and formed by a CVD process (chemical vapor deposition process), and the process conditions are as follows: first, pass silane (SiH 4 ) gas and a silane gas at a temperature of 650 ⁇ 1°C.
  • Nitrous oxide (N 2 O) gas the time is 25 ⁇ 1 minutes, the flow rate of the silane (SiH 4 ) gas is 130 ⁇ 5 ml per minute, and the flow rate of the nitrous oxide (N 2 O) gas is 30 ⁇ 2ml per minute; then, continue to pass in silane (SiH 4 ) gas and nitrous oxide (N 2 O) gas at a temperature of 780 ⁇ 1°C for 15 ⁇ 0.5 minutes, and the two gases
  • the flow rates are respectively 25 ⁇ 5 ml per minute for SiH 4 and 80 ⁇ 5 ml per minute for N 2 O; finally, a layer of the polysilicon passivation composite film layer 9 containing an oxygen-containing polysilicon passivation film and a silicon dioxide film is formed.

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  • Electrodes Of Semiconductors (AREA)

Abstract

一种可并联组合的整流二极管芯片的制造方法，所述方法包括如下步骤：在硅片衬底（1）下表面通过第一掺杂形成下部扩散区（2）；在硅片衬底（1）上、下表面均形成二氧化硅薄膜层（4）；刻蚀并去除上表面二氧化硅薄膜层（4）的两间隔区域（5）；对两所述间隔区域（5）进行第二掺杂，从而在两间隔区域（5）中分别形成一上部扩散区（6），所述上部扩散区（6）在上下方向上与所述下部扩散区（2）间隔设置；在两上部扩散区（6）的边缘区域开沟槽（8）；将硅片衬底（1）上表面的二氧化硅薄膜层（4）去除，清洗并形成多晶硅钝化复合薄膜层（9）；在沟槽（8）中形成玻璃钝化层（10）；将两上部扩散区（6）表面的多晶硅钝化复合薄膜层（9）去除，裸露出两上部扩散区（6）；同时去除硅片衬底（1）下表面的二氧化硅薄膜层（4），裸露出下部扩散区（2）；在两上部扩散区（6）及下部扩散区（2）的表面沉积金属层（11）形成金属电极。上述方法工艺简单，成本低且品质高。

Description

一种可并联组合的整流二极管芯片的制造工艺 技术领域
本发明涉及一种二极管制造工艺，具体涉及一种可并联组合的整流二极管芯片的制造工艺。
背景技术
二极管广泛应用在各种电路中，可以说凡有电路处皆有二级管，利用其单向导通的特性把交流电转化为直流电，使电路的终端部件可以获得稳定的直流电输入。现有整流二极管的制造方法是以N型〈111〉晶向单晶硅片为基本材料，在该硅片的上表面进行一次硼掺杂形成平的P区，然后在下表面进行一次磷扩散形成平的N区，然后再进行光刻、金属化、合金等工序，最终形成二极管的PN结构和电极金属，制成整流二极管芯片(业界亦称“晶粒”)。
现有技术的不足包括：
一、当需要组成桥式整流电路时，通常需要四个独立的二极管进行电连接，不利于产品的小型化，且工艺流程复杂，制造成本较高；
二、现有二极管结构存在侧壁的漏电流，器件可靠性低；
三、上述现有二极管在工作的过程中，反向截止，正向导通，在正向电流导通过程中由于其自身的正向压降存在，二极管会不断发热，P＝U*I(这里U是正向压降，I是代表正常工作的电流)。二极管发热的这部分功耗不但由于持续的发热而影响器件的可靠性和使用寿命，而且消耗大量无谓的能量，这和目前绿色节能的环保要求显得格格不入。
因此，如何解决上述现有技术存在的不足，便成为本发明所要研究解决的课题。
发明内容
本发明的目的是提供一种可并联组合的整流二极管芯片的制造工艺。
为达到上述目的，本发明采用的技术方案是：
一种可并联组合的整流二极管芯片的制造工艺；选择硅片衬底，然后按以下步骤进行操作：
第一步，在所述硅片衬底下表面通过第一掺杂形成一下部扩散区；
第二步，在所述硅片衬底上表面和下表面均形成一层二氧化硅薄膜层；
第三步，通过光刻胶掩膜硅片衬底上表面的所述二氧化硅薄膜层除去两间隔区域之外的周边区域，并以此光刻胶作为掩膜层，刻蚀并去除裸露的所述二氧化硅薄膜层上的两所述间隔区域；
第四步，对两所述间隔区域进行第二掺杂，从而在两间隔区域中分别形成一上部扩散区，所述上部扩散区在上下方向上与所述下部扩散区间隔设置；
第五步，在两所述上部扩散区的边缘区域开沟槽，沟槽的深度为20～40um；
第六步，将位于硅片衬底上表面的所述二氧化硅薄膜层去除，并对所述硅片衬底上表面以及所述沟槽进行清洗，然后形成一层多晶硅钝化复合薄膜层；
第七步，在所述沟槽中的多晶硅钝化复合薄膜层表面形成一层玻璃钝化层；
第八步，将两所述上部扩散区表面的多晶硅钝化复合薄膜层去除，裸露出两上部扩散区；同时去除所述硅片衬底下表面的薄膜层，裸露出所述下部扩散区；
第九步，在两所述上部扩散区以及所述下部扩散区的表面分别沉积金属层，形成金属电极。
上述技术方案中的有关内容解释如下：
1.上述方案中，两所述上部扩散区之间的距离为200～300um。
2.上述方案中，所述硅片衬底为N型〈111〉晶向，所述第一掺杂为磷杂质掺杂或砷杂质掺杂，所述下部扩散区为N+区，其掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；所述第二掺杂为硼杂质掺杂或镓杂质掺杂，所述上部扩散区为P+区，其掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm。
3.上述方案中，所述硅片衬底为P型〈111〉晶向，所述第一掺杂为硼杂质掺杂或镓杂质掺杂，所述下部扩散区为P+区，其掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；所述第二掺杂为磷杂质掺杂或砷杂质掺杂，所述上部扩散区为N+区，其掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm。
4.上述方案中，所述步骤二中，所述二氧化硅薄膜层形成的工艺条件为：1150±0.5℃炉管内，先经过30±5分钟的氧气气氛，再经过480±10分钟的水汽气氛，最后再经过30±5分钟的氧气气氛。
5.上述方案中，所述磷杂质掺杂的工艺条件为：首先在1100℃±0.5℃炉管内，时间为2±0.05小时，气氛为三氯氧磷；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为4±0.05小时，气氛为N 2的条件下进行，从而通过磷原子扩散形成所述N+区。
6.上述方案中，所述硼杂质掺杂的工艺条件为：首先涂覆液态硼源，在1150±0.5℃炉管内，时间为2±0.05小时，气氛为氮气；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为18±0.05小时，气氛为氮气的条件下进行，从而通过硼原子扩散形成所述P+区。
7.上述方案中，在步骤六中，所述多晶硅钝化复合薄膜层采用CVD工艺沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷气体和一氧化二氮气体，时间为25±1分钟，其中所述硅烷气体的流速为每分钟130±5ml，所述一氧化二氮气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷气体和一氧化二氮气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层。
8.上述方案中，在步骤七中，在所述沟槽中形成所述玻璃钝化层的工艺条件为：在沟槽内填充玻璃胶，厚度为25～35μm，然后通过高温烧结形成致密的所述玻璃钝化层，温度为830±10℃，时间为30±5分钟。
为达到上述目的，本发明采用的另一技术方案是：
一种可并联组合的整流二极管芯片，包括一硅片衬底，所述硅片衬底的下表面通过第一掺杂形成一下部扩散区，硅片衬底的上表面通过第二掺杂形成水平间隔设置的两上部扩散区，且所述上部扩散区与所述下部扩散区在上下方向上间隔设置；
其中，两所述上部扩散区的边缘区域开有沟槽；
所述硅片衬底上表面于两所述上部扩散区的周边区域以及所述沟槽的表面覆盖有一层多晶硅钝化复合薄膜层；所述沟槽中还填充有玻璃胶，并通过高温烧结形成致密的玻璃钝化层；所述下部扩散区以及两所述上部扩散区的表面均沉积有金属层，分别形成金属电极。
上述技术方案中的有关内容解释如下：
1.上述方案中，所述沟槽的深度为20～40um。
2.上述方案中，所述玻璃胶的厚度为25～35μm。
3.上述方案中，两所述上部扩散区之间的距离为200～300um。
4.上述方案中，所述硅片衬底为N型〈111〉晶向，所述第一掺杂为磷杂质掺杂或砷杂质掺杂，所述下部扩散区为N+区，其掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；所述第二掺杂为硼杂质掺杂或镓杂质掺杂，所述上部扩散区为P+区，其掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm。
5.上述方案中，所述硅片衬底为P型〈111〉晶向，所述第一掺杂为硼杂质掺杂或镓杂质掺杂，所述下部扩散区为P+区，其掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；所述第二掺杂为磷杂质掺杂或砷杂质掺杂，所述上部扩散区为N+区，其掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm。
6.上述方案中，所述硅片衬底为N型〈111〉晶向的二极管可作为芯片A，所述硅片衬底为P型〈111〉晶向可作为芯片B，芯片A+B可通过引出组装成为整流桥。
7.上述方案中，所述多晶硅钝化复合薄膜层采用CVD工艺沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷气体和一氧化二氮气体，时间为25±1分钟，其中所述硅烷气体的流速为每分钟130±5ml，所述一氧化二氮气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷气体和一氧化二氮气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层。
本发明的工作原理及优点如下：
本发明一种可并联组合的整流二极管芯片的制造工艺；步骤包括：
一、在硅片衬底下表面通过第一掺杂形成下部扩散区；二、在硅片衬底上、下表面均形成二氧化硅薄膜层；三、刻蚀并去除上表面二氧化硅薄膜层的两间隔区域；四、对两间隔区域进行第二掺杂分别形成上部扩散区，与下部扩散区间隔设置；五、在两上部扩散区的边缘区域开沟槽；六、将硅片衬底上表面的二氧化硅薄膜层去除，清洗并形成多晶硅钝化复合薄膜层；七、在沟槽中形成玻璃钝化层；八、将两上部扩散区表面的多晶硅钝化复合薄膜层去除，裸露出两上部扩散区；同时去除硅片衬底下表面的薄膜层，裸露出下部扩散区；九、在两上部扩散区及下部扩散区的表面沉积金属层形成金属电极。
相比现有技术而言，本发明的优点包括：
一、通过选择性扩散形成U形的PN结，增加了PN结的有效面积，显著降低了二极管在电路中应用时的功耗；
二、采用化学汽相淀积钝化和玻璃钝化结合的方法，减少侧壁的漏电流，提高了器件的可靠性；
三、工艺流程简单，化学品耗用少，正向功耗低，实现了低制造成本高品质的效果；
四、采用20～40um的浅沟槽，加玻璃的二极管PN结钝化设计，可通过两颗不同晶向二极管并联的方式制造出单颗芯片作为半桥直接应用于电路，也可以两颗芯片直接组合为桥堆。
另外，本发明一方面不同于常规平面工艺，常规平面工艺一般只能做到600V，如果需要达到800或1000V以上则需要复杂的工艺，即通过多个分压环来实现，需要更大的芯片面积和复杂的工艺过程，加工成本至少需要加倍才能完成；另一方面也不同于100～140um常规的沟槽工艺，常规的沟槽工艺需要3倍以上的化学品腐蚀深的沟槽，采用大面积的玻璃钝化方法增加了杂质沾污的机会，导致漏电流偏高，同时深的沟槽还会导致硅片翘曲增加过程破片率等问题。
相较传统二极管芯片结构而言，本发明能够做到大幅简化封装，从而能够降低材料费、人工费，有利于降低大批量二极管半导体器件的加工成本，实现最多可降低30％的加工成本，并能够提升单位时间的生产效率。还能减少客户端的使用能耗，更有利于减少资源的浪费(免去对树脂、焊锡、铜引线等材料的消耗)，对环保作出贡献。
附图说明
附图1为本实用新型实施例第一步的原理示意图；
附图2为本实用新型实施例第二步的原理示意图；
附图3为本实用新型实施例第三步的原理示意图；
附图4为本实用新型实施例第四步的原理示意图；
附图5为本实用新型实施例第五步的原理示意图；
附图6为本实用新型实施例第六步的原理示意图；
附图7为本实用新型实施例第七步的原理示意图；
附图8为本实用新型实施例第八步的原理示意图；
附图9为本实用新型实施例第九步的原理示意图；
附图10为本实用新型实施例硅片衬底为P型〈111〉晶向的结构示意图；
附图11为本实用新型实施例两颗不同晶向二极管并联组装为整流桥的示意图。
以上附图中：1.硅片衬底；2.下部扩散区；3.N+区；4.二氧化硅薄膜层；5.间隔区域；6.上部扩散区；7.P+区；8.沟槽；9.多晶硅钝化复合薄膜层；d.距离；10.玻璃钝化层；11.金属层。
具体实施方式
下面结合附图及实施例对本发明作进一步描述：
实施例：参见附图1～9所示，一种可并联组合的整流二极管芯片的制造工艺；选择硅片衬底1，按以下步骤进行操作：
第一步，如图1所示，在所述硅片衬底1下表面通过第一掺杂形成一下部扩散区2；如所述硅片衬底1为N型〈111〉晶向，所述第一掺杂为磷杂质掺杂或砷杂质掺杂，所述下部扩散区2为N+区3，其掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；
所述磷杂质掺杂的工艺条件为：首先在1100℃±0.5℃炉管内，时间为2±0.05小时，气氛为三氯氧磷；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为4±0.05小时，气氛为N 2的条件下进行，从而通过磷原子扩散形成所述N+区3。
第二步，如图2所示，在所述硅片衬底1上表面和下表面均形成一层二氧化硅薄膜层4；其工艺条件为：1150±0.5℃炉管内，先经过30±5分钟的氧气气氛，再经过480±10分钟的水汽气氛，最后再经过30±5分钟的氧气气氛。
第三步，如图3所示，通过光刻胶掩膜硅片衬底1上表面的所述二氧化硅薄膜层4除去两间隔区域5之外的周边区域，并以此光刻胶作为掩膜层，刻蚀并去除裸露的所述二氧化硅薄膜层4上的两所述间隔区域5；
第四步，如图4所示，对两所述间隔区域5进行第二掺杂，从而在两间隔区域5中分别形成一上部扩散区6，两所述上部扩散区6之间的距离为200～300um，且上部扩散区6在上下方向上与所述下部扩散区2间隔设置；所述第二掺杂为硼杂质掺杂或镓杂质掺杂，所述上部扩散区6为P+区7，其掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm；
所述硼杂质掺杂的工艺条件为：首先涂覆液态硼源，在1150±0.5℃炉管内，时间为2±0.05小时，气氛为氮气；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为18±0.05小时，气氛为氮气的条件下进行，从而通过硼原子扩散形成所述P+区7。
第五步，如图5所示，在两所述上部扩散区6的边缘区域开沟槽8，沟槽8的深度为20～40um；
通过沟槽8的开设，一方面可去除所述硅片衬底1表面的损伤层，减少器件的漏电流，另一方面在步骤六多晶硅钝化复合薄膜层9保护下，可减小漏电流以提升可靠性。
第六步，如图6所示，将位于硅片衬底1上表面的所述二氧化硅薄膜层4去除，并对所述硅片衬底1上表面以及所述沟槽8进行清洗，然后形成一层多晶硅钝化复合薄膜层9；所述多晶硅钝化复合薄膜层9采用CVD工艺(化学气相淀积工艺)沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷(SiH 4)气体和一氧化二氮(N 2O)气体，时间为25±1分钟，其中所述硅烷(SiH 4)气体的流速为每分钟130±5ml，所述一氧化二氮(N 2O)气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷(SiH 4)气体和一氧化二氮(N 2O)气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层9。通过上述各项工艺条件，达到符合要求的多晶硅钝化复合薄膜层9的膜厚、成分、晶胞大小、折射率等物理参数。
第七步，如图7所示，在所述沟槽8中的多晶硅钝化复合薄膜层9表面形成一层玻璃钝化层10；
在所述沟槽8中形成所述玻璃钝化层10的工艺条件为：在沟槽8内填充玻璃胶，厚度为25～35μm，然后通过高温烧结形成致密的所述玻璃钝化层10，温度为830±10℃，时间为30±5分钟。
第八步，如图8所示，将两所述上部扩散区6表面的多晶硅钝化复合薄膜层9去除，裸露出两上部扩散区6；同时去除所述硅片衬底1下表面的二氧化硅薄膜层4，裸露出所述下部扩散区2。
第九步，如图9所示，在两所述上部扩散区6以及所述下部扩散区2的表面分别沉积金属层11，形成金属电极。
综上工艺步骤所述，本案于产品层面可按以下方案实施，该方案仅为举例说明之用，不应以此为限：
一种可并联组合的整流二极管芯片，包括一硅片衬底1，所述硅片衬底1的下表面通过第一掺杂形成一下部扩散区2，硅片衬底1的上表面通过第二掺杂形成水平间隔设置的两上部扩散区6，两所述上部扩散区6之间的距离d为200～300um，且所述上部扩散区6与所述下部扩散区2在上下方向上间隔设置；
其中，两所述上部扩散区6的边缘区域开有沟槽8，所述沟槽8的深度为20～40um。
所述硅片衬底1上表面于两所述上部扩散区6的周边区域以及所述沟槽8的表面覆 盖有一层多晶硅钝化复合薄膜层9；所述沟槽8中还填充有玻璃胶，所述玻璃胶的厚度为25～35μm，并通过高温烧结形成致密的玻璃钝化层10；
所述下部扩散区2以及两所述上部扩散区6的表面均沉积有金属层11，分别形成金属电极。
如图1～9所示，所述硅片衬底1为N型〈111〉晶向，所述第一掺杂为磷杂质掺杂或砷杂质掺杂，所述下部扩散区2为N+区3，其掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；所述第二掺杂为硼杂质掺杂或镓杂质掺杂，所述上部扩散区6为P+区7，其掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm。
如图10所示，所述硅片衬底1为P型〈111〉晶向，所述第一掺杂为硼杂质掺杂或镓杂质掺杂，所述下部扩散区2为P+区7，其掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；所述第二掺杂为磷杂质掺杂或砷杂质掺杂，所述上部扩散区6为N+区3，其掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm。
如图11所示，所述硅片衬底1为N型〈111〉晶向的二极管可作为芯片A，所述硅片衬底为P型〈111〉晶向可作为芯片B，芯片A+B可通过引出组装成为整流桥。
其中，所述多晶硅钝化复合薄膜层9采用CVD工艺(化学气相淀积工艺)沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷(SiH 4)气体和一氧化二氮(N 2O)气体，时间为25±1分钟，其中所述硅烷(SiH 4)气体的流速为每分钟130±5ml，所述一氧化二氮(N 2O)气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷(SiH 4)气体和一氧化二氮(N 2O)气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层9。
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (10)

  1. 一种可并联组合的整流二极管芯片的制造工艺；其特征在于：选择硅片衬底，然后按以下步骤进行操作：
    第一步，在所述硅片衬底下表面通过第一掺杂形成一下部扩散区；
    第二步，在所述硅片衬底上表面和下表面均形成一层二氧化硅薄膜层；
    第三步，通过光刻胶掩膜硅片衬底上表面的所述二氧化硅薄膜层除去两间隔区域之外的周边区域，并以此光刻胶作为掩膜层，刻蚀并去除裸露的所述二氧化硅薄膜层上的两所述间隔区域；
    第四步，对两所述间隔区域进行第二掺杂，从而在两间隔区域中分别形成一上部扩散区，所述上部扩散区在上下方向上与所述下部扩散区间隔设置；
    第五步，在两所述上部扩散区的边缘区域开沟槽，沟槽的深度为20～40um；
    第六步，将位于硅片衬底上表面的所述二氧化硅薄膜层去除，并对所述硅片衬底上表面以及所述沟槽进行清洗，然后形成一层多晶硅钝化复合薄膜层；
    第七步，在所述沟槽中的多晶硅钝化复合薄膜层表面形成一层玻璃钝化层；
    第八步，将两所述上部扩散区表面的多晶硅钝化复合薄膜层去除，裸露出两上部扩散区；同时去除所述硅片衬底下表面的薄膜层，裸露出所述下部扩散区；
    第九步，在两所述上部扩散区以及所述下部扩散区的表面分别沉积金属层，形成金属电极。
  2. 根据权利要求1所述的工艺，其特征在于：两所述上部扩散区之间的距离为200～300um。
  3. 根据权利要求1所述的工艺，其特征在于：所述硅片衬底为N型〈111〉晶向，所述第一掺杂为磷杂质掺杂或砷杂质掺杂，所述下部扩散区为N+区，其掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；所述第二掺杂为硼杂质掺杂或镓杂质掺杂，所述上部扩散区为P+区，其掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm。
  4. 根据权利要求1所述的工艺，其特征在于：所述硅片衬底为P型〈111〉晶向，所述第一掺杂为硼杂质掺杂或镓杂质掺杂，所述下部扩散区为P+区，其掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；所述第二掺杂为磷杂质掺杂或砷杂质掺杂，所述上部扩散区为N+区，其掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm。
  5. 根据权利要求1所述的工艺，其特征在于：所述步骤二中，所述二氧化硅薄膜层形成的工艺条件为：1150±0.5℃炉管内，先经过30±5分钟的氧气气氛，再经过480±10分钟的水汽气氛，最后再经过30±5分钟的氧气气氛。
  6. 根据权利要求3或4所述的工艺，其特征在于：所述磷杂质掺杂的工艺条件为：首先在1100℃±0.5℃炉管内，时间为2±0.05小时，气氛为三氯氧磷；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为4±0.05小时，气氛为N 2的条件下进行，从而通过磷原子扩散形成所述N+区。
  7. 根据权利要求3或4所述的工艺，其特征在于：所述硼杂质掺杂的工艺条件为：首先涂覆液态硼源，在1150±0.5℃炉管内，时间为2±0.05小时，气氛为氮气；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为18±0.05小时，气氛为氮气的条件下进行，从而通过硼原子扩散形成所述P+区。
  8. 根据权利要求1所述的工艺，其特征在于：在步骤六中，所述多晶硅钝化复合薄膜层采用CVD工艺沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷气体和一氧化二氮气体，时间为25±1分钟，其中所述硅烷气体的流速为每分钟130±5ml，所述一氧化二氮气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷气体和一氧化二氮气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层。
  9. 根据权利要求1所述的工艺，其特征在于：在步骤七中，在所述沟槽中形成所述玻璃钝化层的工艺条件为：在沟槽内填充玻璃胶，厚度为25～35μm，然后通过高温烧结形成致密的所述玻璃钝化层，温度为830±10℃，时间为30±5分钟。
  10. 一种可并联组合的整流二极管芯片，其特征在于：包括一硅片衬底，所述硅片衬底的下表面通过第一掺杂形成一下部扩散区，硅片衬底的上表面通过第二掺杂形成水平间隔设置的两上部扩散区，且所述上部扩散区与所述下部扩散区在上下方向上间隔设置；
    其中，两所述上部扩散区的边缘区域开有沟槽；
    所述硅片衬底上表面于两所述上部扩散区的周边区域以及所述沟槽的表面覆盖有一层多晶硅钝化复合薄膜层；所述沟槽中还填充有玻璃胶，并通过高温烧结形成致密的玻璃钝化层；
    所述下部扩散区以及两所述上部扩散区的表面均沉积有金属层，分别形成金属电极。
PCT/CN2019/121777 2019-04-30 2019-11-28 一种可并联组合的整流二极管芯片的制造工艺 WO2020220664A1 (zh)

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