CN101604660A - 台型半导体装置及其制造方法 - Google Patents

台型半导体装置及其制造方法 Download PDF

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CN101604660A
CN101604660A CNA200910140669XA CN200910140669A CN101604660A CN 101604660 A CN101604660 A CN 101604660A CN A200910140669X A CNA200910140669X A CN A200910140669XA CN 200910140669 A CN200910140669 A CN 200910140669A CN 101604660 A CN101604660 A CN 101604660A
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semiconductor layer
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CN101604660B (zh
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关克行
土屋尚文
铃木彰
冈田喜久雄
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Niigata Sanyo Electronics Corp
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Abstract

本发明的目的在于谋求高耐压、高可靠度的台型半导体装置及其制造方法的确立，通过使用廉价的材料来解决现有的因相当于PN接合部PNJC的位置的台沟内壁11的第2绝缘膜10的厚度较薄而产生耐压劣化与漏电流的问题。本发明的台型半导体装置，以在台沟5内壁形成由热氧化膜6所构成的稳定的保护膜来被覆保护PN接合部PNJC，并且在台沟5内的氧化膜6所夹的空隙填埋具有负电荷的绝缘膜7以使N－型半导体层2的与热氧化膜6的界面不易形成电子蓄积层。通过采用上述构成，减低热氧化膜6中的正电荷所造成的影响，而确保空乏层往与热氧化层6的界面的N－型半导体层的扩展。

Description

台型半导体装置及其制造方法
技术领域
本发明涉及具有台沟的半导体装置及其制造方法。本申请案中是将具有台沟的半导体装置表示为台型半导体装置。
背景技术
现有技术中，就台型半导体装置的一种类而言，已知有大功率用的台型二极管。兹参照图8及图9说明现有例的台型二极管。图8是显示以矩阵状配置多个现有例的台型二极管的半导体晶圆的概略平面图。图9是沿着图8的X-X线的剖面图，显示沿着切割线(scribe line)DL进行切块(dicing)后的状态。
于N+型半导体基板101的表面形成N-型半导体层102。于N-型半导体层102的表面形成有P型半导体层103，于P型半导体层103上形成有第1绝缘膜105。此外，形成与P型半导体层103电性连接的阳极电极106。
此外，形成有从P型半导体层103的表面到达N+型半导体基板101的台沟108。台沟108形成为比N-型半导体102还深，台沟108的底部位于N+型半导体基板101中。从P型半导体层103的表面至台沟108的底部，台沟108的侧壁具有顺锥形状呈倾斜。台型二极管由该台沟108包围而具有台型的构造。
此外，覆盖台沟108的侧壁而形成有由聚酰亚胺膜构成的第2绝缘膜130，且于N+型半导体基板101的背面形成有阴极电极107。
另外，关于台型的半导体装置，记载于例如下述的专利文献1。
专利文献1：日本特开2003-347306号公报
发明内容
(发明所欲解决的课题)
虽然上述的现有例，显示图9所示的第2绝缘膜130是以均匀的膜厚被覆着台沟108的内壁，但实际上是如图11所示，第2绝缘膜130是以在台沟108内壁的上部薄薄地形成并积存在台沟108的底部的形状来形成。此种形状是以下述的步骤形成。亦即，如图10所示，在进行滴涂(dispense)等而将第2绝缘膜130配置于台沟108时，是以第2绝缘膜130填埋台沟108内，由于在之后的热处理时，进行酰亚胺化反应等，会使第2绝缘膜130的流动性变高，故全体而言第2绝缘膜130会流入台沟108的底部，以致如图11所示，第2绝缘膜130在台沟108内壁的上部薄薄地形成。
故，在相当于电场强度最大的PN接合部PNJC的位置的台沟侧壁110的第2绝缘膜130的膜厚变薄，而引起PN接合的耐压劣化及漏电流的增大，结果即产生良率降低、可靠度降低等必须解决的严重课题。又，就解决上述问题的方法而言，虽然可采取重复若干次形成第2绝缘膜的方法，但其材料费用高，会使得半导体装置的成本提高。
(解决课题的手段)
本发明的台型半导体装置的制造方法含有准备第1导电型的半导体基板，于前述半导体基板的表面形成比前述半导体基板低浓度的第1导电型的第1半导体层的步骤；于前述第1半导体层的表面形成第2导电型的第2半导体层的步骤；以屏蔽层局部性地被覆前述第2半导体层的表面，并形成从前述第2半导体层的表面到达前述半导体基板中的台沟的蚀刻步骤；在前述台沟内及前述第2半导体层上形成氧化膜的步骤；及在前述台沟内的由前述氧化膜所围成的沟内形成有机绝缘膜的步骤。
此外，本发明的台型半导体装置具备：第1导电型的半导体基板；第1导电型的第1半导体层，接合于前述半导体基板的表面且比前述半导体基板低浓度；第2导电型的第2半导体层，接合于前述第1半导体层的表面，与前述第1半导体层共同形成PN接合部；台沟，从前述第2半导体层的表面到达前述半导体基板中；氧化膜，形成在前述第2半导体层上及前述台沟内；及有机绝缘膜，形成在前述台沟内的由前述氧化膜所围成的沟内。
在上述手段中采用以良质的氧化膜被覆台沟内的PN接合部的平面(planar)制备技术，并利用被覆在氧化膜上的具有一定性质的绝缘膜来补强氧化膜的弱点。
(发明的效果)
依据本发明的台型半导体装置及其制造方法，可通过廉价的材料使PN接合部的耐压提升，并且能够谋求漏电流的降低。
附图说明
图1是显示本发明实施形态的台型二极管及其制造方法的剖面图；
图2是显示本发明实施形态的台型二极管及其制造方法的剖面图；
图3是显示本发明实施形态的台型二极管及其制造方法的剖面图；
图4是显示本发明实施形态的台型二极管及其制造方法的剖面图；
图5是显示本发明实施形态的台型二极管及其制造方法的剖面图；
图6是显示本发明实施形态的台型二极管及其制造方法的剖面图；
图7是显示在具有未被绝缘膜填埋的台沟的半导体晶圆上所形成的光阻剂层的涂布不均的平面图；
图8是显示现有例的台型二极管及其制造方法的平面图；
图9是现有例的台型二极管的剖面图；
图10是显示现有例的台型二极管及其制造方法的剖面图；
图11是显示现有例的台型二极管及其制造方法的剖面图；
图12(A)及(B)是显示本发明其它实施形态的台型二极管及其制造方法的剖面图。
【主要元件符号说明】
1、101    N+型半导体基板
2、102    N-型半导体层
3、103    P型半导体层
4、14 光阻剂层
4A、6A、8A 开口部
5、108 台沟
6 热氧化膜
7、105、130 绝缘膜
8、106 阳极电极
9、107 阴极电极
10 钝化膜
11PNJC 部台沟侧壁
12A、12B氧化膜
15涂布不均
16半导体晶圆
DL切割线
PNJC PN接合部
具体实施方式
兹针对本发明实施形态的半导体装置及其制造方法，以台型半导体装置是台型二极管的情形为例进行说明。图1至图5显示本实施形态的台型二极管及其制造方法的剖面图。其中，以下所说明的台型二极管的制造方法是针对以矩阵状配置多个台型二极管的晶圆状半导体基板进行，为了说明上的方便，仅图示晶圆状半导体基板所含有的多个台型二极管的中的1个台型二极管。
如图1所示，准备扩散有高浓度的例如磷等N型杂质的N+型半导体基板1(例如，硅单晶基板)。使半导体层磊晶成长于该N+型半导体基板1的表面而形成低浓度的N型半导体层，亦即N-型半导体层2。另外，上述N+型与N-型的双层结构亦可为进行下述步骤而得，亦即，在从N-型半导体基板的两面将作为杂质的磷等予以热扩散而形成N+层后，进行化学性蚀刻或机械性研磨去除该半导体基板的一面。尤其在为必须具备较厚N-型半导体层2的超高耐压品时，会有以扩散法比以磊晶法来形成的方式为理想的情形。
之后，在N-型半导体层2的表面扩散例如硼等P型杂质而形成P型半导体层3。通过此，于N-型半导体层2与P型半导体层3的界面形成PN接合部PNJC。在上述的构成中，N+型半导体基板1、N-型半导体层2、P型半导体层3的全体厚度例如约200μm左右。
接着，如图2所示，在P型半导体层3上形成具有开口部4A的光阻剂层4，该开口部4A是将预定形成台沟5的区域予以开口。接着，以该光阻剂层4为屏蔽(mask)，贯通P型半导体层3与N-型半导体层2将N+型半导体基板1予以干蚀刻达至其厚度方向的中途的区域，通过此形成台沟5。之后，使用氟酸、硝酸的蚀刻液将因干蚀刻而产生于台沟5侧壁的损伤层(damage layer)去除。蚀刻结束后，以灰化(ashing)法或阻剂剥离液去除作为屏蔽使用的光阻剂层4。
接着，如图3所示，在干O2或湿O2环境的高温炉中，于台沟5侧壁上、P型半导体层3上、N+型半导体基板1上形成厚度数μm以下的热氧化膜6。相当于PN接合部PNJC的位置的台沟侧壁11由该热氧化膜6以可确保耐压的足够厚度所被覆保护，因此可容易解决以聚酰亚胺等填埋台沟5时的覆盖台沟侧壁11的膜厚形成为较薄而无法确保耐压等的问题。本实施形态的台沟5的宽度是10μm以上，因此无法以热氧化膜6填埋台沟5内全体，而形成由形成在台沟5内的热氧化膜6所围成的沟。
此时，在平面型NPN高耐压晶体管中会出现成为问题的一种现象，亦即，会有在氧化膜的界面，于属于集极层的N-型半导体层2形成电子蓄积层，空乏层未足够扩展，在表面发生绝缘崩溃，而无法获得以整体电阻率所决定的绝缘耐压的现象，而在以热氧化膜6被覆台沟5的台型二极管也会有发现该现象的情形。当为平面型晶体管时，从集极表面扩散若干个P+保护环(guard ring)来解决上述问题。而在台型二极管中将P+保护环设置在台沟5内则步骤数是增加，反而失去能够以比平面型低廉地生产的好处。
因此，如图4所示，在台沟5内的由热氧化膜6所围成的沟内及除了之后形成阳极电极8的区域的外的P型半导体层3上的热氧化膜6上形成绝缘膜7。当绝缘膜7由环氧树脂等所构成时，相较于疏水性的硅面直接露出的台沟5的沟内，环氧树脂等比较容易流入亲水性的热氧化膜6所围成的沟内。在热氧化膜6中，若热氧化时于与N-型半导体层2等的界面的氧化膜侧半导体为硅的话则会产生因过剩的硅所造成的阳离子，或者，产生存在于硅与氧化膜的界面的悬键(dangling bond)的界面态(interfacestate)。结果，热氧化膜6整体成为或多或少带有正电荷的状态，若维持这种状态，在与热氧化膜6的界面的N-型半导体层2会蓄积电子，而成为耐压降低的原因。
因此，为了抵消上述正电荷，形成于热氧化膜6上的绝缘膜7可选择带有负电荷的廉价的环氧树脂。与其说由于绝缘膜7隔介热氧化膜6而形成于N-型半导体层2等上，因此绝缘膜7中的负电荷直接对该N-型半导体层2等造成影响，不如说起了减低热氧化膜6的正电荷对N-型半导体层2等的影响的作用。另外，即使绝缘膜7中的负电荷量变多，抵消热氧化膜6的正电荷量且成为以整体而言N-型半导体层2上存在负电荷的形式，只要台沟5内的N-型半导体层2的与热氧化膜6的界面不反转成P型便没有问题。
结果，在N-型半导体层2与热氧化膜6的界面的热氧化膜6的正电荷所造成的N-型半导体层2的电子蓄积减少，空乏层变得容易扩展，因此发生在台沟侧壁11的绝缘崩溃变得不易发生，耐压便能够接近整体电阻率所决定的值。当将由具有负电荷的环氧树脂等所构成的绝缘膜7直接形成于台沟5上时，亦防止在N-型半导体层2的与绝缘膜7的界面的P型反转层所产生的漏电流等的问题。
另外，在本实施形态中，虽然亦将绝缘膜7形成在台沟5以外的部分，但只要填埋比台沟5的相当于PNJC部的位置的台沟侧壁11下部的台沟5的话，便可获得上述效果。惟当未将台沟5以绝缘膜7完全填埋时，形成阳极电极8时等的药液等会残留于台沟5内而引起可靠度方面的问题，且如图7所示产生半导体晶圆16内的光阻剂层14的涂布不均15，造成良率下降，因此较理想为将台沟5完全填埋。
另外，就前述绝缘膜7而言，亦可使用例如所谓的永久阻剂的有机阻剂膜与聚酰亚胺膜、或者无机或有机的SOG(Spin On Glass；旋覆式玻璃)膜、或者氮化硅膜等。
最后，如图5所示，经预定的微影步骤而在热氧化膜6形成用以进行P型半导体层与后述的阳极电极8的接触的开口部6A。此时亦去除形成于N+型半导体基板侧1的热氧化膜6。之后，通过溅镀法或蒸镀法将铝等导电材料形成在P型半导体层3上等，再经预定的步骤而形成阳极电极8，并在N+型半导体基板1上形成阴极电极9，通过此便完成以简便且具稳定性的热氧化膜6及由廉价的环氧树脂等所等所构成的绝缘膜7来填埋台沟5的台型二极管。
另外，如图6所示，依需要而将以电浆CVD法制得的氮化膜所构成的钝化(passivation)膜10以在阳极电极8上具有开口部8A的状态予以形成，能够有效地谋求可靠度的提升。当如前述仅在台沟5内填埋绝缘膜7而达成初期目的时，将钝化膜10亦形成为比台沟5的宽度稍微大的宽度，通过此，可阻止绝缘膜7中的负电荷量的变化，而能够获得可靠度高的台型二极管。
以下，参照图12(A)及图12(B)说明本发明的其它实施形态。又，其它实施形态的特征是在于仅以氧化膜填埋台沟5内。
首先，图12(A)所示构成与图6所示构成的相异点，是在以前述热氧化膜6、及CVD法所制作的氧化膜12A完全填埋在台沟5内的状态下，在该等膜的上形成前述绝缘膜7的点。其它的构成则与图6相同。
再者，图12(B)所示构成与图6所示构成的相异点，是在仅以由CVD法所制作的氧化膜12B完全填埋在台沟5内的状态下，在其上形成前述绝缘膜7的点。其它构成则与图6相同。
在本实施形态中，以台沟5深度约100μm、台沟5宽度约10μm为例加以说明，惟前述台沟5的深度、宽度尺寸可做种种变更，且对应各种尺寸形成在台沟内的氧化膜的构成可做变更。亦即，对于比前述宽度尺寸小的台沟要形成氧化膜时，亦可仅以热氧化膜完全填埋在台沟5内，以取代图12(B)所示的氧化膜12B，而可建构更简便的工艺，例如，宽度尺寸若在5μm以下，则可仅以热氧化膜填埋。此种情况时，为了确保台型二极管的超高耐压、低漏电流特性，而为了将热氧化膜6的成长速度减缓以谋求减少氧化膜中的因过剩的硅所造成的正电荷，并且依需要而减少产生于N-型半导体层2与热氧化膜6的界面的悬键亦可通过采用氢退火等，来使热氧化膜所具有的正电荷量减少。另外，虽以台型二极管为一例来说明本发明，但本发明亦可广泛应用于台型晶体管等其它台型半导体装置。

Claims (8)

1.一种台型半导体装置的制造方法，其特征在于含有：
准备第1导电型的半导体基板，
于前述半导体基板的表面形成比前述半导体基板低浓度的第1导电型的第1半导体层的步骤；
于前述第1半导体层的表面形成第2导电型的第2半导体层的步骤；
以屏蔽层局部性地被覆前述第2半导体层的表面，并形成从前述第2半导体层的表面到达前述半导体基板中的台沟的蚀刻步骤；
在前述台沟内及前述第2半导体层上形成氧化膜的步骤；及
在由前述台沟内的前述氧化膜所围成的沟内形成有机绝缘膜的步骤。
2.一种台型半导体装置的制造方法，其特征在于含有：
准备第1导电型的半导体基板，
于前述半导体基板的表面形成比前述半导体基板低浓度的第1导电型的第1半导体层的步骤；
于前述第1半导体层的表面形成第2导电型的第2半导体层的步骤；
以屏蔽层局部性地被覆前述第2半导体层的表面，并形成从前述第2半导体层的表面到达前述半导体基板中的台沟的蚀刻步骤；及
以埋设于前述台沟内的方式形成氧化膜的步骤。
3.如权利要求2的台型半导体装置的制造方法，其特征在于，含有在前述氧化膜上形成有机绝缘膜的步骤。
4.如权利要求1或3所述的台型半导体装置的制造方法，其特征在于，前述有机绝缘膜是有机阻剂、环氧树脂。
5.一种台型半导体装置，其特征在于具备：
第1导电型的半导体基板；
第1导电型的第1半导体层，接合于前述半导体基板的表面且比前述半导体基板低浓度；
第2导电型的第2半导体层，接合于前述第1半导体层的表面，与前述第1半导体层共同形成PN接合部；
台沟，从前述第2半导体层的表面到达前述半导体基板中；
氧化膜，形成在前述第2半导体层上及前述台沟内；及
有机绝缘膜，形成在前述台沟内的由前述氧化膜所围成的沟内。
6.一种台型半导体装置，其特征在于具备：
第1导电型的半导体基板；
第1导电型的第1半导体层，接合于前述半导体基板的表面且比前述半导体基板低浓度；
第2导电型的第2半导体层，接合于前述第1半导体层的表面，与前述第1半导体层共同形成PN接合部；
台沟，从前述第2半导体层的表面到达前述半导体基板中；及
氧化膜，埋设于前述台沟内。
7.如权利要求6所述的台型半导体装置，其特征在于，在前述氧化膜上具备有机绝缘膜。
8.如权利要求5或7所述的台型半导体装置，其特征在于，前述有机绝缘膜是由有机阻剂、环氧树脂所构成。
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Applicant before: Sanyo Electric Co., Ltd.

Co-applicant before: Sanyo Semiconductor Co., Ltd.

Co-applicant before: Sanyo Semiconductor Manufacturing Co., Ltd.

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Granted publication date: 20141203

Termination date: 20210612

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