WO2020220666A1 - 一种浅沟槽的电极同侧二极管芯片的制造工艺 - Google Patents

一种浅沟槽的电极同侧二极管芯片的制造工艺 Download PDF

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WO2020220666A1
WO2020220666A1 PCT/CN2019/121779 CN2019121779W WO2020220666A1 WO 2020220666 A1 WO2020220666 A1 WO 2020220666A1 CN 2019121779 W CN2019121779 W CN 2019121779W WO 2020220666 A1 WO2020220666 A1 WO 2020220666A1
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region
film layer
trench
area
silicon wafer
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French (fr)
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吴念博
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苏州固锝电子股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66128—Planar diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes

Definitions

  • the invention relates to a diode manufacturing process, in particular to a manufacturing process of a diode chip on the same side of the electrode of a shallow trench.
  • Diodes are widely used in various circuits. It can be said that there are diodes wherever there is a circuit, using its unidirectional characteristic to convert alternating current into direct current, so that the terminal parts of the circuit can obtain stable direct current input.
  • the existing manufacturing method of the rectifier diode is based on the N-type ⁇ 111> crystal orientation monocrystalline silicon wafer. The upper surface of the silicon wafer is doped with boron once to form a flat P region, and then the lower surface is formed by a phosphorus diffusion. The flat N area is then subjected to processes such as photolithography, metallization, and alloying, and finally the PN structure and electrode metal of the diode are formed to make a rectifier diode chip (also known as a "die” in the industry).
  • the PN junction is formed by the process of diffusion on both sides of the chip, it is not conducive to the miniaturization of the product;
  • the purpose of the present invention is to provide a manufacturing process of a diode chip on the same side of the electrode of the shallow trench.
  • a manufacturing process for a diode chip on the same side of the electrode of a shallow trench select a silicon wafer substrate, and then perform the following steps:
  • a first silicon dioxide film layer is formed on the upper surface of the silicon wafer substrate
  • the peripheral area of the first silicon dioxide film layer is masked by photoresist, and the photoresist is used as a mask layer to etch and remove the exposed first silicon dioxide film layer.
  • the first impurity is doped, and the first region is first doped on the upper surface of the silicon wafer substrate, thereby forming an N+ region in the first region.
  • the doping concentration of the N+ region surface is at least 10 21 atm/cm 3 , the diffusion depth is 30 ⁇ 50 ⁇ m;
  • the first silicon dioxide film layer is removed, and the upper surface of the silicon wafer substrate is cleaned, and then a second silicon dioxide film layer is formed;
  • the fifth step is to mask the peripheral area of the second silicon dioxide film layer with photoresist, and use the photoresist as a mask layer to etch and remove the exposed second silicon dioxide film layer.
  • a second area, and the second area is spaced apart from the first area;
  • the second impurity is doped.
  • the second region is doped on the upper surface of the silicon wafer substrate to form a P+ region in the second region.
  • the doping concentration of the P+ region surface is at least 10 21 atm/cm 3 , the diffusion depth is 50 ⁇ 70 ⁇ m;
  • a trench is formed in the edge area of the N+ region or the P+ region, and the depth of the trench is 20-40um;
  • the second silicon dioxide film layer is removed, and the upper surface of the silicon wafer substrate and the trench are cleaned, and then a polysilicon passivation composite film layer is formed;
  • a glass passivation layer is formed on the surface of the polysilicon passivation composite film layer in the trench;
  • the tenth step is to remove the polysilicon passivation composite film layer on the surface of the first region and the second region, and expose the N+ region and the P+ region;
  • a metal layer is deposited on the surfaces of the N+ region and the P+ region to form a metal electrode.
  • the first impurity doping is phosphorus impurity doping or arsenic impurity doping
  • the second impurity doping is boron impurity doping or gallium impurity doping
  • the silicon wafer substrate has an N-type ⁇ 111> crystal orientation, and the trench is opened in the edge area of the P+ region;
  • the silicon wafer substrate has a P-type ⁇ 111> crystal orientation, and the trench is opened in the edge region of the N+ region.
  • the distance between the P+ zone and the N+ zone is 200-300um.
  • the first area and the second area are arranged at intervals along a straight line in the horizontal direction, forming the N+ area and the P+ area in parallel and arranged at intervals in the horizontal direction;
  • the first area and the second area are arranged at intervals in the horizontal direction—inside and outside, so that one of the N+ zone and the P+ zone is surrounded by the other in the horizontal direction.
  • the process conditions for the formation of the first silicon dioxide film layer are: in the furnace tube at 1150 ⁇ 0.5°C, first pass through an oxygen atmosphere for 30 ⁇ 5 minutes, and then pass through 480 ⁇ 10 minutes The atmosphere of water vapor, and finally an oxygen atmosphere of 30 ⁇ 5 minutes.
  • the process conditions of phosphorus impurity doping are: first in the furnace tube at 1100°C ⁇ 0.5°C, the time is 2 ⁇ 0.05 hours, the atmosphere is phosphorus oxychloride; after the furnace is soaked in hydrogen fluoride Acidic acid for 30 ⁇ 5 minutes, then, in a furnace tube at 1250 ⁇ 0.5°C for 4 ⁇ 0.05 hours, and the atmosphere is N 2 to form the N+ zone in the first zone through phosphorus atom diffusion.
  • the process conditions for the boron impurity doping in the step six are as follows: firstly, a liquid boron source is coated on the surface of the second region on the same side as the N+ region and heated at 1150 ⁇ 0.5°C. In the tube, the time is 2 ⁇ 0.05 hours, and the atmosphere is nitrogen; after the furnace is soaked in hydrofluoric acid for 30 ⁇ 5 minutes, then, in the 1250 ⁇ 0.5°C furnace tube, the time is 18 ⁇ 0.05 hours, and the atmosphere is nitrogen.
  • the P+ region is formed in the second region by diffusion of boron atoms.
  • step 8 the polysilicon passivation composite thin film layer is deposited and formed by a CVD process.
  • the process conditions are as follows: First, pass silane gas and nitrous oxide at a temperature of 650 ⁇ 1°C Gas, the time is 25 ⁇ 1 minutes, wherein the flow rate of the silane gas is 130 ⁇ 5ml per minute, and the flow rate of the nitrous oxide gas is 30 ⁇ 2ml per minute; then, under the temperature condition of 780 ⁇ 1°C Continue to pass silane gas and nitrous oxide gas for 15 ⁇ 0.5 minutes, and the flow rates of the two gases are 25 ⁇ 5ml per minute for SiH 4 and 80 ⁇ 5ml per minute for N 2 O; finally a layer containing oxygen is formed The polysilicon passivation composite film layer of a polysilicon passivation film and a silicon dioxide film.
  • step 9 the process conditions for forming the glass passivation layer in the trench are: filling the trench with glass paste with a thickness of 25-35 ⁇ m, and then sintering at high temperature to form a dense
  • the glass passivation layer has a temperature of 830 ⁇ 10°C and a time of 30 ⁇ 5 minutes.
  • the lower surfaces of the N+ region and the P+ region are both arc-shaped, and the PN junction is U-shaped to increase the effective area.
  • a diode chip with a shallow trench on the same side of the electrode comprising a silicon wafer substrate, the upper surface of the silicon wafer substrate is doped with a first impurity to form an N+ region, and a second impurity doped to form a P+ region And the N+ region and the P+ region are spaced apart; the doping concentration on the surface of the N+ region is at least 10 21 atm/cm 3 , and the diffusion depth is 30-50 ⁇ m; the doping concentration on the surface of the P+ region is at least 10 21 atm/cm 3 , The diffusion depth is 50 ⁇ 70 ⁇ m;
  • a trench is opened at the edge area of the N+ region or the P+ region, and the depth of the trench is 20-40um;
  • the upper surface of the silicon wafer substrate is covered with a polysilicon passivation composite film layer on the peripheral area of the N+ region and the P+ region and the surface of the trench; the trench is also filled with glass glue, which The thickness is 25 ⁇ 35 ⁇ m, and the dense glass passivation layer is formed by high temperature sintering;
  • a metal layer is deposited on the surface of the N+ region and the P+ region to form a metal electrode.
  • the first impurity doping is phosphorus impurity doping or arsenic impurity doping
  • the second impurity doping is boron impurity doping or gallium impurity doping
  • the silicon wafer substrate has an N-type ⁇ 111> crystal orientation, and the trench is opened in the edge area of the P+ region;
  • the silicon wafer substrate has a P-type ⁇ 111> crystal orientation, and the trench is opened in the edge region of the N+ region. 3.
  • the distance between the P+ zone and the N+ zone is 200-300um.
  • the N+ zone and the P+ zone are arranged side by side and spaced in the horizontal direction;
  • one of the N+ zone and the P+ zone is surrounded by the other in the horizontal direction, in a "back" shape.
  • the P+ zone can be surrounded by the N+ zone, or under certain application requirements, it can be designed such that the N+ zone can be surrounded by the P+ zone.
  • a manufacturing process of a diode on the same side of the shallow trench electrode of the present invention is as follows:
  • a first silicon dioxide film layer is formed on the upper surface of the silicon wafer substrate; 2. A first region of the first silicon dioxide film layer is etched and removed; 3. The first region is first doped to form In the N+ zone, the doping concentration on the surface is at least 10 21 atm/cm 3 , and the diffusion depth is 30-50 ⁇ m; 4. The first silicon dioxide film layer is removed, and a second silicon dioxide film layer is formed after cleaning; 5. Etch and remove a second region of the second silicon dioxide film layer, the second region is spaced apart from the first region; 6.
  • the second region is doped secondly to form a P+ region, and the doping concentration on the surface is at least 10 21 atm/cm 3 , the diffusion depth is 50 ⁇ 70 ⁇ m; Seven, trenches are formed in the edge area of the N+ zone or P+ zone, the depth is 20-40um; 8.
  • the second silicon dioxide film layer is removed, and the silicon wafer The upper surface of the substrate and the trench are cleaned and a polysilicon passivation composite film layer is formed; 9.
  • a glass passivation layer is formed on the surface of the polysilicon passivation composite film layer in the trench; 10.
  • the polysilicon passivation composite film layer on the surface of the second area is removed, and the N+ area and the P+ area are exposed; eleven, a metal layer is deposited on the surface of the N+ area and the P+ area to form a metal electrode.
  • the advantages of the present invention include:
  • the N+ area and the P+ area are located on the same surface of the silicon wafer substrate, and the PN junction is formed by the process of diffusion on the same surface of the chip, which is conducive to the miniaturization of the product and ensures the quality of high reliability;
  • the U-shaped PN junction is formed through selective diffusion, which increases the effective area of the PN junction and significantly reduces the power consumption of the diode when it is used in the circuit;
  • the process has a wide range of applications, which can be applied to ordinary rectifier diodes, fast recovery diodes, TVS protection diodes, voltage regulator tubes, etc.
  • the present invention is different from the conventional planar process on the one hand.
  • the conventional planar process can generally only achieve 600V. If it needs to reach 800 or more than 1000V, a complicated process is required, that is, it is realized by multiple voltage divider rings, and a larger chip is required. Area and complex process, the processing cost needs to be at least doubled to complete; on the other hand, it is different from the conventional trench process of 100-140um.
  • the conventional trench process requires more than 3 times the chemical corrosion of the deep trench.
  • the area of the glass passivation method increases the chance of contamination by impurities, resulting in high leakage current.
  • deep trenches can also cause problems such as warpage of the silicon wafer and increased process fragmentation rate.
  • the present invention can greatly simplify the packaging, thereby reducing material costs and labor costs, which is beneficial to reduce the processing cost of large-scale diode semiconductor devices, and realizes that the processing cost can be reduced by up to 30%, and Can improve the production efficiency per unit time. It can also reduce the energy consumption of the client, which is more conducive to reducing the waste of resources (eliminating the consumption of resin, solder, copper leads and other materials), and contributes to environmental protection.
  • Figure 1 is a schematic diagram of the first step of the embodiment of the utility model
  • Figure 2 is a schematic diagram of the principle of the second step of the embodiment of the utility model
  • Figure 3 is a schematic diagram of the principle of the third step of the embodiment of the utility model
  • Figure 4 is a schematic diagram of the principle of the fourth step of the embodiment of the utility model
  • Figure 5 is a schematic diagram of the fifth step of the embodiment of the utility model
  • Figure 6 is a schematic diagram of the principle of the sixth step of the embodiment of the utility model
  • Fig. 7 is a schematic diagram of the principle of the seventh step of the embodiment of the utility model.
  • Figure 8 is a schematic diagram of the principle of the eighth step of the embodiment of the utility model.
  • Fig. 9 is a schematic diagram of the principle of the ninth step of the embodiment of the utility model.
  • Figure 10 is a schematic diagram of the principle of the tenth step of the embodiment of the utility model
  • Figure 11 is a schematic diagram of the principle of the eleventh step of the embodiment of the utility model.
  • Figure 12 is a schematic diagram of the parallel arrangement of the N+ area and the P+ area in the embodiment of the present invention.
  • Fig. 13 is a schematic diagram of the surrounding arrangement of the N+ area and the P+ area in the embodiment of the present invention.
  • Embodiment Refer to Figures 1 to 11, a manufacturing process for a diode chip on the same side of the electrode of a shallow trench; firstly select a silicon wafer substrate 1, and the silicon wafer substrate 1 can choose an N-type ⁇ 111> crystal orientation Or P-type ⁇ 111> crystal orientation, this embodiment takes N-type ⁇ 111> crystal orientation as an example, and then follow the steps below:
  • a first silicon dioxide film layer 2 is formed on the upper surface of the silicon wafer substrate 1; the process conditions for forming the first silicon dioxide film layer 2 are: 1150 ⁇ In the 0.5°C furnace tube, first go through an oxygen (O 2 ) atmosphere for 30 ⁇ 5 minutes, then go through a water vapor (H 2 O) atmosphere for 480 ⁇ 10 minutes, and finally go through an oxygen (O 2 ) atmosphere for 30 ⁇ 5 minutes.
  • the peripheral area of the first silicon dioxide film layer 2 is masked by photoresist, and the photoresist is used as a mask layer to etch and remove the exposed first silicon dioxide layer.
  • the first impurity doping may be phosphorus impurity doping (or arsenic impurity doping), by aligning the upper surface of the silicon wafer substrate 1
  • the first region 3 is doped with phosphorus, so that an N+ region 10 is formed in the first region 3.
  • the doping concentration on the surface of the N+ region 10 is at least 10 21 atm/cm 3 , and the diffusion depth is 30-50 ⁇ m;
  • the miscellaneous process conditions are: first in the furnace tube at 1100°C ⁇ 0.5°C, the time is 2 ⁇ 0.05 hours, the atmosphere is phosphorous oxychloride (POCl 3 ); after the furnace is soaked in hydrofluoric acid (HF) for 30 ⁇ 5 minutes, then, In the furnace tube at 1250 ⁇ 0.5° C., the time is 4 ⁇ 0.05 hours and the atmosphere is N 2 , so that the N+ zone 10 is formed in the first zone 3 through phosphorus atom diffusion.
  • HF hydrofluoric acid
  • the first silicon dioxide film layer 2 is removed, and the upper surface of the silicon wafer substrate 1 is cleaned, and then a second silicon dioxide film layer 4 is formed.
  • the peripheral area of the second silicon dioxide film layer 4 is masked by photoresist, and the photoresist is used as a mask layer to etch and remove the exposed second silicon dioxide film layer.
  • a second area 5 of the two silicon dioxide film layer 4, and the second area 5 and the first area 3 are spaced apart.
  • the second impurity doping may be boron impurity doping (or gallium impurity doping), and the upper surface of the silicon wafer substrate 1
  • the second region 5 is doped with boron, thereby forming a P+ region 11 in the second region 5.
  • the doping concentration on the surface of the P+ region 11 is at least 10 21 atm/cm 3 , and the diffusion depth is 50-70 ⁇ m;
  • the miscellaneous process conditions are: first coat the surface of the second region 5 on the same side as the N+ zone 10 with a liquid boron source, in a furnace tube of 1150 ⁇ 0.5°C for 2 ⁇ 0.05 hours, and the atmosphere is nitrogen ( N 2 ); After the furnace is soaked in hydrofluoric acid (HF) for 30 ⁇ 5 minutes, then, in the 1250 ⁇ 0.5 °C furnace tube, the time is 18 ⁇ 0.05 hours, and the atmosphere is nitrogen (N 2 ).
  • the second region 5 forms the P+ region 11 through the diffusion of boron atoms.
  • a trench 6 is opened in the edge area of the P+ region 11 (if the silicon wafer substrate has a P-type ⁇ 111> crystal orientation, the trench is opened in the N+ The edge area of the region), thereby exposing the PN junction on the upper surface of the silicon wafer substrate 1 to form a diode device region, and the depth of the trench 6 is 20-40um;
  • the damaged layer on the surface of the silicon wafer substrate 1 can be removed and the leakage current of the device can be reduced.
  • the PN junction exposed on the surface of the silicon wafer can be recessed downward. Under the protection of the polysilicon passivation composite film layer 7 in the ninth step, the leakage current on the surface of the device is reduced to improve reliability.
  • the second silicon dioxide film layer 4 is removed, and the upper surface of the silicon wafer substrate 1 and the trench 6 are cleaned, and then a layer of polysilicon passivation is formed Composite film layer 7;
  • the polysilicon passivation composite thin film layer 7 is deposited and formed by a CVD process (chemical vapor deposition process), and the process conditions are as follows: firstly, pass silane (SiH 4 ) gas and two oxides at a temperature of 650 ⁇ 1°C.
  • Nitrogen (N 2 O) gas the time is 25 ⁇ 1 minute, wherein the flow rate of the silane (SiH 4 ) gas is 130 ⁇ 5 ml per minute, and the flow rate of the nitrous oxide (N 2 O) gas is per minute 30 ⁇ 2ml; then, continue to pass silane (SiH 4 ) gas and nitrous oxide (N 2 O) gas under the temperature condition of 780 ⁇ 1°C for 15 ⁇ 0.5 minutes, and the flow rates of the two gases are respectively SiH 4 is 25 ⁇ 5 ml per minute and N 2 O is 80 ⁇ 5 ml per minute; finally, a layer of the polysilicon passivation composite film layer 7 containing an oxygen-containing polysilicon passivation film and a silicon dioxide film is formed.
  • physical parameters such as the film thickness, composition, unit cell size, and refractive index of the polysilicon passivation composite thin film layer 7 that meet the requirements are achieved.
  • a glass passivation layer 8 is formed on the surface of the polysilicon passivation composite film layer 7 in the trench 6;
  • the process conditions for forming the glass passivation layer 8 in the trench 6 are: filling the trench 6 with glass paste with a thickness of 25-35 ⁇ m, and then forming a dense glass passivation layer 8 through high temperature sintering.
  • the temperature is 830 ⁇ 10°C, and the time is 30 ⁇ 5 minutes.
  • the tenth step as shown in FIG. 10, remove the polysilicon passivation composite film layer 7 on the surfaces of the first region 3 and the second region 5 of the diode device region, and expose the N+ region and the The P+ area.
  • a metal layer 9 is deposited on the surfaces of the N+ region 10 and the P+ region 11 to form a metal electrode.
  • the distance d between the P+ region 11 and the N+ region 10 is 200-300um.
  • the reason for choosing this distance parameter is that the design of the distance between the P+ zone 11 and the N+ zone 10 must ensure a certain range. When an electric field is applied, the space charge zone of the diode PN junction will expand, and the distance between the P+ zone 11 and the N+ zone 10 Too close will result in insufficient expansion of the space charge region, and the diode will break down in advance and fail to meet the design voltage requirements. If it is too wide, it will lead to an increase in size and waste of materials.
  • the first area 3 and the second area 5 may be arranged at intervals along a straight line in the horizontal direction to form the N+ zone 10 and the P+ zone 11 arranged side by side at intervals in the horizontal direction; or, as As shown in FIG. 13, the first area 3 and the second area 5 are arranged at intervals in the horizontal direction—inside and outside—to form the N+ zone 10 and the P+ zone 11 in the horizontal direction.
  • One is surrounded by the other.
  • the P+ area 11 can be surrounded by the N+ area 10, or under certain application requirements, it can be designed such that the N+ area 10 can be surrounded by the P+ area 11.
  • a diode chip with a shallow trench on the same side of the electrode includes a silicon wafer substrate 1.
  • the upper surface of the silicon wafer substrate 1 is doped with phosphorus impurities to form N+ regions 10, and boron impurities are doped to form P+ regions.
  • Region 11, and the N+ region 10 and the P+ region 11 are spaced apart;
  • the doping concentration on the surface of the N+ region 10 is at least 10 21 atm/cm 3 , and the diffusion depth is 30-50 ⁇ m;
  • the doping concentration on the surface of the P+ region 11 is at least 10 21 atm/cm 3 , the diffusion depth is 50 ⁇ 70 ⁇ m;
  • a trench 6 is opened at the edge area of the P+ region 11, and the depth of the trench 6 is 20-40um;
  • the upper surface of the silicon wafer substrate 1 is covered with a polysilicon passivation composite film layer 7 on the peripheral area of the N+ region 10 and the P+ region 11 and the surface of the trench 6; Filled with glass glue, the thickness of which is 25 ⁇ 35 ⁇ m, and the dense glass passivation layer 8 is formed by high temperature sintering;
  • a metal layer 9 is deposited on the surfaces of the N+ region 10 and the P+ region 11 to form a metal electrode.
  • the polysilicon passivation composite thin film layer 5 is deposited and formed by a CVD process (chemical vapor deposition process), and the process conditions are as follows: firstly, pass silane gas and nitrous oxide gas at a temperature of 650 ⁇ 1°C , The time is 25 ⁇ 1 minutes, wherein the flow rate of the silane gas is 130 ⁇ 5ml per minute, and the flow rate of the nitrous oxide gas is 30 ⁇ 2ml per minute; then, continue under the temperature condition of 780 ⁇ 1°C Inject silane gas and nitrous oxide gas for 15 ⁇ 0.5 minutes, and the flow rates of the two gases are 25 ⁇ 5ml per minute for SiH 4 and 80 ⁇ 5ml per minute for N 2 O; finally a layer of oxygen-containing polysilicon is formed The polysilicon passivation composite film layer 5 of a passivation film and a silicon dioxide film.
  • CVD process chemical vapor deposition process

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Abstract

一种浅沟槽的电极同侧二极管芯片的制造工艺，步骤包括：在硅片衬底（1）表面形成第一二氧化硅薄膜层（2）；刻蚀并去除第一二氧化硅薄膜层（2）的一第一区域（3）；对第一区域（3）进行第一掺杂形成N+区（10）；将第一二氧化硅薄膜层（2）去除，清洗后形成第二二氧化硅薄膜层（4）；刻蚀并去除第二二氧化硅薄膜层（4）的一第二区域（5），与第一区域（3）间隔设置；对第二区域（5）进行第二掺杂形成P+区（11）；在N+区（10）或P+区（11）的边缘区域开沟槽（6）；将第二二氧化硅薄膜层（4）去除，清洗并形成多晶硅钝化复合薄膜层（7）；在沟槽（6）中形成玻璃钝化层（8）；将第一、第二区域（3、5）表面的多晶硅钝化复合薄膜层（7）去除，裸露N+区（10）及P+区（11）；在N+区（10）及P+区（11）的表面沉积金属层（9）形成金属电极。所述二极管芯片的电极同侧，体积小成本低且电性能优异。

Description

一种浅沟槽的电极同侧二极管芯片的制造工艺 技术领域
本发明涉及一种二极管制造工艺，具体涉及一种浅沟槽的电极同侧二极管芯片的制造工艺。
背景技术
二极管广泛应用在各种电路中，可以说凡有电路处皆有二级管，利用其单向导通的特性把交流电转化为直流电，使电路的终端部件可以获得稳定的直流电输入。现有整流二极管的制造方法是以N型〈111〉晶向单晶硅片为基本材料，在该硅片的上表面进行一次硼掺杂形成平的P区，然后在下表面进行一次磷扩散形成平的N区，然后再进行光刻、金属化、合金等工序，最终形成二极管的PN结构和电极金属，制成整流二极管芯片(业界亦称“晶粒”)。
现有技术的不足包括：
一、由于采用芯片两面扩散的工艺形成PN结，不利于产品的小型化；
二、芯片两面都有电极和引线框架，进一步增加了厚度，并增加了电路连接工艺的复杂程度，而且在后续的封装工序中，芯片不能与外侧散热片直接接触，散热效果也会受到影响；
三、上述现有二极管在工作的过程中，反向截止，正向导通，在正向电流导通过程中由于其自身的正向压降存在，二极管会不断发热，P＝U*I(这里U是正向压降，I是代表正常工作的电流)。二极管发热的这部分功耗不但由于持续的发热而影响器件的可靠性和使用寿命，而且消耗大量无谓的能量，这和目前绿色节能的环保要求显得格格不入。
因此，如何解决上述现有技术存在的不足，便成为本发明所要研究解决的课题。
发明内容
本发明的目的是提供一种浅沟槽的电极同侧二极管芯片的制造工艺。
为达到上述目的，本发明采用的技术方案是：
一种浅沟槽的电极同侧二极管芯片的制造工艺；选择硅片衬底，然后按以下步骤进行操作：
第一步，在所述硅片衬底上表面形成一层第一二氧化硅薄膜层；
第二步，通过光刻胶掩膜所述第一二氧化硅薄膜层的周边区域，并以此光刻胶作为掩膜层，刻蚀并去除裸露的所述第一二氧化硅薄膜层的一第一区域；
第三步，第一杂质掺杂，在所述硅片衬底上表面对所述第一区域进行第一掺杂，从而在此第一区域形成N+区，该N+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；
第四步，将所述第一二氧化硅薄膜层去除，并对所述硅片衬底上表面进行清洗，然后形成一层第二二氧化硅薄膜层；
第五步，通过光刻胶掩膜所述第二二氧化硅薄膜层的周边区域，并以此光刻胶作为掩膜层， 刻蚀并去除裸露的所述第二二氧化硅薄膜层的一第二区域，且该第二区域与所述第一区域间隔设置；
第六步，第二杂质掺杂，在所述硅片衬底上表面对所述第二区域进行第二掺杂，从而在此第二区域形成P+区，该P+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm；
第七步，在所述N+区或所述P+区的边缘区域开沟槽，沟槽的深度为20～40um；
第八步，将所述第二二氧化硅薄膜层去除，并对所述硅片衬底上表面以及所述沟槽进行清洗，然后形成一层多晶硅钝化复合薄膜层；
第九步，在所述沟槽中的多晶硅钝化复合薄膜层表面形成一层玻璃钝化层；
第十步，将所述第一区域以及所述第二区域表面的多晶硅钝化复合薄膜层去除，并裸露出所述N+区以及所述P+区；
第十一步，在所述N+区以及所述P+区的表面均沉积金属层，形成金属电极。
上述技术方案中的有关内容解释如下：
1.上述方案中，所述第一杂质掺杂为磷杂质掺杂或砷杂质掺杂，所述第二杂质掺杂为硼杂质掺杂或镓杂质掺杂。
2.上述方案中，所述硅片衬底为N型〈111〉晶向，所述沟槽开设于所述P+区的边缘区域；
或者，所述硅片衬底为P型〈111〉晶向，所述沟槽开设于所述N+区的边缘区域。
3.上述方案中，所述P+区与所述N+区的距离为200～300um。
4.上述方案中，所述第一区域及所述第二区域在水平方向沿直线间隔设置，构成所述N+区和所述P+区在水平方向并列间隔设置；
或者，所述第一区域及所述第二区域在水平方向一内一外间隔设置，构成所述N+区和所述P+区在水平方向一者被另一者包围。
5.上述方案中，所述步骤一中，所述第一二氧化硅薄膜层形成的工艺条件为：1150±0.5℃炉管内，先经过30±5分钟的氧气气氛，再经过480±10分钟的水汽气氛，最后再经过30±5分钟的氧气气氛。
6.上述方案中，所述步骤三中，磷杂质掺杂的工艺条件为：首先在1100℃±0.5℃炉管内，时间为2±0.05小时，气氛为三氯氧磷；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为4±0.05小时，气氛为N 2的条件下进行，从而在所述第一区域通过磷原子扩散形成所述N+区。
7.上述方案中，所述步骤六中，硼杂质掺杂的工艺条件为：首先在与所述N+区同侧的所述第二区域的表面涂覆液态硼源，在1150±0.5℃炉管内，时间为2±0.05小时，气氛为氮气；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为18±0.05小 时，气氛为氮气的条件下进行，从而在所述第二区域通过硼原子扩散形成所述P+区。
8.上述方案中，在步骤八中，所述多晶硅钝化复合薄膜层采用CVD工艺沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷气体和一氧化二氮气体，时间为25±1分钟，其中所述硅烷气体的流速为每分钟130±5ml，所述一氧化二氮气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷气体和一氧化二氮气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层。
9.上述方案中，在步骤九中，在所述沟槽中形成所述玻璃钝化层的工艺条件为：在沟槽内填充玻璃胶，厚度为25～35μm，然后通过高温烧结形成致密的所述玻璃钝化层，温度为830±10℃，时间为30±5分钟。
10.上述方案中，所述N+区和所述P+区的下表面均呈弧形，PN结呈U形增加了有效面积。
为达到上述目的，本发明采用的另一技术方案是：
一种浅沟槽的电极同侧二极管芯片，包括一硅片衬底，所述硅片衬底的上表面通过第一杂质掺杂形成有N+区，并通过第二杂质掺杂形成有P+区，且N+区与P+区间隔设置；所述N+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；所述P+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm；
其中，所述N+区或所述P+区的边缘区域开有沟槽，该沟槽的深度为20～40um；
所述硅片衬底上表面于所述N+区以及所述P+区的周边区域以及所述沟槽的表面覆盖有一层多晶硅钝化复合薄膜层；所述沟槽中还填充有玻璃胶，其厚度为25～35μm，并通过高温烧结形成致密的玻璃钝化层；
所述N+区以及所述P+区的表面均沉积有金属层，形成金属电极。
上述技术方案中的有关内容解释如下：
1.上述方案中，所述第一杂质掺杂为磷杂质掺杂或砷杂质掺杂，所述第二杂质掺杂为硼杂质掺杂或镓杂质掺杂。
2.上述方案中，所述硅片衬底为N型〈111〉晶向，所述沟槽开设于所述P+区的边缘区域；
或者，所述硅片衬底为P型〈111〉晶向，所述沟槽开设于所述N+区的边缘区域。3.上述方案中，所述P+区与所述N+区的距离为200～300um。
4.上述方案中，所述N+区和所述P+区在水平方向并列间隔设置；
或者，所述N+区和所述P+区在水平方向一者被另一者包围，呈“回”字形。如P+区可被N+区包围，或者在某些使用要求下，可设计为N+区可被P+区包围。
本发明的工作原理及优点如下：
本发明一种浅沟槽的电极同侧二极管制造工艺；按以下步骤操作：
一、在硅片衬底上表面形成第一二氧化硅薄膜层；二、刻蚀并去除第一二氧化硅薄膜层的一第一区域；三、对第一区域进行第一掺杂，形成N+区，表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；四、将第一二氧化硅薄膜层去除，清洗后形成一层第二二氧化硅薄膜层；五、刻蚀并去除第二二氧化硅薄膜层的一第二区域，该第二区域与第一区域间隔设置；六、对第二区域进行第二掺杂，形成P+区，表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm；七、在N+区或P+区的边缘区域开沟槽，深度为20～40um；八、将第二二氧化硅薄膜层去除，对硅片衬底上表面及沟槽进行清洗并形成一层多晶硅钝化复合薄膜层；九、在沟槽中的多晶硅钝化复合薄膜层表面形成一层玻璃钝化层；十、将第一区域及第二区域表面的多晶硅钝化复合薄膜层去除，裸露N+区及P+区；十一、在N+区及P+区的表面沉积金属层形成金属电极。
相比现有技术而言，本发明的优点包括：
一、N+区与P+区位于硅片衬底的同一面，采用芯片同一面扩散的工艺形成PN结，有利于产品的小型化，并可保证高可靠性的品质；
二、无需在芯片两面都设电极和引线框架，降低了电路连接工艺的复杂程度，且在后续的封装工序中，芯片能与外侧散热片直接接触，散热效果大幅提升；
三、结合印刷技术可取消常规的铜引线，大大简化了流程，并节约成本；
四、通过与陶瓷基板贴装后可直接应用于电路，取消了环氧，降低了热阻，提升了散热性能；
五、采用20～40um的浅沟槽，结合多晶硅钝化复合薄膜层加玻璃钝化的方式对PN结进行保护，工艺流程简单，化学品耗用少，正向功耗低，制造成本低但品质高；
六、通过选择性扩散形成U形的PN结，增加了PN结的有效面积，显著降低了二极管在电路中应用时的功耗；
七、工艺适用范围广，可应用于普通的整流二极管、快恢复二极管、TVS保护二极管、稳压管等。
另外，本发明一方面不同于常规平面工艺，常规平面工艺一般只能做到600V，如果需要达到800或1000V以上则需要复杂的工艺，即通过多个分压环来实现，需要更大的芯片面积和复杂的工艺过程，加工成本至少需要加倍才能完成；另一方面也不同于100～140um常规的沟槽工艺，常规的沟槽工艺需要3倍以上的化学品腐蚀深的沟槽，采用大面积的玻璃钝化方法增加了杂质沾污的机会，导致漏电流偏高，同时深的沟槽还会导致硅片翘曲增加过程破片率等问题。
相较传统二极管芯片结构而言，本发明能够做到大幅简化封装，从而能够降低材料费、人工费，有利于降低大批量二极管半导体器件的加工成本，实现最多可降低30％的加工成本，并能够提升单位时间的生产效率。还能减少客户端的使用能耗，更有利于减少资源的浪费(免去对树脂、焊锡、铜引线等材料的消耗)，对环保作出贡献。
附图说明
附图1为本实用新型实施例第一步的原理示意图；
附图2为本实用新型实施例第二步的原理示意图；
附图3为本实用新型实施例第三步的原理示意图；
附图4为本实用新型实施例第四步的原理示意图；
附图5为本实用新型实施例第五步的原理示意图；
附图6为本实用新型实施例第六步的原理示意图；
附图7为本实用新型实施例第七步的原理示意图；
附图8为本实用新型实施例第八步的原理示意图；
附图9为本实用新型实施例第九步的原理示意图；
附图10为本实用新型实施例第十步的原理示意图；
附图11为本实用新型实施例第十一步的原理示意图；
附图12为本实用新型实施例N+区和P+区并列设置的示意图；
附图13为本实用新型实施例N+区和P+区包围设置的示意图。
以上附图中：1.硅片衬底；2.第一二氧化硅薄膜层；3.第一区域；4.第二二氧化硅薄膜层；5.第二区域；6.沟槽；7.多晶硅钝化复合薄膜层；8.玻璃钝化层；9.金属层；d.距离；10.N+区；11.P+区。
具体实施方式
下面结合附图及实施例对本发明作进一步描述：
实施例：参见附图1～11所示，一种浅沟槽的电极同侧二极管芯片的制造工艺；首先选择硅片衬底1，该硅片衬底1可选用N型〈111〉晶向或者P型〈111〉晶向，本实施例以N型〈111〉晶向为例进行说明，然后按以下步骤进行操作：
第一步，如图1所示，在所述硅片衬底1上表面形成一层第一二氧化硅薄膜层2；所述第一二氧化硅薄膜层2形成的工艺条件为：1150±0.5℃炉管内，先经过30±5分钟的氧气(O 2)气氛，再经过480±10分钟的水汽(H 2O)气氛，最后再经过30±5分钟的氧气(O 2)气氛。
第二步，如图2所示，通过光刻胶掩膜所述第一二氧化硅薄膜层2的周边区域，并以此光刻胶作为掩膜层，刻蚀并去除裸露的所述第一二氧化硅薄膜层2的一第一区域3。
第三步，如图3所示，第一杂质掺杂，该第一杂质掺杂可为磷杂质掺杂(也可为砷杂质掺杂)，通过在所述硅片衬底1上表面对所述第一区域3进行磷掺杂，从而在此第一区域3形成N+区10，该N+区10表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；磷杂质掺杂的工艺条件为：首先在1100℃±0.5℃炉管内，时间为2±0.05小时，气氛为三氯氧磷(POCl 3)；出炉后泡氢氟酸(HF)30±5分钟，接着，在1250±0.5℃炉管内，时间为4±0.05小时，气氛为N 2的条件下进行，从而在所述第一区域3通过磷原子扩散形成所述N+区10。
第四步，如图4所示，将所述第一二氧化硅薄膜层2去除，并对所述硅片衬底1上表面进行清洗，然后形成一层第二二氧化硅薄膜层4。
第五步，如图5所示，通过光刻胶掩膜所述第二二氧化硅薄膜层4的周边区域，并以此光刻胶作为掩膜层，刻蚀并去除裸露的所述第二二氧化硅薄膜层4的一第二区域5，且该第二区域5与所述第一区域3间隔设置。
第六步，如图6所示，第二杂质掺杂，该第二杂质掺杂可为硼杂质掺杂(也可为镓杂质掺杂)，通过在所述硅片衬底1上表面对所述第二区域5进行硼掺杂，从而在此第二区域5形成P+区11，该P+区11表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm；硼杂质掺杂的工艺条件为：首先在与所述N+区10同侧的所述第二区域5的表面涂覆液态硼源，在1150±0.5℃炉管内，时间为2±0.05小时，气氛为氮气(N 2)；出炉后泡氢氟酸(HF)30±5分钟，接着，在1250±0.5℃炉管内，时间为18±0.05小时，气氛为氮气(N 2)的条件下进行，从而在所述第二区域5通过硼原子扩散形成所述P+区11。
第七步，如图7所示，在所述P+区11的边缘区域开沟槽6(若所述硅片衬底为P型〈111〉晶向，则所述沟槽开设于所述N+区的边缘区域)，从而在所述硅片衬底1上表面暴露PN结，形成二极管器件区，沟槽6的深度为20～40um；
通过沟槽6的开设，一方面可去除所述硅片衬底1表面的损伤层，减少器件的漏电流，另一方面使暴露在硅片表面的PN结向下凹陷，在第八步和第九步的多晶硅钝化复合薄膜层7保护下，减小器件表面的漏电流以提升可靠性。
第八步，如图8所示，将所述第二二氧化硅薄膜层4去除，并对所述硅片衬底1上表面以及所述沟槽6进行清洗，然后形成一层多晶硅钝化复合薄膜层7；
所述多晶硅钝化复合薄膜层7采用CVD工艺(化学气相淀积工艺)沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷(SiH 4)气体和一氧化二氮(N 2O)气体，时间为25±1分钟，其中所述硅烷(SiH 4)气体的流速为每分钟130±5ml，所述一氧化二氮(N 2O)气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷(SiH 4)气体和一氧化二氮(N 2O)气体，时间为15±0.5分钟，且两种气体的流速分别为 SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层7。通过上述各项工艺条件，达到符合要求的多晶硅钝化复合薄膜层7的膜厚、成分、晶胞大小、折射率等物理参数。
第九步，如图9所示，在所述沟槽6中的多晶硅钝化复合薄膜层7表面形成一层玻璃钝化层8；
在所述沟槽6中形成所述玻璃钝化层8的工艺条件为：在沟槽6内填充玻璃胶，厚度为25～35μm，然后通过高温烧结形成致密的所述玻璃钝化层8，温度为830±10℃，时间为30±5分钟。
第十步，如图10所示，将所述二极管器件区的所述第一区域3以及所述第二区域5表面的多晶硅钝化复合薄膜层7去除，并裸露出所述N+区以及所述P+区。
第十一步，如图11所示，在所述N+区10以及所述P+区11的表面均沉积金属层9，形成金属电极。
其中，所述P+区11与所述N+区10的距离d为200～300um。之所以选择该距离参数，是因为P+区11和N+区10的距离设计必须保证一定的范围，当外加电场时，二极管PN结的空间电荷区会外扩展，P+区11和N+区10的距离太近则导致空间电荷区的展宽不够，二极管会提前击穿而达不到设计的电压要求，如果太宽则导致尺寸的增加和材料的浪费。
如图12所示，所述第一区域3及所述第二区域5可在水平方向沿直线间隔设置，构成所述N+区10和所述P+区11在水平方向并列间隔设置；或者，如图13所示，所述第一区域3及所述第二区域5在水平方向一内一外间隔设置，构成所述N+区10和所述P+区11在水平方向一者被另一者包围，呈“回”字形，如图中所示的P+区11可被N+区10包围，或者在某些使用要求下，可设计为N+区10可被P+区11包围。
综上工艺步骤所述，本案于产品层面可按以下方案实施，该方案仅为举例说明之用，不应以此为限：
一种浅沟槽的电极同侧二极管芯片，包括一硅片衬底1，所述硅片衬底1的上表面通过磷杂质掺杂形成有N+区10，并通过硼杂质掺杂形成有P+区11，且N+区10与P+区11间隔设置；所述N+区10表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；所述P+区11表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm；
其中，所述P+区11的边缘区域开有沟槽6，该沟槽6的深度为20～40um；
所述硅片衬底1上表面于所述N+区10以及所述P+区11的周边区域以及所述沟槽6的表面覆盖有一层多晶硅钝化复合薄膜层7；所述沟槽6中还填充有玻璃胶，其厚度为25～35μm，并通过高温烧结形成致密的玻璃钝化层8；
所述N+区10以及所述P+区11的表面均沉积有金属层9，形成金属电极。
其中，所述多晶硅钝化复合薄膜层5采用CVD工艺(化学气相淀积工艺)沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷气体和一氧化二氮气体，时间为25±1分钟，其中所述硅烷气体的流速为每分钟130±5ml，所述一氧化二氮气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷气体和一氧化二氮气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层5。
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (10)

  1. 一种浅沟槽的电极同侧二极管芯片的制造工艺；其特征在于：选择硅片衬底，然后按以下步骤进行操作：
    第一步，在所述硅片衬底上表面形成一层第一二氧化硅薄膜层；
    第二步，通过光刻胶掩膜所述第一二氧化硅薄膜层的周边区域，并以此光刻胶作为掩膜层，刻蚀并去除裸露的所述第一二氧化硅薄膜层的一第一区域；
    第三步，第一杂质掺杂，在所述硅片衬底上表面对所述第一区域进行第一掺杂，从而在此第一区域形成N+区，该N+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；
    第四步，将所述第一二氧化硅薄膜层去除，并对所述硅片衬底上表面进行清洗，然后形成一层第二二氧化硅薄膜层；
    第五步，通过光刻胶掩膜所述第二二氧化硅薄膜层的周边区域，并以此光刻胶作为掩膜层，刻蚀并去除裸露的所述第二二氧化硅薄膜层的一第二区域，且该第二区域与所述第一区域间隔设置；
    第六步，第二杂质掺杂，在所述硅片衬底上表面对所述第二区域进行第二掺杂，从而在此第二区域形成P+区，该P+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm；
    第七步，在所述N+区或所述P+区的边缘区域开沟槽，沟槽的深度为20～40um；
    第八步，将所述第二二氧化硅薄膜层去除，并对所述硅片衬底上表面以及所述沟槽进行清洗，然后形成一层多晶硅钝化复合薄膜层；
    第九步，在所述沟槽中的多晶硅钝化复合薄膜层表面形成一层玻璃钝化层；
    第十步，将所述第一区域以及所述第二区域表面的多晶硅钝化复合薄膜层去除，并裸露出所述N+区以及所述P+区；
    第十一步，在所述N+区以及所述P+区的表面均沉积金属层，形成金属电极。
  2. 根据权利要求1所述的工艺，其特征在于：所述第一杂质掺杂为磷杂质掺杂或砷杂质掺杂，所述第二杂质掺杂为硼杂质掺杂或镓杂质掺杂。
  3. 根据权利要求1所述的工艺，其特征在于：所述硅片衬底为N型〈111〉晶向，所述沟槽开设于所述P+区的边缘区域；
    或者，所述硅片衬底为P型〈111〉晶向，所述沟槽开设于所述N+区的边缘区域。
  4. 根据权利要求1所述的工艺，其特征在于：所述第一区域及所述第二区域在水平方向沿直线间隔设置，构成所述N+区和所述P+区在水平方向并列间隔设置；
    或者，所述第一区域及所述第二区域在水平方向一内一外间隔设置，构成所述N+区和所述P+区在水平方向一者被另一者包围。
  5. 根据权利要求1所述的工艺，其特征在于：所述步骤一中，所述第一二氧化硅薄膜层形成的工艺条件为：1150±0.5℃炉管内，先经过30±5分钟的氧气气氛，再经过480±10 分钟的水汽气氛，最后再经过30±5分钟的氧气气氛。
  6. 根据权利要求1所述的工艺，其特征在于：所述步骤三中，所述第一杂质掺杂为磷杂质掺杂，该磷杂质掺杂的工艺条件为：首先在1100℃±0.5℃炉管内，时间为2±0.05小时，气氛为三氯氧磷；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为4±0.05小时，气氛为N 2的条件下进行，从而在所述第一区域通过磷原子扩散形成所述N+区。
  7. 根据权利要求1所述的工艺，其特征在于：所述步骤六中，所述第二杂质掺杂为硼杂质掺杂，该硼杂质掺杂的工艺条件为：首先在与所述N+区同侧的所述第二区域的表面涂覆液态硼源，在1150±0.5℃炉管内，时间为2±0.05小时，气氛为氮气；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为18±0.05小时，气氛为氮气的条件下进行，从而在所述第二区域通过硼原子扩散形成所述P+区。
  8. 根据权利要求1所述的工艺，其特征在于：在步骤八中，所述多晶硅钝化复合薄膜层采用CVD工艺沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷气体和一氧化二氮气体，时间为25±1分钟，其中所述硅烷气体的流速为每分钟130±5ml，所述一氧化二氮气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷气体和一氧化二氮气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层。
  9. 根据权利要求1所述的工艺，其特征在于：在步骤九中，在所述沟槽中形成所述玻璃钝化层的工艺条件为：在沟槽内填充玻璃胶，厚度为25～35μm，然后通过高温烧结形成致密的所述玻璃钝化层，温度为830±10℃，时间为30±5分钟。
  10. 一种浅沟槽的电极同侧二极管芯片，其特征在于：包括一硅片衬底，所述硅片衬底的上表面通过第一杂质掺杂形成有N+区，并通过第二杂质掺杂形成有P+区，且N+区与P+区间隔设置；所述N+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；所述P+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm；
    其中，所述N+区或所述P+区的边缘区域开有沟槽，该沟槽的深度为20～40um；
    所述硅片衬底上表面于所述N+区以及所述P+区的周边区域以及所述沟槽的表面覆盖有一层多晶硅钝化复合薄膜层；所述沟槽中还填充有玻璃胶，其厚度为25～35μm，并通过高温烧结形成致密的玻璃钝化层；
    所述N+区以及所述P+区的表面均沉积有金属层，形成金属电极。
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