CN107680962A - 一种低正向电压tvs器件及其制造方法 - Google Patents

一种低正向电压tvs器件及其制造方法 Download PDF

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CN107680962A
CN107680962A CN201710891229.2A CN201710891229A CN107680962A CN 107680962 A CN107680962 A CN 107680962A CN 201710891229 A CN201710891229 A CN 201710891229A CN 107680962 A CN107680962 A CN 107680962A
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邹有彪
徐玉豹
刘宗贺
廖航
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Anhui Core Microelectronics Co Ltd
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Abstract

本发明公开一种低正向电压TVS器件,包括N+型半导体基体、位于N+型半导体基体上方的N‑型外延层和P+型扩散区,N‑型外延层上表面设有氧化层和肖特基势垒,N‑型外延层和P+型扩散区上方用于连接电极T1的金属层,位于N+型半导体基体下方用于连接电极T2的金属层;一种低正向电压TVS器件的制造方法,包括以下步骤:衬底准备、外延生长、氧化、P+扩散区光刻、硼掺杂、肖特基金属区光刻、溅射势垒金属、金属刻蚀、合金、引线孔光刻、蒸铝、铝反刻、铝合金、减薄和背面金属化。本发明通过将TVS二极管和肖特基二极管并联制作在同一芯片上,利用肖特基二极管进行电源反接保护并利用TVS二极管进行瞬态过压保护,可降低TVS器件的正向压降,提高TVS器件的性能。

Description

一种低正向电压TVS器件及其制造方法
技术领域
本发明属于半导体防护器件技术领域,涉及到一种低正向电压TVS器件及其制造方法。
背景技术
TVS器件作为一种保护器件,因其具有响应时间快、瞬态功率大、漏电流低、击穿电压偏差小、箝位电压容易控制、体积小等优点,一直广泛用于各种电子类产品。针对某些特殊应用,比如防电源反接及防浪涌电压,需要TVS器件具有较低的正向压降以降低出现电源反接时的功耗,常规的TVS器件已经不能满足要求。
发明内容
本发明的目的在于提供一种低正向电压TVS器件及其制造方法,解决了现有TVS器件的正向压降大,造成TVS器件的功耗大,严重影响TVS器件的性能。
本发明的目的可以通过以下技术方案实现:
一种低正向电压TVS器件,低正向电压TVS器件包括N+型半导体基体,位于N+型半导体基体上方的N-型外延层,位于N-型外延层中的P+型扩散区且P+型扩散区的底部延伸至N+型半导体基区内部,位于N-型外延层上表面的氧化层及肖特基势垒金属层,位于N-型外延层和P+型扩散区上方设有与接电极T1的金属层,位于N+型半导体基体下方用于连接电极T2的金属层。
进一步地,所述P+型扩散区的底部延伸至N+型半导体基区内部的深度为2-20um。
进一步地,一种低正向电压TVS器件的制造方法,包括以下步骤:
S1、衬底材料:选择N+型硅片,对硅片进行单面抛光;
S2、外延生长:在硅片表面生长N型外延层;
S3、氧化:对硅片进行氧化,氧化温度为1150℃,时间为5h,要求生长的氧化层厚度至少为1.2μm;
S4、P+扩散区光刻:使用匀胶机将氧化后硅片正面涂上光刻胶,经105℃/25min前烘,光刻机曝光,显影,坚膜,利用SiO2腐蚀液腐蚀出P+扩散区窗口,然后去胶,清洗,甩干;
S5、硼掺杂:包括浓硼预淀积和浓硼再扩散;
S6、肖特基金属区光刻:使用匀胶机将硅片正面涂上光刻胶,前烘,光刻机曝光,显影,坚膜,腐蚀出引线窗口,去胶;
S7、溅射势垒金属:使用金属溅射台,溅射势垒金属层,采用的势垒金属为Ti、Ni、Cr或NiPt;
S8、金属刻蚀;
S9、合金:形成肖特基势垒;
S10、引线孔光刻:使用匀胶机将硅片正面涂上光刻胶,前烘,光刻机曝光,显影,坚膜,腐蚀出引线窗口,去胶;
S11、蒸铝:铝层厚度δ=3.0~4.0μm;
S12、铝反刻:光刻版采用铝光刻版;
S13、铝合金;
S14、减薄:减薄后的厚度为230-250μm;
S15、背面金属化:背面蒸发钛镍银金属层。
进一步地,所述步骤S2对N+型硅片进行外延生长,外延层厚度5~8μm,N型掺杂,电阻率ρ为0.1~0.3Ω·cm。
本发明的有益效果:
本发明中的一种低正向电压TVS器件及其制造方法,通过将TVS二极管和肖特基二极管集成制作在同一芯片上,利用肖特基二极管进行电源反接保护并利用TVS二极管进行瞬态过压保护,可降低TVS器件的正向压降,提高TVS器件的性能。
附图说明
为了更清楚地说明本发明实施例的技术方案,下面将对实施例描述所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明一种低正向电压TVS器件的结构示意图。
附图中,各标号所代表的部件列表如下:
1-氧化层,2-肖特基势垒金属层,3-连接T1的金属层,4-连接T2的金属层。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。
请参阅图1所示,本发明为一种低正向电压TVS器件,通过将TVS二极管和肖特基二极管集成在同一芯片上构成低正向电压TVS器件,肖特基二极管具有低正向电压特性,肖特基二极管的反向击穿电压为20-45V,TVS二极管在反向工作时可抑制瞬态过电压,TVS二极管的反向击穿电压为14-28V,其中肖特基二极管的反向击穿电压高于TVS二极管的反向击穿电压,利用肖特基二极管进行电源反接保护,利用TVS二极管进行瞬态过压保护。
低正向电压TVS器件包括N+型半导体基体,位于N+型半导体基体上方的N-型外延层,位于N-型外延层中的P+型扩散区且P+型扩散区的底部延伸至N+型半导体基区内部,P+型扩散区的底部延伸至N+型半导体基区内部的深度为2-20um;位于N-型外延层上表面的氧化层1及肖特基势垒金属层2,位于N-型外延层和P+型扩散区上方用于连接电极T1的金属层3,位于N+型半导体基体下方用于连接电极T2的金属层4。
一种低正向电压TVS器件,其制造方法包括以下步骤:
S1、衬底材料:选择N+型硅片,电阻率ρ为0.01~0.05Ω·cm、硅片厚为320~330μm,并对硅片进行单面抛光;
S2、外延生长:在硅片表面生长N型外延层,外延层电阻率0.1-0.3Ω·cm,外延层的厚度为5~8μm;
S3、氧化:对硅片进行氧化,氧化温度为1150℃,氧化时间5h,保证生长的氧化层厚度至少为1.2μm;
S4、P+扩散区光刻:使用匀胶机将氧化后硅片正面涂上光刻胶,在105℃环境下进行25min时长的前烘,光刻机曝光,显影,坚膜,利用SiO2腐蚀液腐蚀出P+扩散区窗口,然后去胶,清洗,甩干;
S5、硼掺杂:包括浓硼预淀积和浓硼再扩散,其中,浓硼预淀积时的温度为T=1080±5℃,时间t=150-180min,要求:方块电阻R=3~5Ω/□;浓硼再扩散时的温度为T=1120℃,扩散时间t=0.5-2h;
S6、肖特基金属区光刻:使用匀胶机将硅片正面涂上光刻胶,在105℃环境下进行25min时长的前烘,光刻机曝光,显影,坚膜,利用SiO2腐蚀液腐蚀出肖特基金属区窗口,然后去胶,清洗,甩干;
S7、溅射势垒金属:使用金属溅射台,溅射势垒金属层,采用的势垒金属为Ti、Ni、Cr或NiPt;
S8、金属刻蚀:利用干法刻蚀机刻蚀肖特基势垒金属;
S9、合金:温度500-600℃,时间15-60min;
S10、引线孔光刻:使用匀胶机将硅片正面涂上光刻胶,经105℃/25min前烘,光刻机曝光,显影,坚膜,利用SiO2腐蚀液在正面腐蚀出引线窗口,同时去除硅片背面的氧化层,然后去胶,清洗,甩干;
S11、蒸铝:铝层厚度δ=3.0~4.0μm;
S12、铝反刻:光刻版采用铝光刻版;
S13、铝合金:温度450℃,时间20min
S14、减薄:减薄后的厚度为230-250μm;
S15、背面金属化:背面蒸发钛镍银金属层,厚度分别为
本发明中的一种低正向电压TVS器件及其制造方法,通过将TVS二极管和肖特基二极管集成制作在同一芯片上,利用肖特基二极管进行电源反接保护并利用TVS二极管进行瞬态过压保护,可降低TVS器件的正向压降,提高TVS器件的性能。
以上内容仅仅是对本发明的构思所作的举例和说明,所属本技术领域的技术人员对所描述的具体实施例做各种各样的修改或补充或采用类似的方式替代,只要不偏离发明的构思或者超越本权利要求书所定义的范围,均应属于本发明的保护范围。

Claims (4)

1.一种低正向电压TVS器件,其特征在于:低正向电压TVS器件包括N+型半导体基体,位于N+型半导体基体上方的N-型外延层,位于N-型外延层中的P+型扩散区且P+型扩散区的底部延伸至N+型半导体基区内部,位于N-型外延层上表面的氧化层(1)及肖特基势垒金属层(2),位于N-型外延层和P+型扩散区上方设有与接电极T1的金属层(3),位于N+型半导体基体下方用于连接电极T2的金属层(4)。
2.根据权利要求1所述的一种低正向电压TVS器件,其特征在于:所述P+型扩散区的底部延伸至N+型半导体基区内部的深度为2-20um。
3.一种低正向电压TVS器件的制造方法,其特征在于:包括以下步骤:
S1、衬底材料:选择N+型硅片,对硅片进行单面抛光;
S2、外延生长:在硅片表面生长N型外延层;
S3、氧化:对硅片进行氧化,氧化温度为1150℃,时间为5h,要求生长的氧化层厚度至少为1.2μm;
S4、P+扩散区光刻:使用匀胶机将氧化后硅片正面涂上光刻胶,经105℃/25min前烘,光刻机曝光,显影,坚膜,利用SiO2腐蚀液腐蚀出P+扩散区窗口,然后去胶,清洗,甩干;
S5、硼掺杂:包括浓硼预淀积和浓硼再扩散;
S6、肖特基金属区光刻:使用匀胶机将硅片正面涂上光刻胶,前烘,光刻机曝光,显影,坚膜,腐蚀出引线窗口,去胶;
S7、溅射势垒金属:使用金属溅射台,溅射势垒金属层,采用的势垒金属为Ti、Ni、Cr或NiPt;
S8、金属刻蚀:刻蚀肖特基势垒金属;
S9、合金:形成肖特基势垒;
S10、引线孔光刻:使用匀胶机将硅片正面涂上光刻胶,前烘,光刻机曝光,显影,坚膜,腐蚀出引线窗口,去胶;
S11、蒸铝:铝层厚度δ为3.0~4.0μm;
S12、铝反刻:光刻版采用铝光刻版;
S13、铝合金;
S14、减薄:减薄后的厚度为230-250μm;
S15、背面金属化:背面蒸发钛镍银金属层。
4.根据权利要求3所述的一种低正向电压TVS器件的制造方法,其特征在于:所述步骤S2对N+型硅片进行外延生长,外延层厚度5~8μm,N型掺杂,电阻率ρ为0.1~0.3Ω·cm。
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CN109659236A (zh) * 2018-12-17 2019-04-19 吉林华微电子股份有限公司 降低vdmos恢复时间的工艺方法及其vdmos半导体器件
CN111276393A (zh) * 2020-03-11 2020-06-12 天水天光半导体有限责任公司 一种晶圆级封装瞬态电压抑制二极管的制造方法
CN113270317A (zh) * 2021-05-27 2021-08-17 江苏晟驰微电子有限公司 一种低电容esd芯片制造工艺

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CN108899312A (zh) * 2018-05-17 2018-11-27 上海芯石半导体股份有限公司 一种单向npn穿通型超低压tvs结构及其制备方法
CN109659236A (zh) * 2018-12-17 2019-04-19 吉林华微电子股份有限公司 降低vdmos恢复时间的工艺方法及其vdmos半导体器件
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CN111276393B (zh) * 2020-03-11 2022-10-04 天水天光半导体有限责任公司 一种晶圆级封装瞬态电压抑制二极管的制造方法
CN113270317A (zh) * 2021-05-27 2021-08-17 江苏晟驰微电子有限公司 一种低电容esd芯片制造工艺

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