WO2002091405A1 - High-frequency module device - Google Patents
High-frequency module device Download PDFInfo
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- WO2002091405A1 WO2002091405A1 PCT/JP2002/004409 JP0204409W WO02091405A1 WO 2002091405 A1 WO2002091405 A1 WO 2002091405A1 JP 0204409 W JP0204409 W JP 0204409W WO 02091405 A1 WO02091405 A1 WO 02091405A1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09881—Coating only between conductors, i.e. flush with the conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/467—Adding a circuit layer by thin film methods
Definitions
- the present invention relates to a high-frequency module which is mounted on various electronic devices such as a personal computer, a mobile phone, and an audio device and has an information communication function ⁇ a storage function and constitutes a micro communication function module.
- various information such as music, voice, and images can be easily handled by personal computers, mobile computers, and the like with the progress of digitization. This information is subjected to bandwidth compression by audio codec technology and image codec technology, and is easily and efficiently distributed to various communication terminal devices by digital communication and digital broadcast. Is getting ready. For example, audio video data (AV data) can be received outdoors by portable mobile phones.
- AV data audio video data
- transmission / reception systems such as day / night are widely used by proposing a suitable network system even in a small area such as a home.
- a network system for example, a narrow-band wireless communication system of 5 GHz band as proposed in IEEE 802.11a, and a 2.4-band wireless communication system proposed in IEEE 80.lib.
- Various next-generation wireless systems such as a 5 GHz band wireless LAN system or a short-range wireless communication system called 31 uetooth, have been proposed.
- Transmission / reception systems for data transmission and reception use various types of data in various places, such as at home and outdoors, easily and without the use of a relay device, by effectively utilizing the wireless network system. Evening-access to the net network Trust is possible.
- a communication terminal device that is small, lightweight, portable, and has the above-described communication function.
- communication terminal equipment it is necessary to perform modulation and demodulation of analog high-frequency signals in the transmission / reception unit. Therefore, in general, as shown in Fig. 1, a superconducting system that converts transmission / reception signals to an intermediate frequency once.
- a high-frequency transmission / reception circuit 100 based on a heterodyne system is provided.
- the high-frequency transmission / reception circuit includes an antenna unit having an antenna or a switching switch for receiving or transmitting an information signal, and a transmission / reception switch for switching between transmission and reception.
- the high-frequency transmission / reception circuit includes a reception circuit unit including a frequency conversion circuit unit, a demodulation circuit unit, and the like.
- the high-frequency transmission / reception circuit includes a transmission circuit unit including a power amplifier, a drive amplifier, a modulation circuit unit, and the like. Further, the high-frequency transmission / reception circuit includes a reference frequency generation circuit for supplying a reference frequency to the reception circuit and the transmission circuit.
- the high-frequency transmitting / receiving circuit configured as above consists of various functional components such as various filters, local oscillators (VCOs), SAW filters, etc. inserted between each stage, matching circuits or bias circuits. It has a very large number of passive components such as inductors, resistors, and capacitors that are unique to high-frequency analog circuits such as.
- VCOs local oscillators
- SAW filters etc.
- passive components such as inductors, resistors, and capacitors that are unique to high-frequency analog circuits such as.
- each circuit section is made into an IC, but a filter inserted between each stage cannot be taken into the IC, and an external matching circuit is required for this purpose. Therefore, the high-frequency transmission / reception circuit becomes large as a whole, which has been a major obstacle to reducing the size and weight of communication terminal equipment.
- communication terminal equipment also employs a direct conversion type high-frequency transmission / reception circuit that transmits and receives information signals without conversion to an intermediate frequency.
- the high-frequency transmission / reception circuit the information signal received by the antenna unit is supplied to the demodulation circuit unit via the transmission / reception switch, and the baseband processing is directly performed.
- the high-frequency transmission / reception circuit directly modulates the information signal generated by the source source into a predetermined frequency band without converting it to an intermediate frequency in the modulation circuit section, and transmits the modulated signal from the antenna section via the amplifier and the transmission / reception switch.
- the high-frequency transmission / reception circuit configured as described above has an intermediate frequency Since transmission and reception are performed by performing direct detection without performing conversion, the number of components such as filters is reduced, the overall configuration is simplified, and a configuration closer to one chip is possible. Even in the high-frequency transmitting / receiving circuit using the direct-comparison method, it is necessary to cope with a filter or a matching circuit arranged at a subsequent stage. In addition, since the high-frequency transmission / reception circuit performs amplification once in the high-frequency stage, it is difficult to obtain a sufficient gain, and it is necessary to perform amplification operation also in the baseband section. Therefore, the high-frequency transmitting / receiving circuit requires a DC offset canceling circuit and an extra one-pass filter, and has a problem when the overall power consumption increases.
- a hole is formed in the Si substrate immediately below the inductor element, or a state in which the inductor element is floated. In the case of forming with, there are times when the processing is done, and the processing cost increases.
- the high-frequency signal circuit front end is formed on a semiconductor substrate such as Si or SiGe or a glass substrate, as a pattern wiring layer, in addition to the high-frequency signal circuit pattern, a power supply pattern, a ground pattern, and a control pattern. It is necessary to form a signal wiring pattern or the like, and when these pattern wiring layers are multilayered, problems such as mutual interference between the pattern wiring layers and an increase in processing cost occur.
- Such a high-frequency module device is further mounted on an intermediate substrate (intermediate substrate) by wire bonding or the like.
- an intermediate substrate intermediate substrate
- wire bonding or the like Although mounting is performed, the mounting area and the dimension in the thickness direction increase, which is not necessarily preferable in terms of cost.
- the present invention has been proposed in view of the above-described circumstances, and aims at further improving the characteristics of an inductor element, enabling further downsizing and cost reduction. And a high-frequency module device.
- a high-frequency module device proposed to achieve the above object has a base substrate portion in which a pattern wiring layer and a dielectric insulating layer are formed in multiple layers, and an uppermost layer of the base substrate portion is flat. And a high-frequency element portion on which an inductor element is formed with an insulating layer interposed therebetween, on which the pattern wiring layer of the base substrate is formed. A region that is not provided is provided at least from the uppermost layer of the base substrate portion to a halfway portion in the thickness direction, and a high-frequency device portion located immediately above this region is formed with an inductor element.
- FIG. 1 is a sectional view showing an example of a high-frequency module device according to the present invention.
- FIG. 2 is a cross-sectional view showing a main part of a high-frequency module device according to the present invention, in which a wiring prohibition region and a portion where an inductor is formed are enlarged.
- FIG. 3A to 3C are plan views showing the structure of the wiring prohibited area in each layer of the base substrate portion, FIG. 3A shows the wiring prohibited area in the second wiring layer, and FIG. FIG. 3C shows a wiring prohibited area in the third wiring layer, and FIG. 3C shows a wiring prohibited area in the fourth wiring layer. Indicates a line prohibited area.
- Fig. 4 is a plan view showing the structure of the inductor.
- FIG. 5A to 5C are plan views showing the structure of an inductor in each layer of the high-frequency element section.
- FIG. 5A shows a lead conductor pattern formed on the first insulating layer. Shows a buried conductor pattern buried in the second insulating layer, and
- FIG. 5C shows a thin-film coil pattern formed on the second insulating layer.
- FIG. 6 is a plan view showing another example of the inductor.
- BEST MODE FOR CARRYING OUT THE INVENTION a high-frequency module device according to the present invention will be described in detail with reference to the drawings.
- FIG. 1 is a sectional view showing an example of a high-frequency module device 1 according to the present invention.
- the high-frequency module device 1 according to the present invention has a package form (BGA or the like) for realizing high-density mounting on a mother board (pace substrate) or an internal poser (intermediate substrate). It works as one functional component.
- BGA package form
- the high-frequency module device 1 has a base substrate portion 2, and the top layer of the pace substrate portion 2 is flattened by a flattening layer 3. I have. As shown in FIG. 1, a high-frequency element section 4 is provided on the flattening layer 3.
- the base substrate section 2 is formed of a printed wiring board, and first and second wiring layers 6a and 6b serving as pattern wiring layers are formed on both surfaces of a first dielectric board 5 serving as a dielectric insulating layer.
- a second wiring board in which third and fourth wiring layers 9 a and 9 b serving as pattern wiring layers are formed on both surfaces of a first wiring board 7 and a second dielectric board 8 serving as a dielectric insulating layer 10 have a structure in which they are bonded via a prepreg (adhesive resin) 11 serving as a dielectric insulating layer.
- the first dielectric substrate 5 and the second dielectric substrate 8 are preferably formed of a material having a low dielectric constant and a low loss (low tan), that is, a material having excellent high-frequency characteristics.
- materials include, for example, polyphenylethylene (PPE), bismaleide triazine (BT-resin), polytetrafluoroethylene, Organic materials such as polyimide, liquid crystal polymer (LCP), and polynorpolene (PNB), and mixed materials of ceramics or ceramics and organic materials can be given.
- the first dielectric substrate 5 and the second dielectric substrate 8 are preferably formed of a material having heat resistance and chemical resistance in addition to the above-described materials, and the dielectric substrate made of such a material is preferably used.
- an epoxy-based substrate FR-5 which can be obtained at relatively low cost, can be mentioned.
- the first and second wiring layers 6a and 6b and the third and fourth wiring layers 9a and 9b are composed of functional elements such as a filter 12 and a capacitor 13 and a signal distribution connecting them.
- the line pattern 14, the power supply pattern 15 and the ground pattern 16 are formed by, for example, a thin film of copper foil.
- the first and second wiring layers 6a and 6b and the third and fourth wiring layers 9a and 9b can also be formed with passive elements such as an inductor and a resistor, and antenna patterns. It is.
- Each functional element is formed so as to penetrate the signal wiring pattern 14 connecting these, the power supply pattern 15 and the ground plane 16, and the first dielectric substrate 5 and the second dielectric substrate 8. For example, they are electrically connected via a via hole 17 or a through hole 18 having an inner peripheral surface provided with copper plating or the like.
- the via holes 17 and the through holes 18 are formed in a part of the base substrate portion 2 by drilling or laser processing a hole penetrating the pace substrate portion 2.
- These via holes 17 and through holes 18 are provided with an electrically conductive metal material such as copper (Cu) on the inner peripheral surface thereof, so that the pattern 14, 15, 16 is electrically connected. A function to connect automatically is provided.
- the first wiring board 7 and the second wiring board 10 made of an organic material which can be obtained at relatively low cost are laminated and formed by the same multi-layer board technology as before. Therefore, the cost can be reduced as compared with the conventional case where a relatively expensive Si substrate or glass substrate is used.
- the base substrate 2 is not limited to the above-described structure, and the number of stacked layers is arbitrary.
- the base board section 2 is not limited to the above-described double-sided wiring boards 7, 10 bonded together via the pre-predator 11, and for example, a resin-coated copper foil is provided on both main surfaces of the double-sided wiring board. May be stacked.
- the flattening layer 3 forms a so-called build-up formation surface by highly flattening the uppermost layer of the base substrate portion 2, that is, the fourth wiring layer 9b side of the second dielectric substrate 8.
- an insulating film made of an organic material having excellent high-frequency characteristics is formed on the entire surface of the uppermost layer of the base substrate portion 2 and then formed on the uppermost layer. Polishing is performed until the fourth wiring layer 9b is exposed. As a result, an insulating film is buried between the second dielectric substrate 8 and the fourth wiring layer 9b, and a portion of the second dielectric substrate 8 where the fourth wiring layer 9b is not formed is formed. The step is eliminated, and the uppermost layer of the base substrate portion 2 is highly planarized by the planarization layer 3.
- the high-frequency element section 4 is formed by laminating an insulating layer 19 on the build-up forming surface, and forming an insulating layer 19 on the inner or outer layer of the laminated insulating layer 19 by using a thin-film forming technique or a thick-film forming technique. , 21 1, 22 2, 23, and passive elements such as a capacitor and a resistor. In these passive elements composed of the inductors 20, 21, 22, 23, etc., the wiring pattern 24 and the buried conductor 25 are electrically connected by a pattern wiring layer.
- the insulating layer 19 constituting the high-frequency element section 4 is preferably formed of a material having a low dielectric constant and a low loss (low tand), that is, an organic material having excellent high-frequency characteristics.
- the insulating layer 19 is formed by applying such an organic material to a build-up forming surface by using a method excellent in coating uniformity and film thickness control such as a spin coating method, a curtain coating method, a roll coating method, and a dip coating method. It can be formed with high precision.
- a semiconductor chip 26 is mounted on the uppermost layer of the high-frequency element section 4 by flip-chip connection.
- bumps 27 are formed on the electrodes on the semiconductor chip 26 side, and the electrodes 28 and the bumps 27 of the wiring pattern 24 on the high-frequency element section 4 are turned upside down. Then, it is a mounting method of connecting by so-called “flush down bonding” by heating and melting.
- This flip-chip connection eliminates the need for a wire routing space as compared with, for example, wire bonding. Particularly, the dimension in the height direction can be significantly reduced.
- the passive element and the semiconductor chip 26 formed on the high-frequency element section 4 are electrically connected to the fourth wiring layer 9 b on the base substrate section 2 via the wiring pattern 24 and the buried conductor 25. It is connected to the.
- the number of layers in the high-frequency element portion 4 can be reduced by forming the base substrate portion 2 into a multilayer. That is, the high-frequency module device 1 according to the present invention includes a pace substrate separate from the pattern wiring layer formed on the inner layer or the outer layer of the high-frequency By forming a pattern wiring layer such as a functional element and a signal wiring pattern 14 on the inner layer or the outer layer of the part 2, when these are collectively formed on a conventional Si substrate or glass substrate, In comparison, the load on the high-frequency element unit 4 can be significantly reduced. This makes it possible to reduce the number of layers of the high-frequency element unit 4, thereby enabling further miniaturization and cost reduction of the entire device.
- the pattern wiring layer of the pace substrate section 2 and the pattern wiring layer of the high-frequency element section 4 are separated from each other, the electric interference generated between these pattern wiring layers Can be suppressed, and the characteristics can be improved.
- the high-frequency module device 1 since the high-frequency module device 1 according to the present invention has a build-up formation surface on which the uppermost layer of the base substrate portion 2 is highly planarized by the planarization layer 3, the high-frequency The element section 4 can be formed with high accuracy.
- the first and second wiring layers 6a and 6b and the third and fourth wiring layers 9a and 9b of the base substrate portion 2 are not formed.
- the area (hereinafter referred to as the wiring prohibited area) 30, 31, 32, 33 extends at least from the uppermost layer of the pace substrate part 2 to the middle part in the thickness direction or penetrates the base substrate part 2. It is provided.
- Inductors 20, 21, 22, and 23 are formed in the high-frequency element section 4 located immediately above the wiring prohibited areas 30, 31, 32, and 33, respectively.
- the wiring prohibited area 30 is provided from the position where the inductor 20 is formed to the area from the position where the inductor 20 is formed to the second wiring layer 6b.
- the first wiring prohibition hole 3 corresponding to the region where the inductor 20 is formed is formed in the fourth wiring layer 9b.
- a second wiring prohibition hole 35 corresponding to a region where the inductor 20 is formed is formed in the third wiring layer 9a.
- the ground pattern 16 formed on the second wiring layer 6b passes through the first wiring prohibiting hole 34 and the second wiring prohibiting hole 35. And the inductor 20 are opposed to each other with a predetermined distance therebetween.
- the inductor 20 is a thin-film coil that is located in the inner layer or the outer layer of the insulating layer 19 and is spirally wound so as to form a square as a whole.
- the lead conductor pattern 20 c is drawn out to the outer peripheral side of the thin-film coil pattern 20 a and embedded together with the outer peripheral end of the thin-film coil pattern 20 a.
- the wiring pattern 24 is electrically connected to the wiring pattern 24 via the conductor 25.
- a first insulating layer 19 a made of the above-described organic material is formed on a flat pace substrate 2.
- a conductive film made of a conductive metal material such as nickel (Ni) or copper is formed on the entire surface of the first insulating layer 19a.
- the conductive film is etched using the photoresist patterned into a predetermined shape using photolithography as a mask, thereby forming the base of the lead conductor pattern 20c.
- a lead / conductor pattern 20 c is formed by depositing a conductive film composed of about a few Cu by electrolytic plating using a copper sulfate solution.
- a second insulating layer made of the above-described organic material is formed on the first insulating layer 19 a on which the lead conductor path 20 c is formed.
- 1 9 b Is formed and then etched using a photoresist patterned into a predetermined shape using a photolithography technique as a mask, and a via (hole) that exposes a portion to be joined to an end of the lead conductor pattern 20c is formed.
- a conductive film made of copper (Cu) is formed by, for example, electrolytic plating using a copper sulfate solution, and the photoresist is deposited on the photoresist. Remove with the membrane.
- the buried conductor pattern 20b buried in the second insulating layer 19b and the lead conductor pattern 20c are electrically connected.
- a conductive film made of, for example, nickel (Ni), copper (Cu), or the like is formed over the entire surface of the second insulating layer 19b.
- the conductive film is etched using a photoresist patterned into a predetermined shape using a photolithography technique as a mask, thereby forming a thin film coil pattern 20a base.
- a conductive film made of a few / about Cu is formed by electrolytic plating using a copper sulfate solution, so that the thin film coil pattern 20 electrically connected to the buried conductor pattern 20 b is formed.
- Form a thus, an inductor 20 as shown in FIGS. 2 and 4 is formed.
- the thickness A of the inductor 20 is preferably in a range of not less than 10 m and not more than 1.5 times the winding interval B.
- the inductance 20 can be reduced by using the above-described plating method, compared to a film thickness of about 0.5 to 2 m, which is usually only about 0.5 to 2 m.
- the thickness A can be formed thick.
- the series resistance of the inductor 20 is reduced, and a high Q value of the inductor 20 can be obtained.
- the thickness A of the inductor 20 can be not more than 1.5 times the winding interval B, that is, the interval B between adjacent patterns in the thin-film coil pattern 20a, the inductor 20 can be formed accurately. can do.
- the inductor 20 can be formed with a predetermined thickness A by using a thick film technique other than the plating method described above.
- Inductor 20 has a rectangular spiral shape as shown in Fig. 4.
- the shape is not limited to this, and may be, for example, spirally wound so as to form a circle as shown in FIG.
- the other inductors 21, 22, and 23 also have the same shape as the above-described inductor 20, and are formed in the same manner as the above-described inductor 20, so that the description is omitted below. It shall be.
- the wiring-prohibited areas 30, 31, 31, 32, and 33 of the base substrate portion 2 extend from at least the uppermost layer of the base substrate portion 2 to the middle portion in the thickness direction. Or through the base plate portion 2.
- Inductors 20, 21, 22, and 23 are formed in the high-frequency element section 4 located immediately above the wiring prohibited areas 30, 31, 32, and 33, respectively.
- the distance between each of the inductors 20, 22, and 23 and the ground pattern 16 can be increased, and these inductors 20, 22, and 23 and the ground pattern 16 can be separated. And the coupling capacity with the substrate can be greatly reduced.
- the inductor 21 is formed on the wiring-prohibited area 31 provided to penetrate the pace substrate section 2, further improvement of the characteristics is achieved.
- the high Q value of these inductors 20, 21, 22, and 23 can be obtained, and a hole can be formed in the Si substrate just below the conventional inductor, and this inductor element can be floated. If formed in the bent state, good characteristics of the inductors 20, 21, 22, and 23 can be obtained by a simple configuration without any processing. From the above, in the high-frequency module device 1, the characteristics of the inductors 20:21, 22, and 23 can be further improved, and further downsizing and cost reduction can be achieved. INDUSTRIAL APPLICABILITY
- the high-frequency module device according to the present invention is configured such that the inductor element is formed immediately above a region of the pace substrate portion where the pattern wiring layer is not formed.
- the high-frequency module device according to the present invention
- the characteristics of the inductor element can be further improved, and further downsizing and cost reduction can be achieved.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Coils Or Transformers For Communication (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02724688A EP1387369A4 (en) | 2001-05-07 | 2002-05-02 | HIGH FREQUENCY MODULE DEVICE |
KR1020037000054A KR100862544B1 (ko) | 2001-05-07 | 2002-05-02 | 고주파 모듈 장치 |
US10/332,015 US6800936B2 (en) | 2001-05-07 | 2002-05-02 | High-frequency module device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001-136490 | 2001-05-07 | ||
JP2001136490A JP3666411B2 (ja) | 2001-05-07 | 2001-05-07 | 高周波モジュール装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002091405A1 true WO2002091405A1 (en) | 2002-11-14 |
Family
ID=18983757
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2002/004409 WO2002091405A1 (en) | 2001-05-07 | 2002-05-02 | High-frequency module device |
Country Status (5)
Country | Link |
---|---|
US (1) | US6800936B2 (ja) |
EP (1) | EP1387369A4 (ja) |
JP (1) | JP3666411B2 (ja) |
KR (1) | KR100862544B1 (ja) |
WO (1) | WO2002091405A1 (ja) |
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- 2002-05-02 EP EP02724688A patent/EP1387369A4/en not_active Withdrawn
- 2002-05-02 US US10/332,015 patent/US6800936B2/en not_active Expired - Lifetime
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1443811A3 (en) * | 2003-01-30 | 2007-03-07 | Endicott Interconnect Technologies, Inc. | High speed circuit board and method for fabrication |
EP1443560A3 (en) * | 2003-01-30 | 2008-01-02 | Endicott Interconnect Technologies, Inc. | Multi-chip electronic package having laminate carrier and method of making same |
US7665207B2 (en) | 2003-01-30 | 2010-02-23 | Endicott Interconnect Technologies, Inc. | Method of making a multi-chip electronic package having laminate carrier |
Also Published As
Publication number | Publication date |
---|---|
KR100862544B1 (ko) | 2008-10-09 |
US6800936B2 (en) | 2004-10-05 |
EP1387369A1 (en) | 2004-02-04 |
JP2002334806A (ja) | 2002-11-22 |
KR20030041951A (ko) | 2003-05-27 |
JP3666411B2 (ja) | 2005-06-29 |
US20030148739A1 (en) | 2003-08-07 |
EP1387369A4 (en) | 2009-08-19 |
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