WO1999041812A1 - Support de circuit integre - Google Patents

Support de circuit integre Download PDF

Info

Publication number
WO1999041812A1
WO1999041812A1 PCT/JP1999/000743 JP9900743W WO9941812A1 WO 1999041812 A1 WO1999041812 A1 WO 1999041812A1 JP 9900743 W JP9900743 W JP 9900743W WO 9941812 A1 WO9941812 A1 WO 9941812A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
conductor layer
ground
hole
conductor
Prior art date
Application number
PCT/JP1999/000743
Other languages
English (en)
Japanese (ja)
Inventor
Shigeru Matsumura
Kenji Yoshida
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corporation filed Critical Advantest Corporation
Publication of WO1999041812A1 publication Critical patent/WO1999041812A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R33/00—Coupling devices specially adapted for supporting apparatus and having one part acting as a holder providing support and electrical connection via a counterpart which is structurally associated with the apparatus, e.g. lamp holders; Separate parts thereof
    • H01R33/74—Devices having four or more poles, e.g. holders for compact fluorescent lamps
    • H01R33/76—Holders with sockets, clips, or analogous contacts adapted for axially-sliding engagement with parallely-arranged pins, blades, or analogous contacts on counterpart, e.g. electronic tube socket
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433—Sockets for IC's or transistors
    • G01R1/0483—Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
    • H05K7/1092—Plug-in assemblages of components, e.g. IC sockets with built-in components, e.g. intelligent sockets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Definitions

  • the present invention relates to an IC socket to which a semiconductor integrated circuit (hereinafter, referred to as an IC) is electrically contacted.
  • IC semiconductor integrated circuit
  • a conventional IC socket 1 has a plurality of through holes 2A vertically opened in an insulating resin block 2 and a circular elongated conductor called a probe connector is formed in these through holes 2A.
  • a probe contact 3a, 3b, and 3c are attached, for example, by press fitting.
  • Contacts 3A and 3B are mounted on both ends of each probe contact so as to be movable in the axial direction of the probe contact.
  • the upper contact 3 A is brought into contact with the terminal of the IC under test (hereinafter referred to as DUT) 4.
  • the DUT 4 is a ball ⁇ Ball Grid Array type IC (IC with a large number of ball-shaped terminals (bumps) formed on the back surface of the IC package: BGA ⁇ IC Therefore, the end face of the contact 3A has a shape depressed in a mortar shape so that stable contact with the ball terminal 4A of the DUT 4 can be obtained.
  • the lower contact 3B has a pointed conical shape in order to obtain stable contact with the land 6 formed on the surface of the socket board 5.
  • the socket board 5 is a printed circuit board on which the IC socket 1 is mounted, and is usually formed of a multilayer printed circuit board.
  • a predetermined number of lands are provided on the front and back surfaces (the upper and lower surfaces in the figure). 6 are each formed. The upper and lower two lands 6 at opposing positions on the front and back surfaces are electrically connected by through-hole conductors 7a, 7b, and 7c formed in the through-holes.
  • the front and back surfaces of the socket board 5 where the IC socket 1 is not mounted (see the figure)
  • a predetermined number of lands are formed on the upper and lower surfaces, respectively. The lands are electrically connected by through-hole conductors 8a, 8b, 8c formed in the through-holes.
  • the land 6 on the surface of the socket board comes into contact with the corresponding contact 3B of the probe contact of the IC socket 1.
  • These lands 6 are connected to through-hole conductors 7a, 7b, 7c, conductor layers (wiring patterns) 9a, 9b, 9c inside the socket board, and through-hole conductors 8a, 8b, 8c. Connected to terminals (lands) 10a, 10b, and 10c for connection to a circuit or device, so that IC socket 1 is connected to an external circuit or device.
  • Conductive layer 9 a of the top is a pattern for the ground to provide a common potential (also referred to as GND) to DUT 4, and is electrically connected to the through-hole conductors 7 a and 8 a.
  • the middle conductor layer 9b is a power supply pattern for supplying power to the DUT 4, and is electrically connected to the through-hole conductors 7b and 8b.
  • the lowermost conductor layer 9c is a signal pattern for applying a test signal to the DUT 4 and detecting a response signal of the DUT, and is electrically connected to the through-hole conductors 7c and 8c. .
  • the through-hole conductors 7a and 8a constitute a through-hole conductor for ground
  • the through-hole conductors 7b and 8b constitute a through-hole conductor for power supply
  • the through-hole conductors 7c and 8c Constitutes a signal through-hole conductor.
  • the probe contact 3a of the IC socket 1 forms a grounding probe contact
  • 3b forms a signal probe contact
  • 3c forms a power supply probe contact.
  • the signal land 9c electrically connected to the signal pattern 9c and the ground land 10a electrically connected to the ground pattern 9a are passed through the core of the cable 11 and its shield, and the power supply pattern.
  • 9b is connected to the performance board 12 through the wiring 13 Further, the internal wiring of the performance board 12 and the probe connection bin 15 are connected to the test head 14 of the IC tester.
  • the DUT 4 and IC socket 1 are required to increase the current capacity of the GND system (current capacity flowing into or out of the common potential point) and to reduce the impedance of the path for GND. Accordingly, a plurality of balls 4A and probe contacts 3a to be in contact therewith are formed.
  • the conventional IC socket 1 has a drawback that the impedance of the probe contacts 3a, 3b, and 3c is inserted in series into the connection line to the DUT 4, thereby causing impedance mismatch.
  • This impedance mismatch may cause distortion of the high-speed signal waveform to reduce the measurement accuracy, or may cause distortion of the power supply waveform to generate power supply noise. Disclosure of the invention
  • An object of the present invention is to provide an IC socket which solves the above-mentioned problems of the prior art IC socket.
  • Another object of the present invention is to provide an IC socket that does not cause impedance mismatch.
  • Still another object of the present invention is to generate a capacitance for bypassing power supply noise between a ground conductor layer and a power supply conductor layer formed on a multilayer printed circuit board, thereby generating power supply waveform distortion and power supply noise.
  • An object of the present invention is to provide an IC socket that suppresses the above.
  • a ground conductor layer and a power supply conductor layer have at least two conductor layers laminated at a predetermined interval, and A multi-layer printed circuit board having a plurality of through holes formed in the same direction, and through-hole conductors formed in all the through holes of the multi-layer printed circuit board, respectively, and electrically connected to the ground conductor layer. Attached to the connected through-hole conductor for ground, the through-hole conductor for power supply electrically connected to the above-mentioned power supply conductor layer, the through-hole conductor for signal not connected to any conductor layer, and the through-hole conductor above That is electrically connected to the terminals of the IC under test.
  • An IC socket having a lobe contact, and configured to generate a capacitance between the ground conductor layer and the power supply conductor layer using the material of the multilayer printed circuit board as a dielectric, thereby bypassing power supply noise.
  • a plurality of the ground through-hole conductors are formed, and the probe contact is not attached to at least one of the ground through-hole conductors.
  • the distance between the signal through-hole conductor and the gap between the ground conductor layer and the power supply conductor layer is determined by the capacitance between these gaps and the parasitic inductance of the probe contact.
  • the characteristic impedance of the transmission line formed by is set so as to be a predetermined value.
  • test IC is BGA ⁇ IC (Ball Grid Array type Integrated
  • a probe contact is formed at one end on the side of the IC under test, in contact with the ball-shaped terminal of the BGA * IC, and an IC socket is mounted on the opposite end.
  • a bin connector is formed to contact the land formed on the surface of the socket board to be placed.
  • the multilayer printed board has at least four conductor layers in which conductor layers for ground and conductor layers for power supply are alternately laminated at a predetermined interval, and two adjacent ground layers are used. Capacitance is generated between the conductor layer and the power supply conductor layer by using the material of the multilayer printed circuit board as a dielectric.
  • the multilayer printed circuit board has therein at least four conductive layers in which conductive layers for ground and conductive layers for power are alternately laminated at a predetermined interval.
  • An IC in which an interstitial via hole or via hole for electrically connecting two ground conductor layers or two power conductor layers is formed around the signal through-hole conductor.
  • a socket is provided.
  • two ground conductor layers and two power supply conductor layers are alternately laminated at predetermined intervals, and the two ground conductor layers are arranged around the signal through-hole conductor. Or an electrical via hole or via hole is formed to electrically connect the two power supply conductive layers. I have.
  • ground through-hole conductors are formed, and the probe contact cannot be attached to at least one of the ground through-hole conductors.
  • the distance of the gap between the signal through-hole conductor, the ground conductor layer and the power supply conductor layer is determined by the capacitance between the gaps, and the signal through-hole conductor and the via-hole. Is set so that the characteristic impedance of the transmission line formed by the total capacitance obtained by adding the capacitance formed between the above and the parasitic inductance of the probe contact becomes a predetermined value.
  • the IC under test is a BGA 'IC
  • each of the probe contacts has a contact formed at one end on the IC under test side to contact a ball-shaped terminal of the BGA IC. At the opposite end, a pin contact is formed to contact a land formed on the surface of the socket board on which the IC socket is placed.
  • the multilayer printed board has at least four conductor layers in which conductor layers for ground and conductor layers for power supply are alternately laminated at a predetermined interval, and two adjacent ground layers are used.
  • a capacitance is generated between the conductor layer and the power supply conductor layer by using the material of the multilayer printed circuit board as a dielectric.
  • a multi-layer structure in which a ground conductor layer, a power supply conductor layer, and a signal conductive layer are laminated at a predetermined interval and a plurality of through holes are formed in a vertical direction.
  • a printed circuit board a through-hole conductor formed on each of the through-holes of the multilayer printed circuit board; a ground through-hole conductor electrically connected to the ground conductor layer;
  • the multilayer printed board material to produce a Capacity evening Nsu as a dielectric, IC socket I provide is configured to bypass the power supply noise between the layer It is.
  • a plurality of the ground through-hole conductors are formed, and the probe contact is not attached to at least one of the ground through-hole conductors.
  • the distance between the signal through-hole conductor and the gap between the ground conductor layer and the power supply conductor layer is determined by the capacitance between these gaps and the parasitic inductance of the probe connector.
  • the characteristic impedance of the transmission line formed with the impedance is set to a predetermined value.
  • each of the probe contacts has a contact formed at one end of the IC under test side to contact the ball-shaped terminal of the BGA 'IC.
  • An external connection land electrically connected to the ground conductor layer, the power supply conductor layer, and the signal conductor layer is formed on at least one surface of the multilayer printed board.
  • FIG. 1 is a sectional view principally showing the configuration and electrical connection of a first embodiment of an IC socket according to the present invention.
  • FIG. 2 is a circuit diagram showing an electrical connection between the power supply conductor layer and the ground conductor layer of the IC socket shown in FIG.
  • FIG. 3 is an electrical equivalent circuit diagram of the signal probe contact 3c of the IC socket shown in FIG. 1 and its periphery.
  • FIG. 4 is a sectional view principally showing the configuration and electrical connection of a second embodiment of the IC socket according to the present invention.
  • FIG. 5 is a sectional view principally showing the configuration and electrical connection of a third embodiment of the IC socket according to the present invention.
  • FIG. 6 is a sectional view principally showing the configuration and electrical connection of a conventional IC socket and its peripheral devices.
  • FIG. 1 is a sectional view principally showing the configuration and electrical connection of a first embodiment of an IC socket according to the present invention.
  • the IC under test (DUT) 4 that contacts the contact 3A on the upper part of the IC socket 1 is a ball grid array type IC (BGA IC). ).
  • the IC socket 1 has at least four conductive layers (ground patterns) and power supply conductive layers (wiring patterns) alternately stacked at predetermined intervals.
  • a multi-layer printed circuit board 20 having a wiring pattern) and a plurality of through holes formed in a vertical direction; and a plurality of through-hole conductors 21 a formed in the plurality of through holes of the multi-layer printed circuit board 20.
  • 21a ', 21b, 21c and at least one of these through-hole conductors (2 la' in this embodiment) except for the through-hole conductors (21a, 21b, 21a, 21b, 21c), is composed of probe contacts 3a, 3b, and 3c that are electrically connected to the terminals of the DUT 4, for example, each of which is attached by press-fitting.
  • Ground patterns or GND patterns) 23 and 25 are electrically connected to the through-hole conductors 21 a and 21 a ′, respectively, and are connected to the power supply conductor layer (hereinafter referred to as the power supply pattern) 22.
  • And 24 are each electrically connected to a through-hole conductor 21b.
  • the through-hole conductors 21 a and 21 a ′ constitute ground through-hole conductors, and the probe contacts 3 a attached to these through-hole conductors 21 a and 21 ar constitute ground probe contacts.
  • the through-hole conductor 21b forms a power supply through-hole, and the probe contact 3b attached to this through-hole conductor 21b forms a power supply probe contact.
  • c constitutes a signal through-hole, and the probe contact 3 c attached to this through-hole conductor 21 c constitutes a signal probe contact.
  • the conventional IC socket Like the conventional IC socket, it is attached to both ends of each probe contact.
  • the contacts 3A and 3B are movable in the axial direction of the probe contact.
  • the DUT 4 since the DUT 4 is a BGA IC, the end surface of the upper contact 3 A that comes into contact with the terminal (ball 4 A) of the DUT 4 has a shape depressed in a mortar shape.
  • the tip of the lower contact 3 B that contacts the land on the surface has a conical pointed shape.
  • 01174 is an IC other than the 80 'IC, it goes without saying that the upper contact 3A is formed so as to have a shape that can surely make electrical contact with the corresponding terminal of the IC under test. Since the socket board 5 on which the IC socket 1 is mounted has the same configuration as the socket board of the conventional IC socket shown in FIG. 6, the description is omitted.
  • a capacitor (capacitor) CA is formed by using the material of the printed circuit board 20 as a dielectric, and the GND pattern 25 to which the ground single-hole conductors 21a and 21a 'are connected and the power supply.
  • Capacitors (capacitors) CB using the material of the printed circuit board 20 as a dielectric are formed between the power supply pattern 24 to which the through-hole conductors 21b are connected.
  • Each of these capacities CA and CB has a function to bypass power supply noise. If necessary, an external capacity (not shown) may be connected in parallel with the capacity CA and CB.
  • the through-hole conductor 2 1a 'to which the probe contact is not attached is connected in parallel with the GND through-hole conductor 2 1a to which the GND probe contact 3a is attached through GND patterns 23 and 25, and is connected to GND.
  • the series impedance of the path is reduced.
  • the through-hole conductor 2l a ' may be omitted.
  • FIG. 2 shows an electrical connection between the power supply patterns 22 and 24 and the ground patterns 23 and 25 of the IC socket 1 shown in FIG.
  • a plurality of GND through-hole conductors 21a into which the GND probe contacts 3a are fitted, and a plurality of GND through-hole conductors into which the GND probe contacts 3a are not fitted. Are connected in parallel with each other through GND patterns 23 and 25. You. As a result, the current capacity flowing into or out of the common potential point, that is, the current capacity of the GND system is increased, and the series impedance of the GND path is suppressed to a small value. Does not occur.
  • the low-pass filter is composed of the parasitic inductances La, Lb, and Lc of the power probe contact 3b, and the above-mentioned capacitances (capacitances) CA and CB, and the pass band of the low-pass filter. Since the width can be set sufficiently wide, even if the power supply current / voltage of the DUT4 changes stepwise, waveform distortion such as overshoot and undershoot occurring at the rise and fall of the DUT4 will be suppressed to such a degree that there is no problem. Therefore, the noise component generated by this is suppressed to a level that causes no problem. External noise is also suppressed by this low-pass filter at the same time.
  • Ld, Le, and Lf indicate the parasitic inductance of the probe contact 3a for GND
  • Lg indicates the parasitic inductance of the through-hole conductor 21a 'for GND.
  • FIG. 3 is an electrical equivalent circuit diagram of the signal probe contact 3c of the IC socket 1 shown in FIG. 1 and its periphery. Since the capacitances CA and CB are quite large for the signal frequency, the power supply patterns 22 and 24 are respectively short-circuited to the GND patterns 23 and 25 through the corresponding capacitances CA and CB.
  • the gap distance d between the signal through-hole conductor 21c and the GND patterns 23 and 25 and the power supply patterns 22 and 24 But the capacitance corresponding to those gaps ⁇ - ( ⁇ and parasitic Indakutansu 1 ⁇ ⁇ L 5 to the characteristic impedance Z 0 of the transmission line made of a predetermined value of the signal probe configuration evening transfected 21 c (e.g., 50 ).
  • FIG. 4 shows a second embodiment of the IC socket according to the present invention.
  • the IC socket 1 also serves as the conventional socket board 5.
  • This IC socket 1 comprises a multilayer printed circuit board 20 'having three conductor layers in which a GND pattern 9a, a power supply pattern 9b, and a signal pattern 9c are formed in an insulated state from each other.
  • This multilayer printed circuit board is used as a multilayer printed circuit board, and a predetermined number of through holes are formed in the multilayer printed circuit board 20 'in the vertical direction, and through hole conductors 21a, 21a', 21b, and 21c are formed in these through holes.
  • the remaining through-hole conductors (21a, 21b, 21c in this embodiment) excluding at least one of these through-hole conductors (21a 'in this embodiment) for example,
  • the cylindrical sockets 30a, 30b, 30c are respectively mounted, and these cylindrical sockets 30a, 30b, 30 are mounted.
  • the probe contacts 3a, 3b, and 3c that are electrically connected to the terminals (balls 4A) of the 011-fourth are fitted to the terminals.
  • the ground through-hole conductors 21a and 21a ' are electrically connected to the GND pattern 9a, respectively, and the power supply through-hole conductor 2 lb is electrically connected to the power supply pattern 9b to provide signal through.
  • the hole conductor 21c is electrically connected to the signal pattern 9c. Therefore, the probe contact 3a is electrically connected to the GND pattern 9a through the cylindrical socket 30a, and the probe contact 3b is connected to the power supply through-hole conductor 21b through the cylindrical socket 30b.
  • the probe contacts 3a, 3b, 3c are electrically connected to the signal through-hole conductor 21 through the cylindrical socket 30c.
  • a capacitor (capacitor) C made of the material of the multilayer printed circuit board 20 'as a dielectric is formed between the GND pattern 9a and the power pattern 9b, thereby bypassing power noise.
  • an external capacity connector may be connected in parallel with capacity connector C.
  • FIG. 5 is a sectional view principally showing the configuration and electrical connection of a third embodiment of the IC socket according to the present invention.
  • a plurality of inductive stations for electrically connecting the GND patterns 23 and 25 around the signal probe contact 3c at a predetermined angular interval.
  • a via hole (interstitial via hole) or via hole 31 is provided, and the distances d 2 and d 4 of the gap between the signal through-hole conductor 21 c and the ground patterns 23 and 25 are reduced. It is designed so that the capacitance can be increased without reducing it.
  • the IC socket 1 is provided with a large number of signal probe contacts 3c, a plurality of signal probes 3c for electrically connecting the GND patterns 23 and 25 around all the signal probe contacts 3c.
  • the above-mentioned evening stial, via hole or via hole 31 is formed.
  • the above-mentioned via-stitial 'via' hole or via-hole 31 does not electrically connect between GND pins 23 and 25, but connects between power supply patterns 22 and 24.
  • a hole or via hole 31 may be formed, or may be formed only around a predetermined number of signal probe contacts 3c, but not all.
  • the same operation and effect as those of the first embodiment can be obtained by the configuration of the third embodiment. Therefore, the description thereof is omitted, but in the case of the first embodiment, the signal Distance d 2 , d 4 between the through-hole conductor 21 c for ground and the patterns 23, 25 for ground, or the through-hole conductor 21 c for signal and the patterns 22, 24 for power without extremely small distance d have d 3 of the gap between the, that is, the ground path evening Ichin 2 3 and 2 5, or the power supply pattern 2 2 and 2 for 4 signal through-hole conductor 2 1 c Unless it is very close to the surroundings, the required capacitance C i to C 4 cannot be obtained.
  • the third embodiment since the capacitance between the signal probe contact 3c and the via hole 31 parallel to the signal probe contact 3c is large, the signal through hole for the signal as in the first embodiment is used. gap between the distance d 2, d 4 or signal through-hole conductor 2 1 c and the power supply pattern 2 2 ⁇ beauty 2 4, the gap between the conductor 2 1 c and the ground pattern 2 3 and 2 5 necessary to reduce the distance d have d 3 of is eliminated. Therefore, there is an advantage that workability is improved.
  • the IC socket according to the present invention uses a multilayer printed circuit board in which conductor layers including a GND pattern, a power supply pattern, and a signal pattern are stacked at predetermined intervals.
  • a low-pass filter (LPF) is formed between the GND pattern and the power supply pattern by forming a capacity to bypass power supply noise, and the capacitance and the parasitic inductance of the power supply probe contact. Since the bandwidth is configured to be set sufficiently wide, there is an advantage that it is possible to suppress the occurrence of power supply waveform distortion and power supply noise due to the parasitic inductance of the power supply probe connector. .
  • the distance of the gap between the signal through-hole conductor and the GND pattern and the power supply pattern is the capacitance between these gaps, or the sum of these capacitances plus the capacitance due to via holes. Since the characteristic impedance of the transmission line formed by the capacitance of the signal and the parasitic inductance of the signal probe contact is set to a predetermined value, impedance matching with the DUT etc. is achieved, This has the advantage that the waveform distortion is suppressed and the measurement accuracy is improved.
  • the present invention can be applied not only to the IC socket used in the IC test, but also to the IC sockets of various devices with which the IC is brought into contact, and the same operational effects can be obtained.
  • the present invention can be applied not only to the IC socket used in the IC test, but also to the IC sockets of various devices with which the IC is brought into contact, and the same operational effects can be obtained.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Measuring Leads Or Probes (AREA)
  • Connecting Device With Holders (AREA)

Abstract

L'invention se rapporte à un support de circuit intégré qui permet, d'une part, de réduire les bruits provenant des contacts de test de l'alimentation et la distorsion des formes d'ondes dans les contacts de test du signal et, d'autre part, d'éviter le déséquilibrage d'impédances. Une carte de circuit imprimé (20) possédant au moins quatre couches conductrices, y compris les couches conductrices de mise à la terre (23 et 25) et les couches conductrices d'alimentation (22 et 24) alternées, est munie de plusieurs conducteurs à orifice traversant (21a, 21a', 21b et 21c). A l'exception d'au moins un conducteur à orifice traversant, par exemple (21a'), tous les autres (21a, 21b, 21c) sont munis de contacts de test (3a, 3b et 3c) qui sont destinés au contact avec les bornes du dispositif testé (4). Les couches conductrices de mise à la terre sont connectées électriquement avec les conducteurs à orifice traversant (21a et 21a'), alors que les couches conductrices d'alimentation sont connectées à travers le conducteur à orifice traversant (21b) de manière à former des condensateurs (CA et CB) qui utilisent la carte de circuit imprimé (20) en tant que diélectrique entre les couches conductrices de mise à la terre et les couches conductrices d'alimentation.
PCT/JP1999/000743 1998-02-17 1999-02-17 Support de circuit integre WO1999041812A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3441898 1998-02-17
JP10/34418 1998-02-17

Publications (1)

Publication Number Publication Date
WO1999041812A1 true WO1999041812A1 (fr) 1999-08-19

Family

ID=12413666

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1999/000743 WO1999041812A1 (fr) 1998-02-17 1999-02-17 Support de circuit integre

Country Status (4)

Country Link
KR (1) KR20010006503A (fr)
CN (1) CN1262800A (fr)
TW (1) TW456074B (fr)
WO (1) WO1999041812A1 (fr)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1115129A2 (fr) * 1999-12-28 2001-07-11 TDK Corporation Condensateur multicouche
WO2002076162A1 (fr) * 2001-03-16 2002-09-26 Sun Microsystems, Inc. Systeme de distribution de puissance a structure de puissance specifique comprenant des ouvertures permettant le montage de boitiers de circuit integre
US6791846B2 (en) 2000-10-30 2004-09-14 Sun Microsystems, Inc. Power distribution system with a dedicated power structure and a high performance voltage regulator
US7446545B2 (en) 2003-05-08 2008-11-04 Unitechno Inc. Anisotropically conductive sheet
JP2009230897A (ja) * 2008-03-19 2009-10-08 Fujitsu Ltd 電子部品接合装置、電子ユニット、および電子装置
WO2010027597A2 (fr) 2008-09-04 2010-03-11 3M Innovative Properties Company Douille de dispositif electronique
JP2011075313A (ja) * 2009-09-29 2011-04-14 Three M Innovative Properties Co Ｉｃデバイス検査用ソケット
JP2011252766A (ja) * 2010-06-01 2011-12-15 3M Innovative Properties Co 接触子ホルダ
JP2016153796A (ja) * 2016-03-31 2016-08-25 スリーエム イノベイティブ プロパティズ カンパニー Ｉｃデバイス検査用ソケット
JP2018009994A (ja) * 2017-08-04 2018-01-18 スリーエム イノベイティブ プロパティズ カンパニー Ｉｃデバイス用ソケット
JP2018021914A (ja) * 2017-08-04 2018-02-08 スリーエム イノベイティブ プロパティズ カンパニー Ｉｃデバイス用ソケット
EP3340747A1 (fr) * 2016-12-22 2018-06-27 Google LLC Support de circuit intégré multicouche comportant un réseau d'adaptation d'impédance intégré
KR20190117017A (ko) * 2017-02-24 2019-10-15 테크노프로브 에스.피.에이. 향상된 주파수 특성을 갖는 수직 프로브 테스트 헤드
JP2020008546A (ja) * 2018-07-02 2020-01-16 力成科技股▲分▼有限公司 試験ソケットおよび試験装置

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6468089B1 (en) * 2001-04-20 2002-10-22 Molex Incorporated Solder-less printed circuit board edge connector having a common ground contact for a plurality of transmission lines
JP4186589B2 (ja) * 2002-10-30 2008-11-26 松下電器産業株式会社 シート形電子部品モジュール
CN100427955C (zh) * 2003-06-05 2008-10-22 株式会社爱德万测试 元件介面装置
US7077661B2 (en) * 2004-02-18 2006-07-18 Intel Corporation Socket for having the same conductor inserts for signal, power and ground
US7208936B2 (en) * 2004-04-12 2007-04-24 Intel Corporation Socket lid and test device
CN100367711C (zh) * 2005-05-10 2008-02-06 杭州华三通信技术有限公司 具有滤波装置的网口
CN101231322B (zh) * 2007-02-09 2011-01-26 段超毅 集成电路开路/短路的测试连接方法
KR100882512B1 (ko) * 2007-04-25 2009-02-10 윌테크놀러지(주) 프로브 카드
CN102012440B (zh) * 2010-11-11 2014-04-09 嘉兴斯达微电子有限公司 一种功率模块测试夹具
US8808010B2 (en) * 2011-06-06 2014-08-19 Interconnect Devices, Inc. Insulated metal socket
JP2020047652A (ja) * 2018-09-14 2020-03-26 キオクシア株式会社 半導体記憶装置及び電子機器
TWI684772B (zh) * 2019-03-11 2020-02-11 創意電子股份有限公司 檢測裝置及其探針座
CN110045160B (zh) * 2019-05-24 2021-06-08 安徽鹰龙工业设计有限公司 一种bga封装用的上方取放的测试座
CN112038853B (zh) * 2019-06-03 2023-09-05 泰科电子(上海)有限公司 连接器和天线系统
AT524410A1 (de) * 2020-11-09 2022-05-15 Greenwood Power Gmbh Anordnung einer Messvorrichtung

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58129792A (ja) * 1982-01-28 1983-08-02 ミユ−パツク・コ−ポレ−シヨン 多層パネル盤
JPH0574532A (ja) * 1990-01-18 1993-03-26 Kel Corp 電気コネクタ
JPH05226524A (ja) * 1991-11-26 1993-09-03 Hitachi Ltd 電子機器の実装装置
JPH05315029A (ja) * 1992-05-13 1993-11-26 Hitachi Ltd 電子部品実装装置
JPH0837255A (ja) * 1994-07-22 1996-02-06 Hitachi Ltd 半導体装置用ソケット

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06180343A (ja) * 1992-12-14 1994-06-28 Minato Electron Kk Ｉｃ測定装置用テストボード
JPH08271579A (ja) * 1995-03-30 1996-10-18 Fujitsu Ltd Ｉｃソケット及びそれを用いたｉｃ試験方法
JPH09219267A (ja) * 1996-02-07 1997-08-19 Sony Corp Ｂｇａ・ｉｃ試験用コンタクト・ソケット
JP4082750B2 (ja) * 1996-04-01 2008-04-30 スリーエム カンパニー Ｉｃソケット
JPH09283247A (ja) * 1996-04-04 1997-10-31 Minnesota Mining & Mfg Co <3M> Ｉｃソケット
JPH1038972A (ja) * 1996-07-26 1998-02-13 Ricoh Co Ltd テスト用ｉｃソケット
KR19990081438A (ko) * 1998-04-29 1999-11-15 조성환 집적회로장치용 번인 테스트 보드

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58129792A (ja) * 1982-01-28 1983-08-02 ミユ−パツク・コ−ポレ−シヨン 多層パネル盤
JPH0574532A (ja) * 1990-01-18 1993-03-26 Kel Corp 電気コネクタ
JPH05226524A (ja) * 1991-11-26 1993-09-03 Hitachi Ltd 電子機器の実装装置
JPH05315029A (ja) * 1992-05-13 1993-11-26 Hitachi Ltd 電子部品実装装置
JPH0837255A (ja) * 1994-07-22 1996-02-06 Hitachi Ltd 半導体装置用ソケット

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1115129A3 (fr) * 1999-12-28 2006-06-07 TDK Corporation Condensateur multicouche
EP1115129A2 (fr) * 1999-12-28 2001-07-11 TDK Corporation Condensateur multicouche
US6791846B2 (en) 2000-10-30 2004-09-14 Sun Microsystems, Inc. Power distribution system with a dedicated power structure and a high performance voltage regulator
US7162795B2 (en) 2000-10-30 2007-01-16 Sun Microsystems, Inc. Power distribution system with a dedicated power structure and a high performance voltage regulator
WO2002076162A1 (fr) * 2001-03-16 2002-09-26 Sun Microsystems, Inc. Systeme de distribution de puissance a structure de puissance specifique comprenant des ouvertures permettant le montage de boitiers de circuit integre
US6760232B2 (en) 2001-03-16 2004-07-06 Sun Microsystems, Inc. Power distribution system having a dedicated power structure with apertures for mounting integrated circuit packages
US7446545B2 (en) 2003-05-08 2008-11-04 Unitechno Inc. Anisotropically conductive sheet
JP2009230897A (ja) * 2008-03-19 2009-10-08 Fujitsu Ltd 電子部品接合装置、電子ユニット、および電子装置
US8556638B2 (en) 2008-09-04 2013-10-15 3M Innovative Properties Company Electronic device socket
WO2010027597A2 (fr) 2008-09-04 2010-03-11 3M Innovative Properties Company Douille de dispositif electronique
JP2010062045A (ja) * 2008-09-04 2010-03-18 Three M Innovative Properties Co 電子デバイス用ソケット
JP2011075313A (ja) * 2009-09-29 2011-04-14 Three M Innovative Properties Co Ｉｃデバイス検査用ソケット
US8957693B2 (en) 2009-09-29 2015-02-17 3M Innovative Properties Company IC device testing socket
JP2011252766A (ja) * 2010-06-01 2011-12-15 3M Innovative Properties Co 接触子ホルダ
US8911266B2 (en) 2010-06-01 2014-12-16 3M Innovative Properties Company Contact holder
JP2016153796A (ja) * 2016-03-31 2016-08-25 スリーエム イノベイティブ プロパティズ カンパニー Ｉｃデバイス検査用ソケット
EP3340747A1 (fr) * 2016-12-22 2018-06-27 Google LLC Support de circuit intégré multicouche comportant un réseau d'adaptation d'impédance intégré
KR20190117017A (ko) * 2017-02-24 2019-10-15 테크노프로브 에스.피.에이. 향상된 주파수 특성을 갖는 수직 프로브 테스트 헤드
JP2020509371A (ja) * 2017-02-24 2020-03-26 テクノプローべ ソシエタ ペル アチオニ 改善された周波数特性を有する垂直プローブ試験ヘッド
KR102522522B1 (ko) * 2017-02-24 2023-04-14 테크노프로브 에스.피.에이. 향상된 주파수 특성을 갖는 수직 프로브 테스트 헤드
JP2018009994A (ja) * 2017-08-04 2018-01-18 スリーエム イノベイティブ プロパティズ カンパニー Ｉｃデバイス用ソケット
JP2018021914A (ja) * 2017-08-04 2018-02-08 スリーエム イノベイティブ プロパティズ カンパニー Ｉｃデバイス用ソケット
JP2020008546A (ja) * 2018-07-02 2020-01-16 力成科技股▲分▼有限公司 試験ソケットおよび試験装置

Also Published As

Publication number Publication date
TW456074B (en) 2001-09-21
CN1262800A (zh) 2000-08-09
KR20010006503A (ko) 2001-01-26

Similar Documents

Publication Publication Date Title
WO1999041812A1 (fr) Support de circuit integre
US7345366B2 (en) Apparatus and method for testing component built in circuit board
US4764723A (en) Wafer probe
KR100757577B1 (ko) 고대역폭 수동 집적회로 시험기 탐침 카드 조립체
JP5960383B2 (ja) 接触子ホルダ
KR100363652B1 (ko) 다층 커패시터, 배선기판, 감결합 회로 및 고주파 회로
US6686732B2 (en) Low-cost tester interface module
JP3376731B2 (ja) 高周波用のプリント基板及びこれを用いたプローブカード
US4928061A (en) Multi-layer printed circuit board
TWI678540B (zh) 半導體元件測試載具
KR100543853B1 (ko) 확장 표면 랜드를 갖는 커패시터 및 그 제조 방법
US5194932A (en) Semiconductor integrated circuit device
US6519134B1 (en) Universal capacitor terminal design
US6967557B2 (en) Wafer test space transformer
WO2021133561A1 (fr) Agencement de trou d&#39;interconnexion coaxial dans une carte sonde destinée à un équipement d&#39;essai automatisé
WO2021133560A1 (fr) Agencement transposé de trous d&#39;interconnexion dans une carte sonde pour équipement de vérification automatique
US6859352B1 (en) Capacitor sheet
US6646888B2 (en) Low inductance multiple resistor EC capacitor pad
JP4045841B2 (ja) プローブカード
JP3436183B2 (ja) 半導体検査装置およびそれを用いた検査方法
JP2584908Y2 (ja) プローバのアタッチメントボード
JP2000314745A (ja) プローブ先端構成

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 99800359.X

Country of ref document: CN

AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR SG US

WWE Wipo information: entry into national phase

Ref document number: 1019997009593

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 09403120

Country of ref document: US

WWP Wipo information: published in national office

Ref document number: 1019997009593

Country of ref document: KR

WWR Wipo information: refused in national office

Ref document number: 1019997009593

Country of ref document: KR