WO1998056060A1 - Commutateur a deux frequences, dispositif utilisant une antenne a deux frequences commune, et equipement de radiocommunication mobile pour deux bandes de frequence, utilisant ledit dispositif - Google Patents
Commutateur a deux frequences, dispositif utilisant une antenne a deux frequences commune, et equipement de radiocommunication mobile pour deux bandes de frequence, utilisant ledit dispositif Download PDFInfo
- Publication number
- WO1998056060A1 WO1998056060A1 PCT/JP1998/002428 JP9802428W WO9856060A1 WO 1998056060 A1 WO1998056060 A1 WO 1998056060A1 JP 9802428 W JP9802428 W JP 9802428W WO 9856060 A1 WO9856060 A1 WO 9856060A1
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- terminal
- circuit
- frequency
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- frequency switch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/10—Auxiliary devices for switching or interrupting
- H01P1/15—Auxiliary devices for switching or interrupting by semiconductor devices
Definitions
- Dual-frequency switch, dual-frequency antenna duplexer, and dual-frequency band mobile communication device using the same
- the present invention relates to a dual-frequency switch, a dual-frequency antenna duplexer, and a dual-frequency band mobile communication device using the dual-frequency switch, which is mainly used for mobile communication such as a mobile phone.
- this kind of conventional high-frequency switch is known as disclosed in Japanese Patent Application Laid-Open No. Hei 7-321692.
- the circuit configuration is composed of a parallel connection of a PIN diode 1001 and its compensation circuit 1002, and this compensation circuit 1002 is composed of a capacitor 1003 And Ink 1004 are connected in series.
- the compensation circuit 1002 sets the switch circuit to the 0FF state when the PIN diode 1001 is not conducting, and reduces the parasitic capacitance of the PIN diode 1001 when not conducting.
- the inductor 1004 is set so as to cancel and resonate in a desired band.
- the capacitor 1003 is a so-called DC cut element for cutting off the DC current path of the compensation circuit when the PIN diode 1001 becomes conductive and the switch circuit is brought to the 0N state.
- the compensation circuit 1002 is capacitive at frequencies near the direct current and inductive at the desired band. It becomes a circuit having a dance and having one series resonance point between them.
- the present invention has been made to solve the above problems, and has as its object to realize a two-frequency switch capable of obtaining a sufficient 0 FF state in two bands with a simple configuration. Disclosure of the invention
- the present invention comprises a parallel connection of a diode and its compensation circuit, and the compensation circuit is constituted by a circuit having at least two series resonance points and one parallel resonance point.
- the impedance of the compensation circuit which is capacitive at low frequencies near DC, becomes inductive through the first series resonance point, and cancels the parasitic capacitance of the diode in the first band. At the same time, it becomes inductive again from the parallel resonance point to the next series resonance point, and again in the second band, Since the parasitic capacitance can be canceled, a two-frequency switch that can obtain a sufficient 0FF state in two bands with a simple configuration can be realized.
- FIG. 1 is a circuit diagram of a dual-frequency switch according to the first embodiment
- FIG. 2 is a diagram showing a frequency characteristic of a reactance when the dual-frequency switch is turned off
- FIG. 3 is a dual-frequency switch.
- FIG. 4 is a diagram showing transmission characteristics of the switch
- FIG. 4 is a circuit diagram showing another example of the configuration of the dual-frequency switch in the first embodiment of the present invention
- FIG. 5 is a dual-frequency switch in the second embodiment of the present invention.
- FIG. 6 is a diagram showing transmission characteristics of the dual-frequency switch
- FIG. 7 is a circuit diagram of the dual-frequency switch according to the third embodiment of the present invention
- FIG. 8 is a dual-frequency switch.
- FIG. 9 is a diagram showing the impedance characteristic of the switch when the second switch is OFF
- FIG. 9 is a diagram showing the transmission characteristics of the same two-frequency switch
- FIG. 10 is a diagram showing the fourth embodiment of the present invention.
- Circuit diagram of dual-frequency antenna duplexer Fig. 11 shows transmission characteristics on the transmitting side of dual-frequency antenna duplexer
- Fig. 12 shows dual-frequency antenna. Shows the transmission characteristics of the receiving use device, the first FIG. 3 is a circuit diagram of a conventional high-frequency scan I pitch.
- FIG. 1 shows a two-frequency switch according to the first embodiment of the present invention.
- the two-frequency switch is composed of a parallel connection of a PIN diode 101 and its compensating circuit 102
- the compensating circuit 102 is composed of a first capacitor 103 and a first capacitor 103. It is composed of a series connection of a series resonance circuit consisting of an inductor 104 and a parallel resonance circuit consisting of a second capacitor 105 and a second inductor 106.
- the impedance of the compensation circuit 102 is capacitive at a low frequency near DC where the effect of the first capacitor 103 is dominant.
- the combined impedance of the first inductor 104, the second capacitor 105, and the second inductor 106 and the series resonance formed by the first capacitor 103 After the point, the impedance of the compensation circuit 102 becomes inductive, cancels the parasitic capacitance of the PIN diode 101 when it is not conducting in the first band, and the switch is sufficient. 0FF state.
- the impedance of the compensation circuit 102 becomes capacitive again, and After the combined impedance of the capacitor 103 and the first inductor 104 and the series resonance point formed by the parallel resonance circuit, the impedance of the compensation circuit 102 becomes inductive again. In the second band, the parasitic capacitance of the PIN diode 101 at the time of non-conduction is canceled, and the switch is turned to the sufficient 0FF state again.
- the first capacitor 103 has a PIN diode 101 When the switch is turned on and enters the 0 N state, it acts as a so-called DC power cut element for cutting off the DC current path of the compensation circuit 102.
- FIG. 2 is a characteristic diagram showing a reactance characteristic of the dual-frequency switch according to the present embodiment at the time of OFF.
- XI in the figure is the reactance due to the parasitic capacitance of the PIN diode 101 when not conducting, and X2 is the reactance of the compensation circuit 102 .
- the parasitic capacitance is canceled by connecting circuits having the same absolute value and opposite polarities in parallel, so that two series resonance points r 1 and r 2 and one parallel resonance point a 1
- By connecting the compensating circuits 102 in parallel with each other it is possible to cancel the parasitic capacitance at the two frequencies of the first band Ml and the second band M2 in the figure. .
- the transmission characteristics of this two-frequency switch are as shown in Fig. 3. That is, the input loss when the switch is ON is 0.5 dB or less in the entire band, and the isolation when the switch is OFF is in the first band Ml (890 to 960 MHz). z) and in the second band M 2 (171 0 to 188 MHz), more than 25 dB is obtained.
- this embodiment operates as a two-frequency switch capable of obtaining a sufficient OFF state in two bands.
- the compensating circuit 102 in the present embodiment is constituted by a series connection composed of a series resonance circuit and a parallel resonance circuit, but this is a parallel connection composed of two series resonance circuits as shown in FIG. It may be composed of a connector. That is, the two series resonant circuits are respectively connected to the first capacitor 403 and the first inductor 404, and the second capacitor 405 and the second inductor 406. More composed These are connected in parallel to form the compensation circuit 102.
- This circuit shows another configuration method that is capacitive at low frequencies near DC and has two series resonance points and one parallel resonance point.
- the compensation circuit in FIG. 4 is obtained by converting the compensation circuit 102 in FIG. 1, and is equivalent in circuit. Therefore, the impedance characteristics are the same as in Fig. 2 and the transmission characteristics are the same as in Fig. 3. In this configuration as well, a two-frequency switch capable of obtaining a sufficient OFF state in the two bands M1 and M2 is provided. Can be realized.
- a piezo circuit composed of a resistor for making the PIN diode conductive, an inductor, and a pi bus capacitor, and a dc current external to each terminal.
- the present invention is not limited to these numerical values and details of the configuration.
- a high-frequency switch circuit of the terminal can be configured with a simple circuit, and the terminal can be configured. It can be small and lightweight.
- FIG. 5 shows a two-frequency switch according to the second embodiment of the present invention.
- a first PIN diode 701 is connected between the first terminal 707 and the common terminal 708, and a first PIN diode 701 is connected between the second terminal 709 and the common terminal 708. Is connected to the second PIN diode 710, and both PIN diodes are connected to the common terminal 708 Have been.
- a first compensating circuit 702 is formed by a series connection with the resonant circuit, and this is connected in parallel to a first PIN diode 701 to form a first switch 717. ing.
- a second compensating circuit 711 is formed by a series connection with the parallel resonance circuit, and this is connected in parallel to a second PIN diode 710 to form a second switch 718. are doing.
- a choke coil 716 is connected between the common terminal 708 and the ground.
- the second PIN diode 7 10 When a DC current is applied to the first switch 7 17 to turn it on, the second PIN diode 7 10 is in the opposite direction, and the second compensation circuit 7 11 Since the capacitor 712 of the capacitor cuts the DC component, all the DC current flows to the check coil 716, and the second switch 718 becomes the 0FF state. Also, as described in the first embodiment, the second compensation circuit 711 cancels the parasitic capacitance of the second PIN diode 710 in the two bands (M l, M 2). However, in these bands, the impedance when the second switch 718 is viewed from the common terminal 708 becomes extremely high. This result As a result, in the two bands, the signal input from the first terminal 707 is output only to the common terminal 708 and not output to the second terminal 709.
- the first PIN diode 70 1 is in the opposite direction, and the first compensation circuit 70 0 In No. 2, since the first capacitor 703 cuts the DC component, all the DC current flows to the tie coil 716, and the first switch 717 is turned off. Also, the first compensating circuit 702 cancels the parasitic capacitance of the first PIN diode 71 in two bands (Ml, M2), so that the common terminal 70 The impedance of the first switch 7 17 from 8 becomes extremely high, and as a result, the signal input from the common terminal 708 in the two bands is output only to the second terminal 709. It is not output to the first terminal 707.
- the first switch 717 and the second switch 718 are individually set to the 0 N state, and thus two bands (M l, A two-frequency SPDT switch operating on M 2) can be realized.
- FIG. 6 is a characteristic diagram showing the transmission characteristics of this dual frequency SPDT switch.
- the transmission characteristic from the first terminal 707 to the common terminal 708 is such that when the first switch 717 is 0 N, the insertion loss is 0 in the first band M1 and the second band M2. 5 dB or less, and when the first switch 7 17 is OFF, an isolation of 25 dB or more is also obtained at Ml and M2.
- the transmission characteristic from the common terminal 708 to the second terminal 709 is determined by the second switch 711 Is 0 N, the insertion loss in the first band M 1 and the second band M 2 is 5 dB or less, and when the second switch 7 18 is OFF, M l, In M2, an isolation of 25 dB or more can be obtained.
- the first switch 717 and the second switch 718 are constituted by the circuit shown in FIG. 1, but this is constituted by the circuit shown in FIG. Is also good.
- a bias circuit including a resistor for making the PIN diode conductive, an inductor, and a pino capacitor is required for each switch.
- a DC cut capacitor is required to prevent DC current from flowing outside each terminal, but the present invention is not limited to these numerical values and details of the configuration.
- a high-frequency switch circuit of the terminal can be configured with a simple circuit, and the terminal can be configured. It can be small and lightweight.
- FIG. 7 shows a two-frequency switch according to the third embodiment of the present invention.
- the first switch 827 is the first switch 717 of the second embodiment shown in FIG. Since the configuration is the same as that described above, the same portions are denoted by the same reference numerals and detailed description is omitted.
- one end of a first switch 827 is connected to a common terminal 708, and one end of a third capacitor 817 and a third inductor 8 One end of 18 is connected, and the other end of the third capacitor 8 17 is grounded.
- the other end of the third inductor 818 is connected to one end of the fourth capacitor 819, one end of the fourth inductor 820 and the second PIN diode 822.
- the node is connected, and the other end of the fourth capacitor 819 is grounded.
- the other end of the fourth inductor 820 becomes the second terminal 709, and one end of the fifth capacitor 821 and the anode of the third PIN diode 826 And the other end of the fifth capacitor 821 is grounded.
- the force source of the second PIN diode 82 is connected to one end of a second compensation circuit 82 composed of a parallel resonance circuit of a sixth capacitor 82 and a fifth inductor 82. Are connected, and the other end of the second compensation circuit 823 is grounded.
- the power source of the third PIN diode 826 is grounded.
- the third capacitor 81 7, the third inductor 8 18 and the fourth capacitor 8 19 constitute a first phase shift circuit 8 29, and the fourth capacitor 8 19
- the fourth inductor 82 0 and the fifth capacitor 8 21 constitute a second phase shift circuit 8 30.
- the first phase shift circuit 82 9 is set to have a phase of about 90 ° in the second band (M 2 in the second embodiment), and the first phase shift circuit 82 9
- the sum of the phase of 9 and the phase of the second phase shift circuit 830 is about 90 ° in the first band (M 1 in the second embodiment). It is set as follows.
- the second compensation circuit 8 23 enters a parallel resonance state in the first band M 1, and enters a series resonance state with the second PIN diode 8 22 during conduction in the second band M 2. It is set to be
- the first switch 827 When a bias is applied in the forward direction of the first PIN diode 701 and a direct current flows, the first switch 827 is in the 0 N state as described in the first embodiment. At this time, the DC current flows into the second PIN diode 822 and the third PIN diode 826, and both are brought into conduction.
- the conducting second PIN diode 822 and the second compensating circuit 823 are in series resonance, and the first phase shifting circuit 8 Since the phase is rotated by 90 °, the impedance when the second switch 8288 side is viewed from the common terminal 708 is a high impedance.
- the second PIN diode 822 can be ignored in high frequency because the second compensation circuit 823 is in a parallel resonance state. Since the sum of the phase of the phase shift circuit 829 and the phase of the second phase shift circuit 830 is 90 °, the second switch 828 is connected from the common terminal 7 08 to the second switch 8 2 8 side. The impedance that has been seen becomes a high impedance state.
- FIG. 8 shows the impedance characteristic when the second switch 8288 side is viewed from the common terminal 708 at this time. In FIG. 8, the area between marker 1 and marker 2 is the first band Ml (890 to 960 MHz), and marker 3 and marker 1 Between the force 4 is the second band M2 (1710 to 1880 MHz).
- the first switch 827 is set to 0 in the first band Ml and the second band M2 as described in the first embodiment.
- the impedance when the first switch 827 is viewed from the common terminal 708 becomes a high impedance in these two bands.
- the second PIN diode 822 and the third PIN diode 826 are both in a non-conductive state, and the second switch 828 is in the first phase shift state. Since only the circuit 829 and the second phase shift circuit 830 are provided, the signal from the common terminal 708 is directly transmitted to the second terminal 709. As a result, the second switch 828 is in the ON state.
- FIG. 9 is a characteristic diagram showing the transmission characteristics of the two-frequency SPDT switch.
- the transmission characteristic from the first terminal 707 to the common terminal 708 is such that when the bias is N, the insertion loss is 0.5 dB or less in the first band M1 and the second band M2. In the case of the bias 0 FF, an isolation of 25 dB or more is obtained for Ml and M2.
- the transmission characteristic from the common terminal 708 to the second terminal 709 is less than 0.5 dB in the first band M 1 and the second band M 2 when the bias is 0 FF. In the case of bias 0 N, the isolation is also 25 M dB at Ml and M 2. The above is obtained.
- the first PIN diode 70 1, the second PIN diode 82 2, and the third PIN diode 82 26 are simultaneously in a conductive state or a non-conductive state.
- a two-frequency SPDT switch that operates in two bands, M1 and M2 can be realized.
- This dual frequency SPDT switch requires only one bias circuit, and does not need to supply a DC current when the second switch 828 is ON, so the current consumption is kept low.
- the first switch 827 in the present embodiment is constituted by the circuit shown in FIG. 1, it may be constituted by the circuit shown in FIG.
- first phase shift circuit 829 and the second phase shift circuit 830 in the present embodiment are composed of a lumped constant element capacitor and an inductor. It may be formed by a transmission line. In this case, the number of elements can be reduced and the phase shift circuit can be ideally configured.
- the force source of the third PIN diode 826 in the present embodiment is directly grounded, but this is via a compensation circuit consisting of a parallel resonance circuit composed of a capacitor and an inductor. It may be grounded.
- the third PIN diode 826 when the third PIN diode 826 is turned on, the connection point between the second phase shift circuit 830 and the third PIN diode 826 is set to a sufficiently low impedance state. There is an effect that can be.
- the dual frequency SPDT switch Requires a bias circuit consisting of a resistor, a inductor, and a bypass capacitor to set the PIN diode to the 0 N state, and also to prevent DC current from flowing outside each terminal.
- a DC cut capacitor is required, the invention is not limited to these numbers or configuration details.
- the high-frequency switch circuit of the terminal can be configured with a simple circuit, Can be small and lightweight.
- FIG. 10 shows a dual-frequency antenna duplexer according to Embodiment 4 of the present invention.
- the dual-frequency switch 900 of the dual-frequency antenna duplexer of Embodiment 4 of the present invention shown in FIG. 10 has the same configuration as the dual-frequency switch 900 of Embodiment 3 shown in FIG. Therefore, detailed circuit diagrams and descriptions are omitted.
- the output terminal 902 of the synthesizer 901 is connected to the first terminal 707 of the dual-frequency switch 900 by a DC power capacitor 91.
- the input terminal 906 of the second duplexer 905 is connected to the second terminal 709 via a DC cut capacitor 912. Further, a control terminal 909 for inputting a control signal to the dual-frequency switch 900 and a bias circuit 910 are provided to constitute a dual-frequency antenna duplexer.
- the combiner 90 1 transmits the transmission signal of the first band M 1 input from the first transmission side terminal 90 3 to the output terminal 90 2, and also transmits the second transmission side terminal 90 2 Second input from 4 It also has a function of transmitting a transmission signal of the band M2 to the output terminal 902.
- One demultiplexer 905 transmits the received signal of the first band Ml input from the input terminal 906 to the first receiving terminal 907, and the same as the input terminal. It has a function of transmitting the reception signal of the second band M2 input from the 906 to the reception terminal 908.
- the path from the first transmitting terminal 903 to the output terminal 902 has a four-element path in order to pass through the first band M1 and block the second band M2. It is a ladder-type low-pass filter, and the path from the second transmitting terminal 904 to the output terminal 902 blocks the first band M1 and the second band M2 It is a ladder-type high-pass filter with four elements to pass through.
- the transmission signal of the first band Ml input from the first transmission terminal 903 is transmitted to the output terminal 902 without leaking to the second transmission terminal 904.
- the transmission signal of the second band M2 input from the second transmission terminal 904 is transmitted to the output terminal 902 without leaking to the first transmission terminal 903.
- the demultiplexer 905 may use the synthesizer 901 in the opposite direction, and the configuration is exactly the same.
- the received signal input from the input terminal 906 receives the component of the first band Ml to the first receiving terminal 907 and the component of the second band M2 to the second receiving terminal 907.
- the signal is branched to the side terminal 908, and none of them leaks to the other.
- the transmission signal of each band does not leak to the other transmission side terminal by the function of the synthesizer 9001, and the first reception is performed by the function of the dual-frequency switch 900. There is no leakage to the side terminal 907 and the second receiving terminal 908.
- the bias of the control terminal 909 is released, and the state between the common terminal 708 and the second terminal 709 of the dual-frequency switch 900 is turned on.
- the received signal input from the common terminal 708 passes through the second terminal 709 of the dual-frequency switch 900, and the first band M
- the signal component of 1 can be output to the first receiving terminal 907, and the signal component of the second band M2 can be output to the second receiving terminal 908.
- the received signal of each band does not leak to the other receiving terminal by the function of the duplexer 905, and the function of the two-frequency switch 900 causes the first transmitting terminal 9 There is no leakage to 03 and the second transmitting terminal 904.
- FIG. 11 and FIG. 12 are characteristic diagrams showing the transmission characteristics of the dual-frequency antenna duplexer.
- the first band M1 is set to 890 to 960 MHz
- the second band M2 is set to 1710 to: L880 MHz.
- the first transmitting terminal 9 0 3 The transmission characteristics from the first band to the common terminal 708 are as follows: During transmission, the first band M1 has an insertion loss of 1 dB or less and the second band has an attenuation of 25 dB or more.
- the transmission signal of M1 is transmitted to the common terminal 708. At the time of reception, an isolation of 25 dB or more is obtained in any band.
- the transmission characteristic from the second transmitting terminal 904 to the common terminal 708 is, as shown in FIG. 11 (b), an attenuation of 25 dB in the first band M1 during transmission.
- the insertion loss is equal to or less than ldB in the second band M2, and the transmission signal in the second band M2 is transmitted to the common terminal 708.
- the isolation at the time of reception is 25 dB or more in any band.
- the transmission characteristic from the common terminal 708 to the first receiving terminal 907 is, as shown in FIG. 12 (a), an insertion loss of 1 dB in the first band M1 during reception.
- the attenuation in the second band M2 is equal to or more than 25 dB, and the received signal of the first band Ml input from the common terminal 708 is transmitted to the first receiving terminal 90. 7 is to be transmitted. In transmission, an isolation of 25 dB or more is obtained in any band.
- the transmission characteristic from the common terminal 708 to the second receiving terminal 908 is, as shown in FIG. 12 (b), the attenuation 25 dB in the first band Ml during reception.
- the insertion loss in the second band M2 is 1 dB or less, and the reception signal of the second band M2 input from the common terminal 708 is transmitted to the second reception terminal 908. It is supposed to be done.
- the dual-frequency antenna duplexer of the present invention is composed of the system of the first band Ml and the system of the first band Ml. It has characteristics that make it suitable as an antenna duplexer for portable terminals compatible with complex systems that handles systems with a bandwidth of M2.
- both the combiner 901 and the duplexer 905 are composed of a composite circuit of a low-pass filter and a high-pass filter, but unnecessary frequency components are eliminated. Some or all of them may be configured with bandpass filters to remove them. For example, on the transmitting side, harmonics of signal components often pose a problem, but high-pass filters cannot eliminate this problem. Therefore, the synthesizer may be configured as a band-pass filter. On the receiving side, on the other hand, it is necessary to remove the local frequency image frequency and the like during frequency conversion in addition to the harmonic components, so that the duplexer is divided into a band-pass filter and a band-pass filter. A complex circuit may be used to remove unnecessary high and low frequency components of the signal component.
- the configuration of the third embodiment is used as the dual-frequency switch 900, but the configuration of the second embodiment may be used as well.
- two control terminals and two bypass circuits are required, and one of them is always biased, which increases current consumption.However, only two PIN diodes are used, which is very simple. Circuit configuration.
- the antenna duplexer of the terminal can be configured with a simple circuit, and the terminal is small and lightweight. Can be.
- the present invention provides a dual-frequency switch composed of a parallel connection of a diode and its compensation circuit, wherein the compensation circuit is composed of a circuit having at least two series resonance points and one parallel resonance point. It is something to be called.
- the impedance of the compensation circuit which is capacitive at low frequencies near DC, becomes inductive through the first series resonance point, canceling the parasitic capacitance of the diode in the first band.
- the parallel resonance point passes through the next series resonance point, becomes inductive again, and the parasitic capacitance of the PIN diode can be canceled again in the second band.
- a two-frequency switch capable of obtaining a state can be configured with one PIN diode, and a small and inexpensive two-frequency switch can be realized.
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/242,139 US6496083B1 (en) | 1997-06-03 | 1998-06-02 | Diode compensation circuit including two series and one parallel resonance points |
EP98923080A EP0928038B1 (en) | 1997-06-03 | 1998-06-02 | Two-frequency switch, device using two-frequency antenna in common, and mobile radio communication equipment for two-frequency bands using the device |
CNB988005883A CN100386917C (zh) | 1997-06-03 | 1998-06-02 | 双频带开关 |
DE69835937T DE69835937T2 (de) | 1997-06-03 | 1998-06-02 | Zweifrequenzschalter, anordnung mit gemeinsamer zweifrequenzantenne und mobile zweifrequenz-funkübertragungsausrüstung damit |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14486397 | 1997-06-03 | ||
JP9/144863 | 1997-06-03 | ||
JP13163898A JP3220679B2 (ja) | 1997-06-03 | 1998-05-14 | 2周波スイッチ、2周波アンテナ共用器およびそれを用いた2周波帯域用移動体通信機器 |
JP10/131638 | 1998-05-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998056060A1 true WO1998056060A1 (fr) | 1998-12-10 |
Family
ID=26466417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1998/002428 WO1998056060A1 (fr) | 1997-06-03 | 1998-06-02 | Commutateur a deux frequences, dispositif utilisant une antenne a deux frequences commune, et equipement de radiocommunication mobile pour deux bandes de frequence, utilisant ledit dispositif |
Country Status (6)
Country | Link |
---|---|
US (1) | US6496083B1 (ja) |
EP (1) | EP0928038B1 (ja) |
JP (1) | JP3220679B2 (ja) |
CN (1) | CN100386917C (ja) |
DE (1) | DE69835937T2 (ja) |
WO (1) | WO1998056060A1 (ja) |
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- 1998-06-02 DE DE69835937T patent/DE69835937T2/de not_active Expired - Fee Related
- 1998-06-02 WO PCT/JP1998/002428 patent/WO1998056060A1/ja active IP Right Grant
- 1998-06-02 US US09/242,139 patent/US6496083B1/en not_active Expired - Fee Related
- 1998-06-02 EP EP98923080A patent/EP0928038B1/en not_active Expired - Lifetime
- 1998-06-02 CN CNB988005883A patent/CN100386917C/zh not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
JP3220679B2 (ja) | 2001-10-22 |
EP0928038B1 (en) | 2006-09-20 |
US6496083B1 (en) | 2002-12-17 |
CN1225751A (zh) | 1999-08-11 |
EP0928038A4 (en) | 2001-05-30 |
JPH1155002A (ja) | 1999-02-26 |
DE69835937D1 (de) | 2006-11-02 |
EP0928038A1 (en) | 1999-07-07 |
CN100386917C (zh) | 2008-05-07 |
DE69835937T2 (de) | 2007-01-04 |
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