WO1997031394A1 - Dispositif semi-conducteur et son procede de fabrication - Google Patents

Dispositif semi-conducteur et son procede de fabrication Download PDF

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Publication number
WO1997031394A1
WO1997031394A1 PCT/JP1997/000473 JP9700473W WO9731394A1 WO 1997031394 A1 WO1997031394 A1 WO 1997031394A1 JP 9700473 W JP9700473 W JP 9700473W WO 9731394 A1 WO9731394 A1 WO 9731394A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
lead frame
metal foil
resin
adhesive
Prior art date
Application number
PCT/JP1997/000473
Other languages
English (en)
Japanese (ja)
Inventor
Shinichi Oizumi
Yuji Hotta
Seiji Kondo
Original Assignee
Nitto Denko Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corporation filed Critical Nitto Denko Corporation
Priority to US09/125,523 priority Critical patent/US6144108A/en
Priority to EP97903588A priority patent/EP0883170A4/fr
Publication of WO1997031394A1 publication Critical patent/WO1997031394A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J179/00—Adhesives based on macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing nitrogen, with or without oxygen, or carbon only, not provided for in groups C09J161/00 - C09J177/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Definitions

  • the present invention relates to a semiconductor device in which a semiconductor element is sealed with a resin, and relates to a thin and large-sized semiconductor device which is excellent in heat radiation and soldering heat resistance and does not warp, and a method of manufacturing the same.
  • semiconductor devices such as transistors, 1Cs, and LSIs have been encapsulated into ceramic devices using ceramic packages, but from the viewpoint of cost and mass productivity, semiconductor devices using resin encapsulation have been used.
  • resin encapsulation has become mainstream.
  • Epoxy resins have been used for this type of resin encapsulation, and have achieved good results.
  • the degree of integration is increasing and the size of semiconductor elements is increasing due to technological innovation in the semiconductor field, there is a strong demand for smaller and thinner semiconductor devices.
  • the volume ratio occupied by the sealing resin material has decreased, and the thickness of the sealing resin portion has become thinner.As a result, the semiconductor device is easily warped, and connection troubles occur when the semiconductor device is mounted on a substrate. Easy.
  • the warpage was remarkable in ultra-thin semiconductor devices of 1.5 mm or less.
  • the encapsulation resin is subject to thermal stress generated during the thermal cycle test (TCT), an accelerated test for evaluating the performance of the encapsulation resin. Improvement in crack resistance is desired more than ever.
  • surface mounting has become the mainstream mounting method for semiconductor devices. Therefore, even if the semiconductor device is immersed in solder while absorbing moisture, cracking or swelling of the semiconductor device does not occur. Although solderability is also required, in this case, solder heat resistance higher than before is also required.
  • the degree of ripening generated in semiconductor devices tends to increase with higher integration, and the heat generated during operation is accumulated inside the semiconductor device. The junction temperature of the semiconductor device exceeds the junction temperature, resulting in functional failure That thing was .:
  • thermal stress has conventionally been achieved by modifying the epoxy resin with a silicon compound or adding rubber fine particles as a semiconductor encapsulation resin to improve the properties evaluated by TCT. It is being studied to reduce this.
  • the improvement of the adhesion between the lead frame and the sealing resin and the selection of a low moisture absorbing sealing resin have been studied. Not enough yet.
  • a metal pad is attached to a die pad for fixing a semiconductor element. It has been proposed that the foil be used to dissipate heat using the gold foil.
  • Japanese Patent Application Laid-Open No. 63-187652 discloses that a metal foil is bonded to one or both surfaces of a semiconductor device.
  • the adhesive layer to be bonded generally has large hygroscopicity, and the effect of improving the solder heat resistance is reduced. Further, in a thin semiconductor device that has been frequently used in recent years, the semiconductor device may be warped.
  • the present invention provides a semiconductor device that is excellent in moisture resistance, solder heat resistance during solder immersion, and heat stress resistance, and has high heat dissipation and no warpage even if the semiconductor device is thinned to 5 mm or less.
  • the task is to provide equipment. Disclosure of the invention
  • the present invention relates to the following semiconductor devices and methods for manufacturing the same.
  • a metal foil is adhered via an adhesive to the back side of a lead frame on which the semiconductor element is mounted, and the semiconductor element side
  • a gold foil is fixed to an outer surface of a sealing resin.
  • the gold foil adhered to the outer surface of the encapsulating resin on the semiconductor element side is characterized in that the solid-identifiable organic layer is the outermost layer and is depressed and fixed by the thickness of the organic layer.
  • a method for manufacturing a semiconductor device comprising: setting a lead frame, setting the lead frame, clamping a die, bonding a metal foil to the lead frame, and injecting and molding a resin.
  • FIG. 1 is a cross-sectional view showing one structure of an element-sealed resin-sealed semiconductor device of the present invention.
  • FIG. 2 is a cross-sectional view showing another structural example of the present invention.
  • FIG. 3 is a time-dependent explanatory diagram when the semiconductor device of Example 1 is manufactured.
  • the metal layer 3 is set on the lower mold 2 with the adhesive 4 facing upward, and the metal layer 3 is set.
  • Fig. 5 shows the state where 5 is set in the upper mold by the temporary fixing organic layer 6,
  • B the figure showing the state where the lead frame 8 on which the semiconductor element is mounted is set, and
  • the mold is closed.
  • FIG. 4 is a view showing a state in which a lead frame 8 and a gold foil 3 are bonded via an adhesive 4
  • FIG. 4D is a view showing a down state in which a sealing resin 10 is injected and molded.
  • a metal foil 3 is bonded via an adhesive 4 to the back side of a lead frame 8 on which a semiconductor element 7 is mounted, and A metal foil 5 having an organic layer 6 having a solid identification function is fixed to the outer surface of the sealing resin.
  • Li one Zadoff frame used in the present invention is the linear expansion coefficient of 0. 4 ⁇ 0 8 X 1 0 5 Bruno Te iron -.. Nickel alloys or, and the linear expansion coefficient 6 ⁇ 1 8 X 1 0 5 / A copper alloy of ° C is used and a thickness of 0.1 to 0.25 m is generally used.
  • the die pad for fixing the semiconductor element 7 is removed and the The case where the semiconductor element is used by directly fixing the semiconductor element to a gold foil adhered to the back side of the frame is also included in the scope of the present invention.
  • Metal ⁇ which is adhered to the back side of Lee Zadoff frame is a metal foil linear expansion coefficient of 0. 4 ⁇ 2. 7 X 1 0- 5 / ° C is used.
  • the metal used at this time has a thickness of 1 to 100 // ⁇ , preferably 10 to 50 m in order to constitute a thin semiconductor device. If it is less than 1 m, it is easy to deform and it is difficult to handle. If it exceeds 100 m, it is not preferable because it hinders the thinning of the whole semiconductor device.
  • the metals used at this time include alloys, iron-nickel alloys, and aluminum.
  • gold ⁇ 3 to for example 0. 9 4 1 0 4 (cal / cm - sec ⁇ ° C) of about ⁇ alloy desired to have a thermal conductivity correct .
  • a sealing resin 10 for sealing the semiconductor element having a thickness of about 0.3 wm, further preventing the semiconductor device from warping on its outer surface, and having a heat resistance of soldering.
  • gold 5 that has a favorable effect on the thermal cyclability.
  • An organic layer 6 is formed on the surface of the metal foil, and solid-state identification information can be recorded using the organic layer.
  • this organic layer is not essential, and when it is temporarily fixed to the mold cavity surface by means such as magnetic force or adsorption, a semiconductor device having the structure shown in FIG. 2 can be obtained.
  • this type of semiconductor device tends to bend the semiconductor element side when the lead frame is made of an iron-Nigel alloy and to make the semiconductor element side convex when the lead frame is made of a copper alloy.
  • the reason for this is that the members constituting the semiconductor device have different coefficients of linear expansion during the process of returning from the molding temperature (usually 175 ° C) to room temperature.
  • the present inventors have studied the phenomenon in detail, and as a result, by appropriately selecting a metal ⁇ having a different linear expansion coefficient according to the material of the lead frame, and further changing its rigidity by changing the thickness of the metal foil. It has been found that warpage of semiconductor devices can be suppressed.
  • metal foil located on the back side Lee Zadoff frame is the linear expansion coefficient of 0.4 ⁇ 2.
  • 7 X 1 0- 5 Z ° C metal foil can be used, the thickness of the case metal foil placed on the semiconductor element side linear expansion coefficient of 0. 4 ⁇ 0.
  • the average linear expansion coefficient of the sealing resin 10 using a thermosetting resin, which can be used in the present invention at 20 to 17 ° C. of 1.0 to 1.0 ° C. 2.4 x 10 /. C. Since the flexural modulus is 100 to 2000 kg / mm and the thickness of the sealing resin layer on the lead frame is as thin as 0.4 to 1.1 mm, Stress based on the difference in linear expansion coefficient between the lead frame and the sealing resin It is considered that the metal foil 5 placed on the semiconductor element side applies a stress in the opposite direction to prevent warpage.
  • a resin for encapsulating a semiconductor element for example, an epoxy resin, a phenol resin, a urea resin, a melamine resin, a polyester resin, a diaryl phthalate resin, a A thermosetting resin such as phenylene sulfide can be used, but among these, it is preferable to use an epoxy resin in view of the reliability of the resin-encapsulated semiconductor device.
  • a conventionally known additive such as a curing agent, a curing accelerator, and a filler is blended with the epoxy resin, and the epoxy resin is used as an epoxy resin composition.
  • the method for encapsulating the semiconductor element using the epoxy resin composition is not particularly limited, and the encapsulation can be performed by a known molding method such as ordinary transfer molding.
  • the method of manufacturing a semiconductor device is a method of forming and processing a resin 10 for encapsulating a semiconductor purple 7 using a mold, wherein a metal foil 5 is temporarily fixed to an upper cavity surface of the mold. Attach the gold foil 3 with adhesive 4 on the lower cavity surface of the mold with the adhesive side up, set the lead frame 8 and tighten the mold to remove the metal foil. It is characterized in that it is bonded to the frame and then injected with resin and molded.
  • a metal foil 5 used on the semiconductor element side has an organic layer 6 formed in advance on the surface, as shown in FIG. 1, after molding, organic S forms an outer surface on one side of the semiconductor device, and A semiconductor device in which the metal foil 5 is depressed and fixed below the organic layer is obtained.
  • a method is used in which a metal foil is temporarily fixed to the surface of a mold by an adsorption method or an organic layer having a temporary fixing function, and then molded.
  • gold ⁇ having no organic layer was also in this case c semiconductor device is obtained in which the metal foil forms one of the outer surface of the semiconductor device, as shown in FIG. 2, gold ⁇ For (4), a method of temporarily fixing to the mold surface by an adsorption method or the like and then molding is used.
  • the metal foil 3 formed on the back side of the lead frame 8 is bonded to the lead frame via the adhesive 4, but the gold foil 3 and the lead frame 8 are bonded in advance with the adhesive 4.
  • Prepare a lead frame with metal foil It can be used with the chip 7 mounted, or it can be mounted on the lower molding surface of the mold with the adhesive provided on the metal plate 3 facing up, and the lead frame on which the semiconductor element is mounted can be set from above. Then, the metal mold may be bonded to the lead frame by clamping the mold.
  • the adhesive 4 used at this time has excellent compatibility with the encapsulating resin, and also has sufficient flow between the lead pins when pressed by a mold heated to 175 ° C.
  • the initial thickness of the adhesive be 10 to 200 "m and the crystallization point be 150 ° C or less. After bonding, the thickness of the adhesive becomes 10 to 50 ⁇ m, the flowing adhesive 4 enters between the lead pins, and a dam bar effect is also produced to prevent the sealing resin from flowing out of the mold during molding. Wake up.
  • the adhesive 4 has a saturated water absorption of 0.1 wt% or less at 85 ° C / 85% RH from the viewpoint of reliability.
  • an epoxy resin, a polyimide resin, a polyester resin, a polyurethane resin, or the like can be used, for example.
  • a material containing polycarbodiimide as a main component is preferable because of its heat resistance and low water absorption.
  • the carbodiimide of the above structural formula is used as a main component (preferably 70% by weight or more of the adhesive component), and as an auxiliary component, an epoxy resin, a polyether imide resin, a rubber resin. Etc. can be used. Further, silica or the like may be contained in the adhesive.
  • FIG. 3 shows the method of the present invention over time.
  • the metal foil 5 is temporarily fixed to the upper mold cavities 1 and 2 of the open molds 1 and 2 which are set around 1 7 5 through the organic employment 6.
  • the metal 3 having the adhesive 4 is placed on the lower mold cavity surface.
  • the installation of the metals 3 and 5 may be performed by vacuum suction, a magnet, or the like, or may be performed by using an organic layer provided on the metal as a temporary fixing agent. Good.
  • a semiconductor chip 7 with a lead frame 8 is supplied, and then, as shown in FIG. 2 is closed.
  • the adhesive 4 of the metal foil flows between the lead bin and between the die pad and the die due to heat from the die and the clamping force of the die.
  • the sealing resin 10 is injected into the mold under the conditions set as shown in (D) of FIG.
  • an organic layer is formed on one surface of the semiconductor device, a metal foil 5 is buried under the organic S, and a metal 3 is exposed on the other surface. The removed semiconductor device is taken out.
  • the organic resin 6 of the sealing resin outer surface metal foil 5 on the semiconductor element side can be provided with a temporary fixing function by a heat-adhesive adhesive, for example, epoxy resin, polyester resin, phenol resin. , Polyimide resin and the like are used.
  • the thickness of organic S is preferably 5 to 100 m.
  • the organic ⁇ for temporary fixation can be used by blending a pigment or a pitting material to provide a contrast, and it can be used as a recording layer for solid identification. Can function.
  • the coating of the semiconductor device with the gold foil 5 preferably covers at least ⁇ 0% of one surface area of the semiconductor device, particularly preferably 80% or more. That is, by covering the semiconductor device by 50% or more, the crack resistance at T C ⁇ of the obtained semiconductor device and the crack resistance at the time of solder immersion are remarkably improved.
  • the semiconductor device obtained by the present invention has the following features.
  • the semiconductor device of the present invention has a sealing material only on the lead frame, so that the semiconductor device can be made thinner and the mounting density can be greatly improved.
  • the structure is such that the sealing resin is only on the lead frame.
  • the semiconductor device is difficult to sledge. As a result, mounting on a motherboard or the like can be easily performed. Also at T C ⁇ ⁇ , there is little deformation due to stress, and a long life can be achieved.
  • the structure of the semiconductor device of the present invention is such that the back surface of the lead frame is covered with a metal foil having a high thermal conductivity relative to the sealing resin via an adhesive, so that the heat of the semiconductor element is transferred to the outside of the semiconductor device. Easy to release. As a result, the heat dissipation efficiency of the semiconductor device can be increased.
  • the metal foil since most of the surface of the semiconductor device is covered with the metal foil, it is difficult to absorb moisture. In addition, since the strength of the metal foil is higher than that of the sealing resin, it has excellent solder heat resistance when dipped in solder.
  • the die pad size used in this experiment was 8 x 8 mm, and the chip size was 7 x 7 x 0.3 mm.
  • the fabricated semiconductor device is an 80-pin QFP (size 20 x 14 mm). The test method was measured by the following measurement method.
  • the semiconductor device After leaving the semiconductor device in a thermostat at 85 ° C and 85% relative humidity and absorbing moisture, the semiconductor device was immersed in the solder melt at 260 for 10 seconds, and the number of cracks in the semiconductor device was measured. Evaluation.
  • a resistor element capable of generating 2 W of heat and having the same size as the above was used as the semiconductor element, and molded in the same manner as above to obtain a sample.
  • the heat generation of the element was 2 W, the cooling was air cooling, and the experiment was performed while changing the flow velocity.
  • the thermal resistance Rja was obtained by the following equation.
  • T j junction temperature
  • Ta room temperature
  • Q element heat generation
  • the surface roughness of the semiconductor device after molding and the surface of the semiconductor device on the opposite side are measured by a contact surface roughness meter, and the difference between the maximum value and the minimum value is measured. The larger one was taken as the amount of warpage of the semiconductor device.
  • a value of plus (+) means that the semiconductor device side is concave, and a value of minus (-) means that the semiconductor device is convex. In the case of the size of the semiconductor device used in this test, It has been confirmed that a warp having no practical problem exists within ⁇ 30 m.
  • the size of the aluminum alloy foil was 18 x 12 mm, and that of the copper alloy foil was 2 O x 14 mm.
  • the total thickness of this semiconductor device is 1 mm.
  • the warpage of the semiconductor device of the embodiment is so small that it does not support the mounting, and that the semiconductor device is clearly superior in terms of T C ⁇ , solder heat resistance and thermal resistance.
  • the molding of this example did not cause any defect such as void, gold wire deformation, and semiconductor element deformation, and a stable sample was obtained at a high yield. There was no warpage of the semiconductor device, and the mounting on the motherboard was performed without fail.
  • Example 1 iron-nickel alloy foil (thickness 50 m, coefficient of linear expansion 0.4 X10 " 5 / ° 0 was used as the metal foil on the semiconductor element side, and to 4 2 Aroi (thickness 1 2 5 m, the linear expansion coefficient 0. 4 x 1 0 one 5 / ° C), copper-gold ⁇ (thickness 2 5 as a rie de frames back surface of the metal foil m, the linear expansion coefficient 1. 7 1 0 -. 5 z.c ) but using got semiconductor equipment perform the molding in the same manner as in example 1 test results where obtained semiconductor device Table 1 However, as in Example 1, good evaluation results were obtained.
  • Example 2 the constituent materials of the semiconductor device were selected, and the others were prepared in the same manner as in Example 1. The results of the same tests as in Example 1 are shown in Table 1.
  • Comparative Example 1 copper is used as the lead frame.
  • Iron conductive elements side metal S is the linear expansion coefficient Te 0 4 X 1 0- 5 Z - . Due to the nickel metal ⁇ , warp on the convex is generated in the semiconductor element side, the results of TCT in the influence of the warp It is worse than in the example.
  • the semiconductor device of the present invention is characterized in that a metal is mounted on the back surface of the lead frame on which the element is mounted, and further, a gold foil is mounted on the outer surface of the sealing resin on the semiconductor element side.
  • the semiconductor device can be easily made thinner, and has excellent moisture resistance, solder heat resistance during solder immersion, and heat stress resistance, and has high heat dissipation.
  • the warpage of the semiconductor device can also be reduced by the combination of the linear expansion coefficient and the thickness of the metal II, and the mother board can be mounted reliably.

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Dans un dispositif semi-conducteur scellé par de la résine, comportant un élément scellé au moyen d'une résine, on soude une feuille métallique à la face arrière d'une grille de connexion fixée à l'élément semi-conducteur au moyen d'un adhésif et, dans le même temps, on fixe ladite feuille métallique à la surface externe de la résine de scellement sur le côté de l'élément semi-conducteur. Il est ainsi possible de fabriquer un dispositif semi-conducteur ne présentant aucun gauchissement. En outre, du fait de l'absence de gauchissement et de la présence de la feuille métallique sur les surfaces externes supérieure et inférieure du dispositif semi-conducteur, ledit dispositif possède des caractéristiques améliorées de rayonnement thermique et de fiabilité, il n'est pratiquement pas affecté par l'absorption d'humidité et peut supporter de fortes contraintes thermiques.
PCT/JP1997/000473 1996-02-22 1997-02-20 Dispositif semi-conducteur et son procede de fabrication WO1997031394A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09/125,523 US6144108A (en) 1996-02-22 1997-02-20 Semiconductor device and method of fabricating the same
EP97903588A EP0883170A4 (fr) 1996-02-22 1997-02-20 Dispositif semi-conducteur et son procede de fabrication

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8035154A JPH09232475A (ja) 1996-02-22 1996-02-22 半導体装置及びその製造方法
JP8/35154 1996-02-22

Publications (1)

Publication Number Publication Date
WO1997031394A1 true WO1997031394A1 (fr) 1997-08-28

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PCT/JP1997/000473 WO1997031394A1 (fr) 1996-02-22 1997-02-20 Dispositif semi-conducteur et son procede de fabrication

Country Status (6)

Country Link
US (1) US6144108A (fr)
EP (1) EP0883170A4 (fr)
JP (1) JPH09232475A (fr)
KR (1) KR19990087129A (fr)
CN (1) CN1215501A (fr)
WO (1) WO1997031394A1 (fr)

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Also Published As

Publication number Publication date
CN1215501A (zh) 1999-04-28
KR19990087129A (ko) 1999-12-15
EP0883170A4 (fr) 2001-01-31
US6144108A (en) 2000-11-07
JPH09232475A (ja) 1997-09-05
EP0883170A1 (fr) 1998-12-09

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