WO1990016079A3 - Boitier a faible impedance - Google Patents

Boitier a faible impedance Download PDF

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Publication number
WO1990016079A3
WO1990016079A3 PCT/US1990/003262 US9003262W WO9016079A3 WO 1990016079 A3 WO1990016079 A3 WO 1990016079A3 US 9003262 W US9003262 W US 9003262W WO 9016079 A3 WO9016079 A3 WO 9016079A3
Authority
WO
WIPO (PCT)
Prior art keywords
low impedance
package
disclosed
dielectric layer
packaging
Prior art date
Application number
PCT/US1990/003262
Other languages
English (en)
Other versions
WO1990016079A2 (fr
Inventor
Jaesup N Lee
Original Assignee
Jaesup N Lee
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jaesup N Lee filed Critical Jaesup N Lee
Publication of WO1990016079A2 publication Critical patent/WO1990016079A2/fr
Publication of WO1990016079A3 publication Critical patent/WO1990016079A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un boîtier destiné à un circuit intégré. Ledit boîtier comprend un cadre de montage recouvert d'une couche diélectrique. En place un ou plusieurs conducteurs sur ladite couche diélectrique, lesquels font office de chemins inducteurs multiples pour les lignes d'alimentation et de terre. L'invention concerne également des condensateurs de découplage ainsi qu'un procédé de fabrication dudit boîtier.
PCT/US1990/003262 1989-06-09 1990-06-08 Boitier a faible impedance WO1990016079A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/364,370 US5089878A (en) 1989-06-09 1989-06-09 Low impedance packaging
US364,370 1989-06-09

Publications (2)

Publication Number Publication Date
WO1990016079A2 WO1990016079A2 (fr) 1990-12-27
WO1990016079A3 true WO1990016079A3 (fr) 1991-02-07

Family

ID=23434218

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1990/003262 WO1990016079A2 (fr) 1989-06-09 1990-06-08 Boitier a faible impedance

Country Status (3)

Country Link
US (1) US5089878A (fr)
JP (1) JPH05500882A (fr)
WO (1) WO1990016079A2 (fr)

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2669177B1 (fr) * 1990-11-09 1992-12-31 Sofradir Ste Fse Detecteurs In Procede pour realiser l'assemblage reversible d'un circuit electronique de lecture et/ou d'exploitation et d'un support conducteur ou non de l'electricite.
JPH04280462A (ja) * 1991-03-08 1992-10-06 Mitsubishi Electric Corp リードフレームおよびこのリードフレームを使用した半導体装置
JP2917607B2 (ja) * 1991-10-02 1999-07-12 セイコーエプソン株式会社 半導体装置用リードフレーム
US5220195A (en) * 1991-12-19 1993-06-15 Motorola, Inc. Semiconductor device having a multilayer leadframe with full power and ground planes
US5221858A (en) * 1992-02-14 1993-06-22 Motorola, Inc. Tape automated bonding (TAB) semiconductor device with ground plane and method for making the same
US5442228A (en) * 1992-04-06 1995-08-15 Motorola, Inc. Monolithic shielded integrated circuit
JPH0653394A (ja) * 1992-07-28 1994-02-25 Shinko Electric Ind Co Ltd 多層リードフレーム用プレーン支持体
US5854094A (en) * 1992-07-28 1998-12-29 Shinko Electric Industries Co., Ltd. Process for manufacturing metal plane support for multi-layer lead frames
US5208725A (en) * 1992-08-19 1993-05-04 Akcasu Osman E High capacitance structure in a semiconductor device
JPH06163794A (ja) * 1992-11-19 1994-06-10 Shinko Electric Ind Co Ltd メタルコアタイプの多層リードフレーム
US5311057A (en) * 1992-11-27 1994-05-10 Motorola Inc. Lead-on-chip semiconductor device and method for making the same
JP2732767B2 (ja) * 1992-12-22 1998-03-30 株式会社東芝 樹脂封止型半導体装置
JPH06334105A (ja) * 1993-05-24 1994-12-02 Shinko Electric Ind Co Ltd 多層リードフレーム
US5343074A (en) * 1993-10-04 1994-08-30 Motorola, Inc. Semiconductor device having voltage distribution ring(s) and method for making the same
US5498901A (en) * 1994-08-23 1996-03-12 National Semiconductor Corporation Lead frame having layered conductive planes
US5622588A (en) * 1995-02-02 1997-04-22 Hestia Technologies, Inc. Methods of making multi-tier laminate substrates for electronic device packaging
US5597643A (en) * 1995-03-13 1997-01-28 Hestia Technologies, Inc. Multi-tier laminate substrate with internal heat spreader
US5541453A (en) * 1995-04-14 1996-07-30 Abb Semiconductors, Ltd. Power semiconductor module
US5635767A (en) * 1995-06-02 1997-06-03 Motorola, Inc. Semiconductor device having built-in high frequency bypass capacitor
WO1997029512A1 (fr) * 1996-02-09 1997-08-14 Mci Computer Gmbh Element a semi-conducteur comportant un condensateur
US5783857A (en) * 1996-07-25 1998-07-21 The Whitaker Corporation Integrated circuit package
KR100204600B1 (ko) * 1996-10-23 1999-06-15 정선종 패키지 접지단 패들의 근사적인 등가회로의 구조
KR100218368B1 (ko) * 1997-04-18 1999-09-01 구본준 리드프레임과 그를 이용한 반도체 패키지 및 그의 제조방법
US5955777A (en) * 1997-07-02 1999-09-21 Micron Technology, Inc. Lead frame assemblies with voltage reference plane and IC packages including same
US6159764A (en) * 1997-07-02 2000-12-12 Micron Technology, Inc. Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages
US5982027A (en) * 1997-12-10 1999-11-09 Micron Technology, Inc. Integrated circuit interposer with power and ground planes
US6002165A (en) * 1998-02-23 1999-12-14 Micron Technology, Inc. Multilayered lead frame for semiconductor packages
US7020958B1 (en) * 1998-09-15 2006-04-04 Intel Corporation Methods forming an integrated circuit package with a split cavity wall
JP3062192B1 (ja) * 1999-09-01 2000-07-10 松下電子工業株式会社 リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法
US6285324B1 (en) * 1999-09-15 2001-09-04 Lucent Technologies Inc. Antenna package for a wireless communications device
US6225690B1 (en) * 1999-12-10 2001-05-01 Lsi Logic Corporation Plastic ball grid array package with strip line configuration
US6418031B1 (en) 2000-05-01 2002-07-09 International Business Machines Corporation Method and means for decoupling a printed circuit board
US6320757B1 (en) * 2000-07-12 2001-11-20 Advanced Semiconductor Engineering, Inc. Electronic package
US7183138B2 (en) * 2000-08-23 2007-02-27 Micron Technology, Inc. Method and apparatus for decoupling conductive portions of a microelectronic device package
JP4613416B2 (ja) * 2000-11-28 2011-01-19 日本電気株式会社 半導体装置およびその実装方法
TW488054B (en) * 2001-06-22 2002-05-21 Advanced Semiconductor Eng Semiconductor package for integrating surface mount devices
US6806568B2 (en) * 2001-07-20 2004-10-19 The Board Of Trustees Of The University Of Arkansas Decoupling capacitor for integrated circuit package and electrical components using the decoupling capacitor and associated methods
JP2005347369A (ja) * 2004-06-01 2005-12-15 Renesas Technology Corp 半導体装置およびその製造方法
WO2007054883A2 (fr) * 2005-11-08 2007-05-18 Nxp B.V. Boitier de circuit integre a grille de connexion dote d’un peigne de reference d’alimentation
KR101221807B1 (ko) * 2006-12-29 2013-01-14 페어차일드코리아반도체 주식회사 전력 소자 패키지
US20090032941A1 (en) * 2007-08-01 2009-02-05 Mclellan Neil Under Bump Routing Layer Method and Apparatus
US7906424B2 (en) * 2007-08-01 2011-03-15 Advanced Micro Devices, Inc. Conductor bump method and apparatus
US8314474B2 (en) * 2008-07-25 2012-11-20 Ati Technologies Ulc Under bump metallization for on-die capacitor
US7994610B1 (en) 2008-11-21 2011-08-09 Xilinx, Inc. Integrated capacitor with tartan cross section
US7944732B2 (en) * 2008-11-21 2011-05-17 Xilinx, Inc. Integrated capacitor with alternating layered segments
US7994609B2 (en) * 2008-11-21 2011-08-09 Xilinx, Inc. Shielding for integrated capacitors
US7956438B2 (en) * 2008-11-21 2011-06-07 Xilinx, Inc. Integrated capacitor with interlinked lateral fins
US8207592B2 (en) * 2008-11-21 2012-06-26 Xilinx, Inc. Integrated capacitor with array of crosses
US8362589B2 (en) * 2008-11-21 2013-01-29 Xilinx, Inc. Integrated capacitor with cabled plates
US8653844B2 (en) 2011-03-07 2014-02-18 Xilinx, Inc. Calibrating device performance within an integrated circuit
US8941974B2 (en) 2011-09-09 2015-01-27 Xilinx, Inc. Interdigitated capacitor having digits of varying width
US9270247B2 (en) 2013-11-27 2016-02-23 Xilinx, Inc. High quality factor inductive and capacitive circuit structure
US9524964B2 (en) 2014-08-14 2016-12-20 Xilinx, Inc. Capacitor structure in an integrated circuit
IT201700000460A1 (it) 2017-01-03 2018-07-03 St Microelectronics Srl Procedimento per realizzare prodotti a semiconduttore, prodotto e dispositivo a semiconduttore corrispondenti

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6092646A (ja) * 1983-10-27 1985-05-24 Toshiba Corp 二層構造リ−ドフレ−ム
JPS6112053A (ja) * 1984-06-27 1986-01-20 Nec Corp リ−ドフレ−ム
JPS6254456A (ja) * 1985-07-31 1987-03-10 Nec Corp 半導体装置用リ−ドフレ−ム
US4796078A (en) * 1987-06-15 1989-01-03 International Business Machines Corporation Peripheral/area wire bonding technique
JPH01137660A (ja) * 1987-11-25 1989-05-30 Hitachi Ltd 半導体装置
US4891687A (en) * 1987-01-12 1990-01-02 Intel Corporation Multi-layer molded plastic IC package

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5423570U (fr) * 1977-07-19 1979-02-16
JPS598067B2 (ja) * 1979-02-02 1984-02-22 三菱電機株式会社 半導体装置の製造方法
EP0115514B1 (fr) * 1982-08-10 1986-11-12 BROWN, David, Frank Support de circuit integre
US4827377A (en) * 1982-08-30 1989-05-02 Olin Corporation Multi-layer circuitry
US4551747A (en) * 1982-10-05 1985-11-05 Mayo Foundation Leadless chip carrier apparatus providing for a transmission line environment and improved heat dissipation
JPS5998543A (ja) * 1982-11-26 1984-06-06 Hitachi Ltd 半導体装置
EP0120500B1 (fr) * 1983-03-29 1989-08-16 Nec Corporation Empaquetage pour LSI à haute densité pour circuits logiques
US4680613A (en) * 1983-12-01 1987-07-14 Fairchild Semiconductor Corporation Low impedance package for integrated circuit die
US4543544A (en) * 1984-01-04 1985-09-24 Motorola, Inc. LCC co-planar lead frame semiconductor IC package
JPS60180154A (ja) * 1984-02-27 1985-09-13 Clarion Co Ltd 半導体装置
DE3516954A1 (de) * 1984-05-14 1985-11-14 Gigabit Logic, Inc., Newbury Park, Calif. Montierte integrierte schaltung
US4680617A (en) * 1984-05-23 1987-07-14 Ross Milton I Encapsulated electronic circuit device, and method and apparatus for making same
JPS6120343A (ja) * 1984-07-09 1986-01-29 Toshiba Corp 半導体装置
US4675717A (en) * 1984-10-09 1987-06-23 American Telephone And Telegraph Company, At&T Bell Laboratories Water-scale-integrated assembly
US4754366A (en) * 1985-01-22 1988-06-28 Rogers Corporation Decoupling capacitor for leadless surface mounted chip carrier
JPS61208242A (ja) * 1985-03-13 1986-09-16 Hitachi Ltd 半導体装置
JPS61239649A (ja) * 1985-04-13 1986-10-24 Fujitsu Ltd 高速集積回路パツケ−ジ
US4594641A (en) * 1985-05-03 1986-06-10 Rogers Corporation Decoupling capacitor and method of formation thereof
JPS628544A (ja) * 1985-07-05 1987-01-16 Hitachi Ltd 樹脂封止半導体装置
US4729010A (en) * 1985-08-05 1988-03-01 Hitachi, Ltd. Integrated circuit package with low-thermal expansion lead pieces
JPS6235655A (ja) * 1985-08-09 1987-02-16 Hitachi Ltd 半導体集積回路装置
US4801765A (en) * 1986-01-06 1989-01-31 American Telephone And Telegraph Company, At&T Bell Laboratories Electronic component package using multi-level lead frames
US4839717A (en) * 1986-12-19 1989-06-13 Fairchild Semiconductor Corporation Ceramic package for high frequency semiconductor devices
US4731700A (en) * 1987-02-12 1988-03-15 Delco Electronics Corporation Semiconductor connection and crossover apparatus

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6092646A (ja) * 1983-10-27 1985-05-24 Toshiba Corp 二層構造リ−ドフレ−ム
JPS6112053A (ja) * 1984-06-27 1986-01-20 Nec Corp リ−ドフレ−ム
JPS6254456A (ja) * 1985-07-31 1987-03-10 Nec Corp 半導体装置用リ−ドフレ−ム
US4891687A (en) * 1987-01-12 1990-01-02 Intel Corporation Multi-layer molded plastic IC package
US4796078A (en) * 1987-06-15 1989-01-03 International Business Machines Corporation Peripheral/area wire bonding technique
JPH01137660A (ja) * 1987-11-25 1989-05-30 Hitachi Ltd 半導体装置

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US5089878A (en) 1992-02-18
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