WO1990008401A1 - Circuit integre comportant au moins un transistor a effet de champ a canal n et au moins un transistor a effet de champ a canal p - Google Patents

Circuit integre comportant au moins un transistor a effet de champ a canal n et au moins un transistor a effet de champ a canal p Download PDF

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Publication number
WO1990008401A1
WO1990008401A1 PCT/EP1990/000033 EP9000033W WO9008401A1 WO 1990008401 A1 WO1990008401 A1 WO 1990008401A1 EP 9000033 W EP9000033 W EP 9000033W WO 9008401 A1 WO9008401 A1 WO 9008401A1
Authority
WO
WIPO (PCT)
Prior art keywords
potential
channel fet
well
equal
integrated circuit
Prior art date
Application number
PCT/EP1990/000033
Other languages
German (de)
English (en)
Inventor
Werner Muth
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. filed Critical Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Publication of WO1990008401A1 publication Critical patent/WO1990008401A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Definitions

  • Integrated circuit with at least one n-channel FET and at least one p-channel FET is Integrated circuit with at least one n-channel FET and at least one p-channel FET
  • the present invention relates to an integrated circuit with at least one n-channel field effect transistor (n-channel FET) and at least one p-channel field effect transistor (p-channel FET).
  • n-channel FET n-channel field effect transistor
  • p-channel FET p-channel field effect transistor
  • an n-channel FET and p-channel FET are located in spatial proximity on a substrate.
  • Such a structure is found, for example, in an inverter circuit. If such a circuit is implemented, for example, in an n-substrate, the n-channel FET lies within a p-well.
  • the source of the p-channel FET is connected to a positive supply voltage via an ohmic contact, while the source of the n-channel FET is connected to a negative supply voltage via an ohmic contact.
  • the drain electrodes of both FETs are connected to each other and form the inverter output.
  • the gate electrodes of the two FETs are also connected to one another and form the input.
  • Such a structure of the integrated circuit results in parasitic bipolar structures, such as, for example, a parasitic thyristor between the source electrode of the p-channel transistor and the source electrode of the n-channel transistor.
  • the npnp layer sequence between the source electrodes of these transistors is a parasitic thyristor, the anode and cathode of which are at the opposite supply voltages. Therefore, in known integrated circuits with an n-channel FET and a p-channel FET, there is a risk that a parasitic thyristor will be switched through. This is called "latch-up".
  • CMOS structures with an n-channel FET and a p-channel FET are already in a common n- Substrate known in which the n-channel FET lies in a p-well and in which the p-channel FET lies in an n-well, which in turn lies in a further p-well, is used in this known CMOS structure the additional p-well of the p-channel FET alone serves to decouple the p-channel FET from the potential of the n-epitaxial layer, and this publication does not deal with problems of latch-up, nor does it contain any problems Notes regarding the potentials for operating the CMOS circuit structure shown there.
  • the present invention is based on the object of developing an integrated circuit with at least one n-channel FET and at least one p-channel FET, which are arranged in a common substrate, in such a way that parasitic bipolar structures are switched on or a "latch-up" is prevented or at least excluded with a high probability.
  • the basic idea of the present invention is, in the case of an integrated circuit with a p-channel FET and n-channel FET, to surround the FET whose polarity does not correspond to the polarity of the substrate or the epitaxial layer with a trough which: in turn lies in a further well, the potentials with which the three wells of the FETs are controlled being chosen such that no parasitic bipolar structure in can get into a connected state.
  • the probability of the occurrence of a "latch-up" is considerably reduced in the structure of the integrated circuit according to the invention.
  • FIG. 1 shows an exemplary embodiment of the integrated circuit according to the invention with an n-substrate
  • FIG. 2 shows a second embodiment with p-type substrate, essentially corresponding to the embodiment of FIG. 1;
  • FIG. 4 shows a fourth embodiment in which a well of the n-channel transistor merges into an additional well of the p-channel transistor.
  • an n-channel FET 4 and a p-channel FET 5 are arranged on a common n-substrate 1 with an (n +) - substrate layer 2 and an (n -) - epitaxial layer 3.
  • the n-channel FET 4 lies in a first p-well 6 and comprises a source electrode 7, a gate electrode 8 and a drain electrode 9.
  • the source electrode 7 and the Drain electrodes 9 are connected in a manner known per se via ohmic contacts with meta-conductor tracks, while the gate electrode is arranged insulated from the channel of the FET 4.
  • the p-channel FET 5 has a second n-well 10, which in turn is bordered to the epitaxial layer 3 by a third (p -) - well.
  • the p-channel FET 5 has a source electrode 12, a gate electrode 13 and a drain electrode 14.
  • the source electrode 12 and the drain electrode 14 are connected to metal conductor tracks via ohmic contacts connected, while the gate electrode 13 is formed as a gate insulated from the channel.
  • the two FETs 4, 5 are connected as inverters in that the two gate electrodes 8, 13 have an input E, the two drain electrodes 9, 14 have an output A, the source electrode 7 of the n-channel FET 4 is connected to a negative supply potential V ss (-) and the source electrode 12 of the p-channel FET 5 is connected to a positive supply potential V DD (+).
  • the (n -) - epitaxial layer 3 is connected to the positive supply potential V DD (+) via at least one, here three ohmic contacts 15, 16, 17.
  • One 16 of these ohmic contacts 15, 16, 17 can lie between the two FETs 4, 5 as here.
  • the first p-well 6 is connected to the negative supply potential V ss (-) via at least a fourth ohmic contact 18.
  • the second n-well 10 is connected to the positive supply potential V DD (+) via at least a fifth Oh 'see contact 19.
  • the third (p -) - well 11 is connected to the positive supply potential V DD (+) via at least a sixth ohmic contact 20 and possibly via a seventh ohmic contact 21.
  • the potentials described above represent the preferred potential choice in order to prevent parasitic bipolar structures, such as parasitic thyristors, from being switched through
  • the potentials can also be selected such that the potential of the first p-well 6 is less than or equal to the positive supply potential V. DD (+), with which the (n -) - substrate 1, 2, 3 is applied, the potential of the third (p -) - well 11 being less than or equal to this positive supply potential V DD (+) and the potential of the second n-well 10 is greater than or equal to the potential of the third p-well 11.
  • the source 12 and the drain 14 of the p-channel FET 5 must be connected so that their potential is less than or equal to the potential of the second n-well.
  • the source 7 and the drain 9 of the n-channel FET 4 must be connected in such a way that their potential is greater than or equal to the potential of the first p-well 6.
  • the second embodiment of the integrated circuit according to the invention is explained below with reference to FIG. 2.
  • This second embodiment differs from the first embodiment only in that n-semiconductor regions are replaced by p-semiconductor regions and p-semiconductor regions by n-semiconductor regions, and accordingly the polarity of the voltages is reversed.
  • FIG. 2 the parts which correspond to parts shown in FIG. 1 are designated with corresponding reference symbols which are provided with an apostrophe.
  • Those circuit elements which in the first embodiment according to FIG. 1 have the positive supply supply potential V D D (+) are connected in the second embodiment according to FIG. 2 to the negative supply potential Vgg (-).
  • those circuit elements which are connected to the negative supply potential V ss (-) in the first embodiment are connected to the positive supply potential V DD (+) in the second embodiment.
  • the p-substrate 1 ', 2', 3 ' is supplied with the negative supply potential V ss (-), which is also supplied to the second p-well 10' and the source 12 of the n-channel FET 5 ' .
  • the third (n -) - well 11 ', the first n-well 6' and the source 7 'of the p-channel FET 4' are connected to the positive supply potential V DD (+).
  • a potential to the first n-well 6 ' which is greater than or equal to the negative supply potential V ss (-) with which the (p -) - substrate 1', 2 ', 3' is acted upon; to apply a third potential to the third (n -) - well 11 ', which is greater than or equal to the first, negative supply potential V ss (-), and to apply a fourth potential to the second well 10', that is less than or equal to the third potential.
  • the source 12 'and the drain 14' of the n-channel FET 5 'must be connected in such a way that their potential is greater than or equal to the potential of the second p-well 10'.
  • the source 7 'and the drain 9' of the n-channel FET 5 'must be connected in such a way that their potential is greater than or equal to the potential of the first n-well 6'.
  • the third embodiment of the integrated circuit according to the invention is explained in more detail below with reference to FIG. 3.
  • the third embodiment according to FIG. 3 essentially corresponds to the first embodiment according to FIG. 1.
  • Corresponding circuit elements or areas are identified by corresponding reference numerals. records, which are however provided with a double apostrophe.
  • Deviations from the embodiment according to FIG. 1 consist essentially in the fact that so-called trench isolations 22, 23, 24 are provided between the two FET's 4 ", 5" and on the two sides of the FET's 4 ", 5" facing away from each other, due to which it is it is possible to implement the circuit with an increased integration density.
  • the middle ohmic contact 16 is left out and replaced by a contact 25 on the underside.
  • FIG. 4 A fourth embodiment of the integrated circuit according to the invention is explained below with reference to FIG. 4.
  • Those circuit elements or areas that correspond to the elements or areas according to FIG. 1 are identified with the same reference numerals, but are provided with a triple apostrophe.
  • the main deviation from the first exemplary embodiment is that the first (p -) - tub 6 "'merges into the third (p -) - tub 11"', so that a single contact 18 "'to Applying this fused trough 6 "', 11"' with the negative supply potential V ss (-) is sufficient.
  • an additional potential source Vgyg can be connected between the source electrode 12 "'of the p-channel FET 5"' and the two Oh's contacts 15 "', 17"' to apply the substrate 1 "', 2"'
  • the potentials correspond to the potential relationships explained with reference to FIG. 1.
  • the degree of "latch-up" freedom in this fourth embodiment does not correspond to the degree of "latch-up” freedom achieved in the first three embodiments, this fourth embodiment can be used for many applications because of its simpler structure. «.
  • the present invention is not limited to those applications in which the n-channel FET and the p-channel FET are connected to form an inverter circuit. Any other structures which have at least one n-channel FET and one p-channel FET can be considered as fields of application for the purposes of the present invention.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Un circuit intégré comporte un transistor à effet de champ à canal n et un transistor à effet de champ à canal p qui sont disposés dans un substrat n. Le transistor à effet de champ à canal n possède un premier puits p, le canal p comprend un double puits constitué d'un deuxième puits n et d'un troisième puits p. Dans le but d'augmenter la liberté de ''verrouillage'', le potentiel du premier puits est inférieur ou égal au potentiel du substrat, le potentiel du troisième puits est inférieur ou égal au potentiel du substrat et le potentiel du deuxième puits est supérieur ou égal au potentiel du troisième puits.
PCT/EP1990/000033 1989-01-12 1990-01-08 Circuit integre comportant au moins un transistor a effet de champ a canal n et au moins un transistor a effet de champ a canal p WO1990008401A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19893900769 DE3900769A1 (de) 1989-01-12 1989-01-12 Integrierte schaltung mit zumindest einem n-kanal-fet und zumindest einem p-kanal-fet
DEP3900769.3 1989-01-12

Publications (1)

Publication Number Publication Date
WO1990008401A1 true WO1990008401A1 (fr) 1990-07-26

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PCT/EP1990/000033 WO1990008401A1 (fr) 1989-01-12 1990-01-08 Circuit integre comportant au moins un transistor a effet de champ a canal n et au moins un transistor a effet de champ a canal p

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DE (1) DE3900769A1 (fr)
WO (1) WO1990008401A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0522579A2 (fr) * 1991-07-12 1993-01-13 Texas Instruments Incorporated Circuit de décalage de niveau pour circuits intégrés
GB2269049A (en) * 1992-07-13 1994-01-26 Samsung Electronics Co Ltd Semiconductor memory device
GB2289162A (en) * 1994-05-04 1995-11-08 Hyundai Electronics Ind Semiconductor device with trench isolation and method for fabrication therof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59110153A (ja) * 1982-12-15 1984-06-26 Fujitsu Ltd Ｃｍｉｓ電界効果半導体装置
JPS61101072A (ja) * 1984-10-24 1986-05-19 Nec Corp 相補型ｍｏｓ半導体装置
JPS61194767A (ja) * 1985-02-22 1986-08-29 Nec Corp 相補型ｍｏｓ半導体装置の製造方法
JPS62155555A (ja) * 1985-09-18 1987-07-10 Sony Corp 相補型ｍｏｓトランジスタ
JPS62296455A (ja) * 1986-06-16 1987-12-23 Mitsubishi Electric Corp 半導体装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4306916A (en) * 1979-09-20 1981-12-22 American Microsystems, Inc. CMOS P-Well selective implant method
DE3855945T2 (de) * 1987-07-10 1997-11-13 Toshiba Kawasaki Kk Halbleiterbauelement mit Bereichen unterschiedlicher Störstellenkonzentration

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59110153A (ja) * 1982-12-15 1984-06-26 Fujitsu Ltd Ｃｍｉｓ電界効果半導体装置
JPS61101072A (ja) * 1984-10-24 1986-05-19 Nec Corp 相補型ｍｏｓ半導体装置
JPS61194767A (ja) * 1985-02-22 1986-08-29 Nec Corp 相補型ｍｏｓ半導体装置の製造方法
JPS62155555A (ja) * 1985-09-18 1987-07-10 Sony Corp 相補型ｍｏｓトランジスタ
JPS62296455A (ja) * 1986-06-16 1987-12-23 Mitsubishi Electric Corp 半導体装置

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 10, no. 283 (E-440)(2339) 26 September 1986, & JP-A-61 101072 (NEC) 19 Mai 1986, siehe das ganze Dokument *
PATENT ABSTRACTS OF JAPAN vol. 11, no. 23 (E-473)(2470) 22 Januar 1987, & JP-A-61 194767 (NEC) 29 August 1986, siehe das ganze Dokument *
PATENT ABSTRACTS OF JAPAN vol. 11, no. 390 (E-567)(2837) 19 Dezember 1987, & JP-A-62 155555 (SONY) 10 Juli 1987, siehe das ganze Dokument *
PATENT ABSTRACTS OF JAPAN vol. 12, no. 193 (E-617)(3040) 04 Juni 1988, & JP-A-62 296455 (MITSUBISHI) 23 Dezember 1987, siehe das ganze Dokument *
PATENT ABSTRACTS OF JAPAN vol. 8, no. 229 (E-273)(1666) 20 Oktober 1984, & JP-A-59 110153 (FUJITSU) 26 Juni 1984, siehe das ganze Dokument *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0522579A2 (fr) * 1991-07-12 1993-01-13 Texas Instruments Incorporated Circuit de décalage de niveau pour circuits intégrés
EP0522579A3 (en) * 1991-07-12 1994-07-20 Texas Instruments Inc Level-shifter circuit for integrated circuits
GB2269049A (en) * 1992-07-13 1994-01-26 Samsung Electronics Co Ltd Semiconductor memory device
GB2289162A (en) * 1994-05-04 1995-11-08 Hyundai Electronics Ind Semiconductor device with trench isolation and method for fabrication therof
GB2289162B (en) * 1994-05-04 1998-07-22 Hyundai Electronics Ind Method for fabricating a semiconductor device

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Publication number Publication date
DE3900769A1 (de) 1990-08-09

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