WO1990008401A1 - Integrated circuit with at least one n-channel fet and at least one p-channel fet - Google Patents

Integrated circuit with at least one n-channel fet and at least one p-channel fet Download PDF

Info

Publication number
WO1990008401A1
WO1990008401A1 PCT/EP1990/000033 EP9000033W WO9008401A1 WO 1990008401 A1 WO1990008401 A1 WO 1990008401A1 EP 9000033 W EP9000033 W EP 9000033W WO 9008401 A1 WO9008401 A1 WO 9008401A1
Authority
WO
WIPO (PCT)
Prior art keywords
potential
channel fet
well
equal
integrated circuit
Prior art date
Application number
PCT/EP1990/000033
Other languages
German (de)
French (fr)
Inventor
Werner Muth
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. filed Critical Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Publication of WO1990008401A1 publication Critical patent/WO1990008401A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Definitions

  • Integrated circuit with at least one n-channel FET and at least one p-channel FET is Integrated circuit with at least one n-channel FET and at least one p-channel FET
  • the present invention relates to an integrated circuit with at least one n-channel field effect transistor (n-channel FET) and at least one p-channel field effect transistor (p-channel FET).
  • n-channel FET n-channel field effect transistor
  • p-channel FET p-channel field effect transistor
  • an n-channel FET and p-channel FET are located in spatial proximity on a substrate.
  • Such a structure is found, for example, in an inverter circuit. If such a circuit is implemented, for example, in an n-substrate, the n-channel FET lies within a p-well.
  • the source of the p-channel FET is connected to a positive supply voltage via an ohmic contact, while the source of the n-channel FET is connected to a negative supply voltage via an ohmic contact.
  • the drain electrodes of both FETs are connected to each other and form the inverter output.
  • the gate electrodes of the two FETs are also connected to one another and form the input.
  • Such a structure of the integrated circuit results in parasitic bipolar structures, such as, for example, a parasitic thyristor between the source electrode of the p-channel transistor and the source electrode of the n-channel transistor.
  • the npnp layer sequence between the source electrodes of these transistors is a parasitic thyristor, the anode and cathode of which are at the opposite supply voltages. Therefore, in known integrated circuits with an n-channel FET and a p-channel FET, there is a risk that a parasitic thyristor will be switched through. This is called "latch-up".
  • CMOS structures with an n-channel FET and a p-channel FET are already in a common n- Substrate known in which the n-channel FET lies in a p-well and in which the p-channel FET lies in an n-well, which in turn lies in a further p-well, is used in this known CMOS structure the additional p-well of the p-channel FET alone serves to decouple the p-channel FET from the potential of the n-epitaxial layer, and this publication does not deal with problems of latch-up, nor does it contain any problems Notes regarding the potentials for operating the CMOS circuit structure shown there.
  • the present invention is based on the object of developing an integrated circuit with at least one n-channel FET and at least one p-channel FET, which are arranged in a common substrate, in such a way that parasitic bipolar structures are switched on or a "latch-up" is prevented or at least excluded with a high probability.
  • the basic idea of the present invention is, in the case of an integrated circuit with a p-channel FET and n-channel FET, to surround the FET whose polarity does not correspond to the polarity of the substrate or the epitaxial layer with a trough which: in turn lies in a further well, the potentials with which the three wells of the FETs are controlled being chosen such that no parasitic bipolar structure in can get into a connected state.
  • the probability of the occurrence of a "latch-up" is considerably reduced in the structure of the integrated circuit according to the invention.
  • FIG. 1 shows an exemplary embodiment of the integrated circuit according to the invention with an n-substrate
  • FIG. 2 shows a second embodiment with p-type substrate, essentially corresponding to the embodiment of FIG. 1;
  • FIG. 4 shows a fourth embodiment in which a well of the n-channel transistor merges into an additional well of the p-channel transistor.
  • an n-channel FET 4 and a p-channel FET 5 are arranged on a common n-substrate 1 with an (n +) - substrate layer 2 and an (n -) - epitaxial layer 3.
  • the n-channel FET 4 lies in a first p-well 6 and comprises a source electrode 7, a gate electrode 8 and a drain electrode 9.
  • the source electrode 7 and the Drain electrodes 9 are connected in a manner known per se via ohmic contacts with meta-conductor tracks, while the gate electrode is arranged insulated from the channel of the FET 4.
  • the p-channel FET 5 has a second n-well 10, which in turn is bordered to the epitaxial layer 3 by a third (p -) - well.
  • the p-channel FET 5 has a source electrode 12, a gate electrode 13 and a drain electrode 14.
  • the source electrode 12 and the drain electrode 14 are connected to metal conductor tracks via ohmic contacts connected, while the gate electrode 13 is formed as a gate insulated from the channel.
  • the two FETs 4, 5 are connected as inverters in that the two gate electrodes 8, 13 have an input E, the two drain electrodes 9, 14 have an output A, the source electrode 7 of the n-channel FET 4 is connected to a negative supply potential V ss (-) and the source electrode 12 of the p-channel FET 5 is connected to a positive supply potential V DD (+).
  • the (n -) - epitaxial layer 3 is connected to the positive supply potential V DD (+) via at least one, here three ohmic contacts 15, 16, 17.
  • One 16 of these ohmic contacts 15, 16, 17 can lie between the two FETs 4, 5 as here.
  • the first p-well 6 is connected to the negative supply potential V ss (-) via at least a fourth ohmic contact 18.
  • the second n-well 10 is connected to the positive supply potential V DD (+) via at least a fifth Oh 'see contact 19.
  • the third (p -) - well 11 is connected to the positive supply potential V DD (+) via at least a sixth ohmic contact 20 and possibly via a seventh ohmic contact 21.
  • the potentials described above represent the preferred potential choice in order to prevent parasitic bipolar structures, such as parasitic thyristors, from being switched through
  • the potentials can also be selected such that the potential of the first p-well 6 is less than or equal to the positive supply potential V. DD (+), with which the (n -) - substrate 1, 2, 3 is applied, the potential of the third (p -) - well 11 being less than or equal to this positive supply potential V DD (+) and the potential of the second n-well 10 is greater than or equal to the potential of the third p-well 11.
  • the source 12 and the drain 14 of the p-channel FET 5 must be connected so that their potential is less than or equal to the potential of the second n-well.
  • the source 7 and the drain 9 of the n-channel FET 4 must be connected in such a way that their potential is greater than or equal to the potential of the first p-well 6.
  • the second embodiment of the integrated circuit according to the invention is explained below with reference to FIG. 2.
  • This second embodiment differs from the first embodiment only in that n-semiconductor regions are replaced by p-semiconductor regions and p-semiconductor regions by n-semiconductor regions, and accordingly the polarity of the voltages is reversed.
  • FIG. 2 the parts which correspond to parts shown in FIG. 1 are designated with corresponding reference symbols which are provided with an apostrophe.
  • Those circuit elements which in the first embodiment according to FIG. 1 have the positive supply supply potential V D D (+) are connected in the second embodiment according to FIG. 2 to the negative supply potential Vgg (-).
  • those circuit elements which are connected to the negative supply potential V ss (-) in the first embodiment are connected to the positive supply potential V DD (+) in the second embodiment.
  • the p-substrate 1 ', 2', 3 ' is supplied with the negative supply potential V ss (-), which is also supplied to the second p-well 10' and the source 12 of the n-channel FET 5 ' .
  • the third (n -) - well 11 ', the first n-well 6' and the source 7 'of the p-channel FET 4' are connected to the positive supply potential V DD (+).
  • a potential to the first n-well 6 ' which is greater than or equal to the negative supply potential V ss (-) with which the (p -) - substrate 1', 2 ', 3' is acted upon; to apply a third potential to the third (n -) - well 11 ', which is greater than or equal to the first, negative supply potential V ss (-), and to apply a fourth potential to the second well 10', that is less than or equal to the third potential.
  • the source 12 'and the drain 14' of the n-channel FET 5 'must be connected in such a way that their potential is greater than or equal to the potential of the second p-well 10'.
  • the source 7 'and the drain 9' of the n-channel FET 5 'must be connected in such a way that their potential is greater than or equal to the potential of the first n-well 6'.
  • the third embodiment of the integrated circuit according to the invention is explained in more detail below with reference to FIG. 3.
  • the third embodiment according to FIG. 3 essentially corresponds to the first embodiment according to FIG. 1.
  • Corresponding circuit elements or areas are identified by corresponding reference numerals. records, which are however provided with a double apostrophe.
  • Deviations from the embodiment according to FIG. 1 consist essentially in the fact that so-called trench isolations 22, 23, 24 are provided between the two FET's 4 ", 5" and on the two sides of the FET's 4 ", 5" facing away from each other, due to which it is it is possible to implement the circuit with an increased integration density.
  • the middle ohmic contact 16 is left out and replaced by a contact 25 on the underside.
  • FIG. 4 A fourth embodiment of the integrated circuit according to the invention is explained below with reference to FIG. 4.
  • Those circuit elements or areas that correspond to the elements or areas according to FIG. 1 are identified with the same reference numerals, but are provided with a triple apostrophe.
  • the main deviation from the first exemplary embodiment is that the first (p -) - tub 6 "'merges into the third (p -) - tub 11"', so that a single contact 18 "'to Applying this fused trough 6 "', 11"' with the negative supply potential V ss (-) is sufficient.
  • an additional potential source Vgyg can be connected between the source electrode 12 "'of the p-channel FET 5"' and the two Oh's contacts 15 "', 17"' to apply the substrate 1 "', 2"'
  • the potentials correspond to the potential relationships explained with reference to FIG. 1.
  • the degree of "latch-up" freedom in this fourth embodiment does not correspond to the degree of "latch-up” freedom achieved in the first three embodiments, this fourth embodiment can be used for many applications because of its simpler structure. «.
  • the present invention is not limited to those applications in which the n-channel FET and the p-channel FET are connected to form an inverter circuit. Any other structures which have at least one n-channel FET and one p-channel FET can be considered as fields of application for the purposes of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

An integrated circuit has one n-channel FET and one p-channel FET, which are arranged in an n-substrate. The n-channel FET has a first p-well, the p-channel has a double well consisting of a second n-well and a third p-well. In order to increase the ''latch-up'' freedeom, the potential of the first well is less than or equal to the potential of the substrate, the potential of the third well is less than or equal to the potential of the substrate and the potential of the second well is greater than or equal to the potential of the third well.

Description

I I.
Integrierte Schaltung mit zumindest einem n-Kanal-FET und zumindest einem p-Kanal-FETIntegrated circuit with at least one n-channel FET and at least one p-channel FET
Die vorliegende Erfindung betrifft eine integrierte Schal¬ tung mit zumindest einem n-Kanal-Feldeffekttransistor (n-Kanal-FET) und zumindest einem p-Kanal-Feldeffekttran- sistor (p-Kanal-FET) .The present invention relates to an integrated circuit with at least one n-channel field effect transistor (n-channel FET) and at least one p-channel field effect transistor (p-channel FET).
Bei einer Vielzahl von integrierten Schaltungen befinden sich in räumlicher Nachbarschaft auf einem Substrat ein n-Kanal-FET und p-Kanal-FET. Eine derartige Struktur fin¬ det sich beispielsweise bei einer Inverterschaltung. Wenn eine derartige Schaltung beispielsweise in einem n-Sub- strat implementiert ist, so liegt der n-Kanal-FET inner¬ halb einer p-Wanne. Die Source des p-Kanal-FET liegt über Ohm'sehen Kontakt an einer positiven Versorgungsspannung, während die Source des n-Kanal-FET über einen Ohm'sehen Kontakt an einer negativen Versorgungsspannung liegt. Die Drain-Elektroden beider FET's sind miteinander verbunden und bilden den Inverterausgang. Die Gate-Elektroden der beiden FET's sind gleichfalls miteinander verbunden und bilden den Eingang. Bei einer derartigen Struktur der integrierten Schaltung ergeben sich parasitäre bipolare Strukturen, wie beispielsweise ein parasitärer Thyristor zwischen der Source-Elektrode des p-Kanal-Transistors und der Source-Elektrode des n-Kanal-Transistors. Mit anderen Worten stellt die npnp-Schichtfolge zwischen den Source- Elektroden dieser Transistoren einen parasitären Thyristor dar, dessen Anode und Kathode an den entgegengesetzten Versorgungsspannungen liegen. Daher beteht bei bekannten integrierten Schaltungen mit einem n-Kanal-FET und einem p-Kanal-FET die Gefahr, daß ein parasitärer Thyristor in einen durchgeschalteten Zustand gerät. Dies wird als "Latch-up" bezeichnet. Aus der Fachveröffentlichung "W. G. Meyer et al: Integrable High Voltage CMOS-Devices, IEEE 1985, IEDM 85, Seiten 732 bis 735 sind bereits CMOS-Strukturen mit einem n-Kanal-FET und einem p-Kanal-FET in einem gemeinsamen n-Substrat bekannt, bei denen der n-Kanal-FET in einer p-Wanne liegt und bei denen der p-Kanal-FET in einer n- Wanne liegt, die ihrerseits in einer weiteren p-Wanne liegt. Bei dieser bekannten CMOS-Struktur dient die zusätzliche p-Wanne des p-Kanal-FET allein dazu, den p-Kanal-FET potentialmäßig vom Potential der n-Epitaxie- Schicht zu entkoppeln. Diese Fachveröffentlichung befaßt sich weder mit Problemen des "Latch-up", noch beinhaltet sie irgendwelche Hinweise bezüglich der Potentiale zum Betreiben der dort gezeigten CMOS-Schaltungsstruktur.In a large number of integrated circuits, an n-channel FET and p-channel FET are located in spatial proximity on a substrate. Such a structure is found, for example, in an inverter circuit. If such a circuit is implemented, for example, in an n-substrate, the n-channel FET lies within a p-well. The source of the p-channel FET is connected to a positive supply voltage via an ohmic contact, while the source of the n-channel FET is connected to a negative supply voltage via an ohmic contact. The drain electrodes of both FETs are connected to each other and form the inverter output. The gate electrodes of the two FETs are also connected to one another and form the input. Such a structure of the integrated circuit results in parasitic bipolar structures, such as, for example, a parasitic thyristor between the source electrode of the p-channel transistor and the source electrode of the n-channel transistor. In other words, the npnp layer sequence between the source electrodes of these transistors is a parasitic thyristor, the anode and cathode of which are at the opposite supply voltages. Therefore, in known integrated circuits with an n-channel FET and a p-channel FET, there is a risk that a parasitic thyristor will be switched through. This is called "latch-up". From the technical publication "WG Meyer et al: Integrable High Voltage CMOS Devices, IEEE 1985, IEDM 85, pages 732 to 735, CMOS structures with an n-channel FET and a p-channel FET are already in a common n- Substrate known in which the n-channel FET lies in a p-well and in which the p-channel FET lies in an n-well, which in turn lies in a further p-well, is used in this known CMOS structure the additional p-well of the p-channel FET alone serves to decouple the p-channel FET from the potential of the n-epitaxial layer, and this publication does not deal with problems of latch-up, nor does it contain any problems Notes regarding the potentials for operating the CMOS circuit structure shown there.
Gegenüber diesem Stand der Technik liegt der vorliegenden Erfindung die Aufgabe zugrunde, eine integrierte Schaltung mit zumindest einem n-Kanal-FET und zumindest einem p-Kanal-FET, die in einem gemeinsamen Substrat angeordnet sind, so weiterzubilden, daß ein Leitendschalten von parasitären Bipolarstrukturen bzw. ein "Latch-up" verhin¬ dert oder zumindest mit hoher Wahrscheinlichkeit ausge¬ schlossen wird.In comparison with this prior art, the present invention is based on the object of developing an integrated circuit with at least one n-channel FET and at least one p-channel FET, which are arranged in a common substrate, in such a way that parasitic bipolar structures are switched on or a "latch-up" is prevented or at least excluded with a high probability.
Diese Aufgabe wird bei einer integrierten Schaltung nach dem Oberbegriff des Patentanspruchs 1 oder 2 durch die im kennzeichnenden Teil des Patentanspruchs 1 bzw. Patent¬ anspruchs 2 angegebenen Merkmale gelöst.This object is achieved in an integrated circuit according to the preamble of patent claim 1 or 2 by the features specified in the characterizing part of patent claim 1 or patent claim 2.
Der Grundgedanke der vorliegenden Erfindung liegt darin, bei einer integrierten Schaltung mit einem p-Kanal-FET und n-Kanal-FET denjenigen FET, dessen Polarität nicht der Polarität des Substrates bzw. der Epitaxieschicht ent¬ spricht, mit einer Wanne zu umgeben, die ihrerseits in einer weiteren Wanne liegt, wobei die Potentiale, mit denen die drei Wannen der FET's angesteuert werden, so gewählt sind, daß keine parasitäre BipolarStruktur in einen durchgeschalteten Zustand geraten kann. Die Wahr¬ scheinlichkeit des Auftretens eines "Latch-up" ist bei der erfindungsgemäßen Struktur der integrierten Schaltung erheblich herabgesetzt.The basic idea of the present invention is, in the case of an integrated circuit with a p-channel FET and n-channel FET, to surround the FET whose polarity does not correspond to the polarity of the substrate or the epitaxial layer with a trough which: in turn lies in a further well, the potentials with which the three wells of the FETs are controlled being chosen such that no parasitic bipolar structure in can get into a connected state. The probability of the occurrence of a "latch-up" is considerably reduced in the structure of the integrated circuit according to the invention.
Bevorzugte Weiterbildungen der erfindungsgemäßen inte¬ grierten Schaltung sind Gegenstand der Unteransprüche 3 bis 8.Preferred developments of the integrated circuit according to the invention are the subject of subclaims 3 to 8.
Vier verschiedene Ausführungsbeispiele der erfindungsge¬ mäßen integrierten Schaltung werden nachfolgend unter Be¬ zugnahme auf die beiliegenden Zeichnungen näher erläutert. Es zeigen:Four different exemplary embodiments of the integrated circuit according to the invention are explained in more detail below with reference to the accompanying drawings. Show it:
Fig. 1 ein Ausführungsbeispiel der erfindungsge¬ mäßen integrierten Schaltung mit n-Substrat;1 shows an exemplary embodiment of the integrated circuit according to the invention with an n-substrate;
Fig. 2 eine im wesentlichen der Ausführungsform von Fig. 1 entsprechende zweite Ausführungsform mit p-Substrat;FIG. 2 shows a second embodiment with p-type substrate, essentially corresponding to the embodiment of FIG. 1;
Fig. 3 eine dritte Ausführungsform mit Trenchisola- tion; und3 shows a third embodiment with trench isolation; and
Fig. 4 eine vierte Ausführungsform, bei der eine Wanne des n-Kanal-Transistors in eine zu¬ sätzliche Wanne des p-Kanal-Transistors übergeht.4 shows a fourth embodiment in which a well of the n-channel transistor merges into an additional well of the p-channel transistor.
Wie in Fig. 1 gezeigt ist, sind auf einem gemeinsamen n-Substrat 1 mit einer (n+)-Substratschicht 2 und einer (n-)-Epitaxieschicht 3 ein n-Kanal-FET 4 und ein p-Kanal- FET 5 angeordnet.As shown in FIG. 1, an n-channel FET 4 and a p-channel FET 5 are arranged on a common n-substrate 1 with an (n +) - substrate layer 2 and an (n -) - epitaxial layer 3.
Der n-Kanal-FET 4 liegt in einer ersten p-Wanne 6 und um¬ faßt eine Source-Elektrode 7, eine Gate-Elektrode 8 und eine Drain-Elektrode 9. Die Source-Elektrode 7 und die Drain-Elektrode 9 sind in an sich bekannter Weise über Ohm'sehe Kontakte mit MetaHeiterbahnen angeschlossen, während die Gate-Elektrode gegenüber dem Kanal des FET 4 isoliert angeordnet ist.The n-channel FET 4 lies in a first p-well 6 and comprises a source electrode 7, a gate electrode 8 and a drain electrode 9. The source electrode 7 and the Drain electrodes 9 are connected in a manner known per se via ohmic contacts with meta-conductor tracks, while the gate electrode is arranged insulated from the channel of the FET 4.
Der p-Kanal-FET 5 weist eine zweite n-Wanne 10 auf, die ihrerseits zur Epitaxie-Schicht 3 durch eine dritte (p-)- Wanne eingefaßt wird. Der p-Kanal-FET 5 hat eine Source- Elektrode 12, eine Gate-Elektrode 13 und eine Drain- Elektrode 14. Auch bei diesem FET 5 werden die Source- Elektrode 12 und die Drain-Elektrode 14 über Ohm'sehe Kontakte mit Metalleiterbahnen angeschlossen, während die Gate-Elektrode 13 als gegenüber dem Kanal isoliertes Gate ausgebildet ist.The p-channel FET 5 has a second n-well 10, which in turn is bordered to the epitaxial layer 3 by a third (p -) - well. The p-channel FET 5 has a source electrode 12, a gate electrode 13 and a drain electrode 14. In this FET 5, too, the source electrode 12 and the drain electrode 14 are connected to metal conductor tracks via ohmic contacts connected, while the gate electrode 13 is formed as a gate insulated from the channel.
Bei der integrierten Schaltung nach diesem ersten Ausfüh¬ rungsbeispiel sind die beiden FET's 4, 5 als Inverter be¬ schaltet, indem die beiden Gate-Elektroden 8, 13 mit einem Eingang E, die beiden Drain-Elektroden 9, 14 mit einem Ausgang A, die Source-Elektrode 7 des n-Kanal-FET 4 mit einem negativen Versorgungspotential Vss(-) und die Source-Elektrode 12 des p-Kanal-FET 5 mit einem positiven Versorgungspotential VDD(+) verbunden sind.In the integrated circuit according to this first exemplary embodiment, the two FETs 4, 5 are connected as inverters in that the two gate electrodes 8, 13 have an input E, the two drain electrodes 9, 14 have an output A, the source electrode 7 of the n-channel FET 4 is connected to a negative supply potential V ss (-) and the source electrode 12 of the p-channel FET 5 is connected to a positive supply potential V DD (+).
Die (n-)-Epitaxieschicht 3 steht über wenigstens einen, hier drei Ohm'sehe Kontakte 15, 16, 17 mit dem positiven Versorgungspotential VDD(+) in Verbindung. Einer 16 dieser Ohm'sehen Kontakte 15, 16, 17 kann wie hier zwischen den beiden FET's 4, 5 liegen.The (n -) - epitaxial layer 3 is connected to the positive supply potential V DD (+) via at least one, here three ohmic contacts 15, 16, 17. One 16 of these ohmic contacts 15, 16, 17 can lie between the two FETs 4, 5 as here.
Die erste p-Wanne 6 steht über mindestens einen vierten Ohm'sehen Kontakt 18 mit dem negativen Versorgungspoten¬ tial Vss(-) in Verbindung. Die zweite n-Wanne 10 steht über mindestens einen fünften Oh 'sehen Kontakt 19 mit dem positiven Versorgungspotential VDD(+) in Verbindung. Die dritte (p-)-Wanne 11 steht über mindestens einen sechsten Ohm'sehen Kontakt 20 und gegebenenfalls über einen siebten Ohm'sehen Kontakt 21 mit dem positiven Versorgungspotential VDD(+) in Verbindung.The first p-well 6 is connected to the negative supply potential V ss (-) via at least a fourth ohmic contact 18. The second n-well 10 is connected to the positive supply potential V DD (+) via at least a fifth Oh 'see contact 19. The third (p -) - well 11 is connected to the positive supply potential V DD (+) via at least a sixth ohmic contact 20 and possibly via a seventh ohmic contact 21.
Obwohl die oben beschriebenen Potentiale die bevorzugte Potentialwahl darstellen, um ein Durchschalten parasitärer Bipolarstrukturen, wie beispielsweise parasitärer Thyristoren zu vermeiden, können die Potentiale auch so gewählt sein, daß das Potential der ersten p-Wanne 6 kleiner oder gleich gegenüber dem positiven Versorgungs¬ potential VDD(+) ist, mit dem das (n-)-Substrat 1, 2, 3 beaufschlagt wird, wobei das Potential der dritten (p-)- Wanne 11 kleiner oder gleich diesem positiven Versorgungs¬ potential VDD(+) ist und das Potential der zweiten n-Wanne 10 größer oder gleich dem Potential der dritten p-Wanne 11 ist.Although the potentials described above represent the preferred potential choice in order to prevent parasitic bipolar structures, such as parasitic thyristors, from being switched through, the potentials can also be selected such that the potential of the first p-well 6 is less than or equal to the positive supply potential V. DD (+), with which the (n -) - substrate 1, 2, 3 is applied, the potential of the third (p -) - well 11 being less than or equal to this positive supply potential V DD (+) and the potential of the second n-well 10 is greater than or equal to the potential of the third p-well 11.
Die Source 12 und die Drain 14 des p-Kanal-FET 5 müssen so verschaltet werden, daß deren Potential kleiner oder gleich dem Potential der zweiten n-Wanne ist. Die Source 7 und die Drain 9 des n-Kanal-FET 4 müssen so verschaltet werden, daß deren Potential größer oder gleich dem Poten¬ tial der ersten p-Wanne 6 ist.The source 12 and the drain 14 of the p-channel FET 5 must be connected so that their potential is less than or equal to the potential of the second n-well. The source 7 and the drain 9 of the n-channel FET 4 must be connected in such a way that their potential is greater than or equal to the potential of the first p-well 6.
Nachfolgend wird unter Bezugnahme auf Fig. 2 die zweite Ausführungsform der erfindungsgemäßen integrierten Schal¬ tung erläutert. Diese zweite Ausführungsform unterscheidet sich lediglich dadurch von der ersten Ausführungsform, daß n-Halbleiterbereiche durch p-Halbleiterbereiche und p-Halbleiterbereiche durch n-Halbleiterbereiche ersetzt sind und dementsprechend die Polarität der Spannungen um¬ gekehrt ist. In der Fig. 2 sind die Teile, die in Fig. 1 gezeigten Teilen entsprechen, mit entsprechenden Bezugs¬ zeichen, die mit einem Apostroph versehen sind, bezeich¬ net. Diejenigen Schaltungselemente, die bei der ersten Ausführungsform gemäß Fig. 1 mit dem positiven Versor- gungspotential VDD(+) verbunden sind, sind bei der zweiten Ausführungsform gemäß Fig. 2 mit dem negativen Versor¬ gungspotential Vgg(-) verbunden. Entsprechend sind die¬ jenigen Schaltungselemente, die bei der ersten Ausfüh¬ rungsform mit dem negativen Versorgungspotential Vss(-) verbunden sind, bei der zweiten Ausführungsform mit dem positiven Versorgungspotential VDD(+) verbunden. Dement¬ sprechend wird das p-Substrat 1', 2', 3' mit dem negativen Versorgungspotential Vss(-) beaufschlagt, welches auch der zweiten p-Wanne 10' und der Source 12 des n-Kanal-FET 5' zugeleitet wird. Die dritte (n-)-Wanne 11', die erste n-Wanne 6' sowie die Source 7' des p-Kanal-FET 4' liegen an dem positiven Versorgungspotential VDD(+) . Gleichfalls ist es jedoch möglich, die erste n-Wanne 6' mit einem Potential zu beaufschlagen, das größer oder gleich dem negativen Versorgungspotential Vss(-) ist, mit dem das (p-)-Substrat 1', 2', 3' beaufschlagt wird; die dritte (n-)-Wanne 11'mit einem dritten Potential zu beaufschla¬ gen, das größer oder gleich dem ersten, negativen Versor¬ gungspotential Vss(-) ist, und die zweite Wanne 10' mit einem vierten Potential zu beaufschlagen, das kleiner oder gleich dem dritten Potential ist.The second embodiment of the integrated circuit according to the invention is explained below with reference to FIG. 2. This second embodiment differs from the first embodiment only in that n-semiconductor regions are replaced by p-semiconductor regions and p-semiconductor regions by n-semiconductor regions, and accordingly the polarity of the voltages is reversed. In FIG. 2, the parts which correspond to parts shown in FIG. 1 are designated with corresponding reference symbols which are provided with an apostrophe. Those circuit elements which in the first embodiment according to FIG. 1 have the positive supply supply potential V D D (+) are connected in the second embodiment according to FIG. 2 to the negative supply potential Vgg (-). Correspondingly, those circuit elements which are connected to the negative supply potential V ss (-) in the first embodiment are connected to the positive supply potential V DD (+) in the second embodiment. Accordingly, the p-substrate 1 ', 2', 3 'is supplied with the negative supply potential V ss (-), which is also supplied to the second p-well 10' and the source 12 of the n-channel FET 5 ' . The third (n -) - well 11 ', the first n-well 6' and the source 7 'of the p-channel FET 4' are connected to the positive supply potential V DD (+). However, it is also possible to apply a potential to the first n-well 6 'which is greater than or equal to the negative supply potential V ss (-) with which the (p -) - substrate 1', 2 ', 3' is acted upon; to apply a third potential to the third (n -) - well 11 ', which is greater than or equal to the first, negative supply potential V ss (-), and to apply a fourth potential to the second well 10', that is less than or equal to the third potential.
Die Source 12' und die Drain 14' des n-Kanal-FET 5' müssen so verschaltet werden, daß deren Potential größer oder gleich dem Potential der zweiten p-Wanne 10' ist. Die Source 7' und die Drain 9' des n-Kanal-FET 5' müssen so verschaltet werden, daß deren Potential größer oder gleich dem Potential der ersten n-Wanne 6' ist.The source 12 'and the drain 14' of the n-channel FET 5 'must be connected in such a way that their potential is greater than or equal to the potential of the second p-well 10'. The source 7 'and the drain 9' of the n-channel FET 5 'must be connected in such a way that their potential is greater than or equal to the potential of the first n-well 6'.
Nachfolgend wird unter Bezugnahme auf Fig. 3 die dritte Ausführungsform der erfindungsgemäßen integrierten Schal¬ tung näher erläutert. Die dritte Ausführungsform gemäß Fig. 3 entspricht im wesentlichen der ersten Ausführungs¬ form gemäß Fig. 1. Entsprechende Schaltungselemente oder Bereiche sind durch übereinstimmende Bezugszeichen be- zeichnet, die jedoch mit einem zweifachen Apostroph ver¬ sehen sind.The third embodiment of the integrated circuit according to the invention is explained in more detail below with reference to FIG. 3. The third embodiment according to FIG. 3 essentially corresponds to the first embodiment according to FIG. 1. Corresponding circuit elements or areas are identified by corresponding reference numerals. records, which are however provided with a double apostrophe.
Abweichungen gegenüber der Ausführungform gemäß Fig. 1 bestehen im wesentlichen darin, daß zwischen den beiden FET's 4", 5" sowie auf den beiden einander abgewandten Seiten der FET's 4", 5" sogenannte Trenchisolationen 22, 23, 24 vorgesehen sind, aufgrund derer es möglich ist, die Schaltung mit einer erhöhten Integrationsdichte zu imple¬ mentieren. In weiterer Abweichung von der Ausführungsform gemäß Fig. 1 ist der mittlere Ohm'sehe Kontakt 16 fortge¬ lassen und durch einen unterseitigen Kontakt 25 ersetzt.Deviations from the embodiment according to FIG. 1 consist essentially in the fact that so-called trench isolations 22, 23, 24 are provided between the two FET's 4 ", 5" and on the two sides of the FET's 4 ", 5" facing away from each other, due to which it is it is possible to implement the circuit with an increased integration density. In a further deviation from the embodiment according to FIG. 1, the middle ohmic contact 16 is left out and replaced by a contact 25 on the underside.
Nachfolgend wird unter Bezugnahme auf Fig. 4 eine vierte Ausführungsform der erfindungsgemäßen integrierten Schal¬ tung erläutert. Diejenigen Schaltungselemente oder Be¬ reiche, die den Elementen oder Bereichen gemäß Fig. 1 ent¬ sprechen, sind mit gleichen Bezugszeichen bezeichnet, die jedoch mit einem dreifachen Apostroph versehen sind.A fourth embodiment of the integrated circuit according to the invention is explained below with reference to FIG. 4. Those circuit elements or areas that correspond to the elements or areas according to FIG. 1 are identified with the same reference numerals, but are provided with a triple apostrophe.
Bei dieser Ausführungsform besteht die hauptsächliche Ab¬ weichung gegenüber dem ersten Ausführungsbeispiel darin, daß die erste (p-)-Wanne 6"' in die dritte (p-)-Wanne 11"' übergeht, so daß ein einziger Kontakt 18"' zum Beaufschla¬ gen dieser verschmolzenen Wanne 6"', 11"' mit dem negati¬ ven Versorgungspotential Vss(-) genügt.In this embodiment, the main deviation from the first exemplary embodiment is that the first (p -) - tub 6 "'merges into the third (p -) - tub 11"', so that a single contact 18 "'to Applying this fused trough 6 "', 11"' with the negative supply potential V ss (-) is sufficient.
Gegebenenfalls kann eine zusätzliche Potentialquelle Vgyg zwischen der Source-Elektrode 12"' des p-Kanal-FET 5"' und den beiden Oh 'schen Kontakten 15"', 17"' zum Beaufschla¬ gen des Substrates 1"', 2"', 3"' vorgesehen sein. Im übri¬ gen entsprechen die Potentiale den unter Bezugnahme auf Fig. 1 erläuterten Potentialverhältnissen. Obwohl der Grad der "Latch-up"-Freiheit bei dieser vierten Ausführungsform nicht den Grad der "Latch-up"-Freiheit der ersten drei Ausführungsformen erreicht, kann diese vierte Ausführungs¬ form wegen ihrer einfacheren Struktur für viele Anwen- «.If necessary, an additional potential source Vgyg can be connected between the source electrode 12 "'of the p-channel FET 5"' and the two Oh's contacts 15 "', 17"' to apply the substrate 1 "', 2"' The potentials correspond to the potential relationships explained with reference to FIG. 1. Although the degree of "latch-up" freedom in this fourth embodiment does not correspond to the degree of "latch-up" freedom achieved in the first three embodiments, this fourth embodiment can be used for many applications because of its simpler structure. «.
dungsfälle die geeignetere Lösung sein.cases are the more suitable solution.
Selbstverständlich ist die vorliegende Erfindung nicht auf solche Anwendungsfälle beschränkt, bei denen der n-Kanal- FET und der p-Kanal-FET zu einer Inverterschaltung ver¬ schaltet sind. Beliebige andere Strukturen, die wenigstens einen n-Kanal-FET und einen p-Kanal-FET aufweisen, kommen als Anwendungsgebiete für die Zwecke der vorliegenden Er¬ findung in Betracht. Of course, the present invention is not limited to those applications in which the n-channel FET and the p-channel FET are connected to form an inverter circuit. Any other structures which have at least one n-channel FET and one p-channel FET can be considered as fields of application for the purposes of the present invention.

Claims

SIntegrierte Schaltung mit zumindest einem n-Kanal-FET und zumindest einem p-Kanal-FETPatentansprüche Integrated circuit with at least one n-channel FET and at least one p-channel FET patent claims
1. Integrierte Schaltung mit zumindest einem n-Kanal-FET (4) und zumindest einem p-Kanal-FET (5) , die in einem n-Substrat (1; 2, 3) angeordnet sind,1. Integrated circuit with at least one n-channel FET (4) and at least one p-channel FET (5), which are arranged in an n-substrate (1; 2, 3),
- wobei der n-Kanal-FET (4) eine erste p-Wanne (6) aufweist, und- Wherein the n-channel FET (4) has a first p-well (6), and
- wobei der p-Kanal-FET (5) eine zweite n-Wanne (10) aufweist, die ihrerseits (10) in einer dritten p- Wanne (11) liegt,- The p-channel FET (5) has a second n-well (10), which in turn (10) lies in a third p-well (11),
gekennzeichnet durchmarked by
- eine erste Einrichtung (15, 16, 17), die das n-Sub¬ strat (1; 2, 3) mit einem ersten Potential (VDD) be¬ aufschlagt,a first device (15, 16, 17) which applies a first potential (V DD ) to the n-substrate (1; 2, 3),
- eine zweite Einrichtung (18) , die die erste Wanne (6) mit einem zweiten Potential beaufschlagt, daß kleiner oder gleich dem ersten Potential (VDD) ist,a second device (18) which acts on the first well (6) with a second potential that is less than or equal to the first potential (V DD ),
- eine dritte Einrichtung (20, 21) , die die dritte Wanne (11) mit einem dritten Potential beaufschlagt, das kleiner oder gleich dem ersten Potential (VDD) ist, und- A third device (20, 21) which acts on the third well (11) with a third potential which is less than or equal to the first potential (V DD ), and
- eine vierte Einrichtung (19) , die die zweite Wanne (10) mit einem vierten Potential beaufschlagt, das größer oder gleich dem dritten Potential ist. l O- A fourth device (19) which acts on the second well (10) with a fourth potential which is greater than or equal to the third potential. l O
2. Integrierte Schaltung nach Anspruch 1,2. Integrated circuit according to claim 1,
gekennzeichnet durchmarked by
- eine fünfte Einrichtung (7) , die die Source des n-Kanal-FET (4) mit einem fünften Potential beauf¬ schlagt, das größer oder gleich dem zweiten Poten¬ tial ist,a fifth device (7) which acts on the source of the n-channel FET (4) with a fifth potential which is greater than or equal to the second potential,
- eine sechste Einrichtung (9) r die die Drain des n-Kanal-FET (4) mit einem sechsten Potential be¬ aufschlagt, das größer oder gleich dem zweiten Potential ist,a sixth device (9) r which applies a sixth potential to the drain of the n-channel FET (4) which is greater than or equal to the second potential,
- eine siebte Einrichtung (12) , die die Source des p-Kanal-FET (5) mit einem achten Potential beauf¬ schlagt, das kleiner oder gleich dem vierten Poten¬ tial ist, und- A seventh device (12) which acts on the source of the p-channel FET (5) with an eighth potential which is less than or equal to the fourth potential, and
- eine achte Einrichtung (14) , die die Drain des p-Kanal-FET (5) mit einem neunten Potential beauf¬ schlagt, das kleiner oder gleich dem vierten Poten¬ tial ist.- An eighth device (14) which acts on the drain of the p-channel FET (5) with a ninth potential which is less than or equal to the fourth potential.
Integrierte Schaltung mit zumindest einem p-Kanal-FET (4') und zumindest einem n-Kanal-FET (5'), die in einem p-Substrat (1'; 2', 3') angeordnet sind,Integrated circuit with at least one p-channel FET (4 ') and at least one n-channel FET (5'), which are arranged in a p-substrate (1 '; 2', 3 '),
- wobei der p-Kanal-FET (4') eine erste n-Wanne (6') aufweist, und- wherein the p-channel FET (4 ') has a first n-well (6'), and
- wobei der n-Kanal-FET (5') eine zweite p-Wanne (10') aufweist, die ihrerseits (10') in einer dritten n-Wanne (11') 1iegt,the n-channel FET (5 ') has a second p-well (10') which in turn (10 ') lies in a third n-well (11') 1,
gekennzeichnet durchmarked by
- eine erste Einrichtung (15', 16', 17'), die das p- Substrat (1', 2', - a first device (15 ', 16', 17 ') which the p-substrate (1', 2 ',
3') mit einem ersten Potential (Vss) beaufschlagt, \\3 ') applied with a first potential (V ss ), \\
- eine zweite Einrichtung (18'), die die erste Wanne (6') mit einem zweiten Potential beaufschlagt, das größer oder gleich dem ersten Potential (Vss) ist,a second device (18 ') which applies a second potential to the first trough (6') which is greater than or equal to the first potential (V ss ),
- eine dritte Einrichtung (20', 21'), die die dritte Wanne (11') mit einem dritten Potential beauf¬ schlagt, das größer oder gleich dem ersten Potential (Vss) ist, und- a third device (20 ', 21') which acts on the third well (11 ') with a third potential which is greater than or equal to the first potential (V ss ), and
- eine vierte Einrichtung (19'), die die zweite Wanne (10') mit einem vierten Potential beaufschlagt, das kleiner oder gleich dem dritten Potential ist.- A fourth device (19 ') which acts on the second well (10') with a fourth potential which is less than or equal to the third potential.
4. Integrierte Schaltung nach Anspruch 3,4. Integrated circuit according to claim 3,
gekennzeichnet durchmarked by
- eine fünfte Einrichtung (7'), die die Source des p-Kanal-FET (4') mit einem fünften Potential beauf¬ schlagt, das kleiner oder gleich dem zweiten Poten¬ tial ist,a fifth device (7 ') which acts on the source of the p-channel FET (4') with a fifth potential which is less than or equal to the second potential,
- eine sechste Einrichtung (9'), die die Drain des p-Kanal-FET (4') mit einem sechsten Potential beauf¬ schlagt, das kleiner oder gleich dem zweiten Poten¬ tial ist,a sixth device (9 ') which acts on the drain of the p-channel FET (4') with a sixth potential which is less than or equal to the second potential,
- eine siebte Einrichtung (12'), die die Source des n-Kanal-FET (5') mit einem achten Potential beauf¬ schlagt, das größer oder gleich dem vierten Poten¬ tial ist, und- a seventh device (12 ') which applies an eighth potential to the source of the n-channel FET (5'), which potential is greater than or equal to the fourth potential, and
- eine achte Einrichtung (14'), die die Drain des p-Kanal-FET (5') mit einem neunten Potential beauf¬ schlagt, das größer oder gleich dem vierten Poten¬ tial ist. - An eighth device (14 ') which acts on the drain of the p-channel FET (5') with a ninth potential which is greater than or equal to the fourth potential.
5. Integrierte Schalatung nach einem der Ansprüche 1 bis 4,5. Integrated formwork according to one of claims 1 to 4,
dadurch gekennzeichnet,characterized,
daß die zweite Einrichtung (18; 18') mit der dritten Einrichtung (20, 2l;20', 21') und der fünften Einrich¬ tung (7; 7') derart verbunden ist, daß das zweite Potential (Vss; VDD> gleich dem dritten Potential (VSS' vDü) un< ( em fünften Potential (Vss; VDD) ist.that the second device (18; 18 ') is connected to the third device (20, 2l; 20', 21 ') and the fifth device (7; 7') in such a way that the second potential (V ss ; V DD > is equal to the third potential ( V SS ' v Dü) un <(em fifth potential (V ss ; V DD ).
6. Integrierte Schaltung nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet,6. Integrated circuit according to one of claims 1 to 5, characterized in
daß die vierte Einrichtung (19; 19') mit der ersten Einrichtung (15, 16, 17; 15', 16', 17') und der sieb¬ ten Einrichtung (12; 12') derart verbunden ist, daß das vierte Potential (VDD; Vss) gleich dem ersten Potential (Vj)D; Vss) und dem achten Potential (VDD; Vss) und dem achten Potential (VDD; Vss) ist.that the fourth device (19; 19 ') is connected to the first device (15, 16, 17; 15', 16 ', 17') and the seventh device (12; 12 ') in such a way that the fourth potential (V DD ; V ss ) equal to the first potential (V j) D ; V ss ) and the eighth potential (V DD ; V ss ) and the eighth potential (V DD ; V ss ).
7. Integrierte Schaltung nach einem der Ansprüche l bis 6,7. Integrated circuit according to one of claims 1 to 6,
dadurch gekennzeichnet,characterized,
daß eine erste Isolationsschicht (23) zwischen dem n-Kanal-FET (4") und dem p-Kanal-FET (5") angeordnet ist, die sich von der Substratoberseite bis wenigstens zur Tiefe der dritten Wanne (11") erstreckt.that a first insulation layer (23) is arranged between the n-channel FET (4 ") and the p-channel FET (5"), which extends from the substrate top to at least the depth of the third well (11 ").
8. Integrierte Schaltung nach Anspruch 7,8. Integrated circuit according to claim 7,
dadurch gekennzeichnet,characterized,
daß weitere Isolationsschichten (22, 24) auf der der ersten Isolationsschicht (23) abgewandten Seite der FET's (4", 5") vorgesehen sind, die sich von der Substratoberseite aus bis wenigstens zur Tiefe der ersten bzw. dritten Wanne (6", 11") erstrecken.that further insulation layers (22, 24) on the The first insulation layer (23) facing away from the FETs (4 ", 5") are provided, which extend from the top of the substrate to at least the depth of the first or third well (6 ", 11").
9. Integrierte Schaltung nach Anspruch 7 oder 8,9. Integrated circuit according to claim 7 or 8,
dadurch gekennzeichnet,characterized,
daß die Isolationsschichten als sogenannte Trench- isolationen (22, 23, 24) ausgebildet sind.that the insulation layers are designed as so-called trench insulation (22, 23, 24).
10. Integrierte Schaltung nach einem der Ansprüche 1 bis 9,10. Integrated circuit according to one of claims 1 to 9,
dadurch gekennzeichnet,characterized,
daß die erste Wanne (6"') in die dritte Wanne (11"') übergeht. that the first tub (6 "') merges into the third tub (11"').
PCT/EP1990/000033 1989-01-12 1990-01-08 Integrated circuit with at least one n-channel fet and at least one p-channel fet WO1990008401A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEP3900769.3 1989-01-12
DE19893900769 DE3900769A1 (en) 1989-01-12 1989-01-12 INTEGRATED CIRCUIT WITH AT LEAST ONE N-CHANNEL FET AND AT LEAST ONE P-CHANNEL FET

Publications (1)

Publication Number Publication Date
WO1990008401A1 true WO1990008401A1 (en) 1990-07-26

Family

ID=6371967

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1990/000033 WO1990008401A1 (en) 1989-01-12 1990-01-08 Integrated circuit with at least one n-channel fet and at least one p-channel fet

Country Status (2)

Country Link
DE (1) DE3900769A1 (en)
WO (1) WO1990008401A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0522579A2 (en) * 1991-07-12 1993-01-13 Texas Instruments Incorporated Level-shifter circuit for integrated circuits
GB2269049A (en) * 1992-07-13 1994-01-26 Samsung Electronics Co Ltd Semiconductor memory device
GB2289162A (en) * 1994-05-04 1995-11-08 Hyundai Electronics Ind Semiconductor device with trench isolation and method for fabrication therof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59110153A (en) * 1982-12-15 1984-06-26 Fujitsu Ltd Complementary mis field effect semiconductor device
JPS61101072A (en) * 1984-10-24 1986-05-19 Nec Corp Complementary mos semiconductor device
JPS61194767A (en) * 1985-02-22 1986-08-29 Nec Corp Complementary type mos semiconductor device
JPS62155555A (en) * 1985-09-18 1987-07-10 Sony Corp Complementary mos transistor
JPS62296455A (en) * 1986-06-16 1987-12-23 Mitsubishi Electric Corp Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4306916A (en) * 1979-09-20 1981-12-22 American Microsystems, Inc. CMOS P-Well selective implant method
DE3886283T2 (en) * 1987-07-10 1994-05-11 Toshiba Kawasaki Kk Semiconductor component with areas of different impurity concentration.

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59110153A (en) * 1982-12-15 1984-06-26 Fujitsu Ltd Complementary mis field effect semiconductor device
JPS61101072A (en) * 1984-10-24 1986-05-19 Nec Corp Complementary mos semiconductor device
JPS61194767A (en) * 1985-02-22 1986-08-29 Nec Corp Complementary type mos semiconductor device
JPS62155555A (en) * 1985-09-18 1987-07-10 Sony Corp Complementary mos transistor
JPS62296455A (en) * 1986-06-16 1987-12-23 Mitsubishi Electric Corp Semiconductor device

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 10, no. 283 (E-440)(2339) 26 September 1986, & JP-A-61 101072 (NEC) 19 Mai 1986, siehe das ganze Dokument *
PATENT ABSTRACTS OF JAPAN vol. 11, no. 23 (E-473)(2470) 22 Januar 1987, & JP-A-61 194767 (NEC) 29 August 1986, siehe das ganze Dokument *
PATENT ABSTRACTS OF JAPAN vol. 11, no. 390 (E-567)(2837) 19 Dezember 1987, & JP-A-62 155555 (SONY) 10 Juli 1987, siehe das ganze Dokument *
PATENT ABSTRACTS OF JAPAN vol. 12, no. 193 (E-617)(3040) 04 Juni 1988, & JP-A-62 296455 (MITSUBISHI) 23 Dezember 1987, siehe das ganze Dokument *
PATENT ABSTRACTS OF JAPAN vol. 8, no. 229 (E-273)(1666) 20 Oktober 1984, & JP-A-59 110153 (FUJITSU) 26 Juni 1984, siehe das ganze Dokument *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0522579A2 (en) * 1991-07-12 1993-01-13 Texas Instruments Incorporated Level-shifter circuit for integrated circuits
EP0522579A3 (en) * 1991-07-12 1994-07-20 Texas Instruments Inc Level-shifter circuit for integrated circuits
GB2269049A (en) * 1992-07-13 1994-01-26 Samsung Electronics Co Ltd Semiconductor memory device
GB2289162A (en) * 1994-05-04 1995-11-08 Hyundai Electronics Ind Semiconductor device with trench isolation and method for fabrication therof
GB2289162B (en) * 1994-05-04 1998-07-22 Hyundai Electronics Ind Method for fabricating a semiconductor device

Also Published As

Publication number Publication date
DE3900769A1 (en) 1990-08-09

Similar Documents

Publication Publication Date Title
DE60213889T2 (en) A semiconductor device
DE3816002C2 (en)
DE1918222C3 (en) Insulating gate field effect transistor
DE4110369C2 (en) MOS semiconductor device
DE4037876A1 (en) LATERAL DMOS FET DEVICE WITH REDUCED OPERATING RESISTANCE
DE3145230A1 (en) &#34;SEMICONDUCTOR ARRANGEMENT&#34;
DE19623846A1 (en) SOI-MOS transistor structure
DE2903534A1 (en) FIELD EFFECT TRANSISTOR
DE69724578T2 (en) The SOI MOS field effect transistor
DE19811604A1 (en) Semiconductor component with high breakdown/voltage and SOI substrate
DE102004059627B4 (en) Semiconductor device having a high potential island region
DE2503864B2 (en) Semiconductor component
DE2604088A1 (en) INTEGRATED SEMI-CONDUCTOR CIRCUIT
DE2953931C2 (en)
DE10256575B4 (en) Lateral MOSFET with high breakdown voltage and device equipped therewith
DE2904812C2 (en) Semiconductor memory device in MOS technology
DE19923388A1 (en) Semiconductor memory component with SOI (silicon on insulator) structure and method for its production
EP0052860A2 (en) Monolithic integrated semiconductor bridge circuit
DE2153284A1 (en) Storage matrix
DE2734509A1 (en) INTEGRATED SEMI-CONDUCTOR CIRCUIT
DE2451364C2 (en) Digitally controllable MOS field effect capacitor
DE19902749C2 (en) Power transistor arrangement with high dielectric strength
WO1990008401A1 (en) Integrated circuit with at least one n-channel fet and at least one p-channel fet
DE2415736A1 (en) METAL-SILICON FIELD EFFECT TRANSISTOR
EP0040263B1 (en) Insulated gate field effect transistor

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB IT LU NL SE