US7993981B2 - Electronic device package and method of manufacture - Google Patents

Electronic device package and method of manufacture Download PDF

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Publication number
US7993981B2
US7993981B2 US12/483,139 US48313909A US7993981B2 US 7993981 B2 US7993981 B2 US 7993981B2 US 48313909 A US48313909 A US 48313909A US 7993981 B2 US7993981 B2 US 7993981B2
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Prior art keywords
insulating layer
bonding
metallic
layer
bonding locations
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US12/483,139
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US20100314747A1 (en
Inventor
Qwai Low
Patrick Variot
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Bell Semiconductor LLC
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LSI Corp
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Assigned to LSI CORPORATION reassignment LSI CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LOW, QWAI, VARIOT, PATRICK
Priority to US12/483,139 priority Critical patent/US7993981B2/en
Priority to CN201010202786.7A priority patent/CN101924038B/zh
Priority to TW099118956A priority patent/TWI413210B/zh
Priority to KR1020100054807A priority patent/KR20100133310A/ko
Priority to SG2013042312A priority patent/SG191632A1/en
Priority to JP2010132552A priority patent/JP5784280B2/ja
Priority to EP10165738A priority patent/EP2261962A3/en
Publication of US20100314747A1 publication Critical patent/US20100314747A1/en
Priority to US13/174,970 priority patent/US8384205B2/en
Publication of US7993981B2 publication Critical patent/US7993981B2/en
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Assigned to DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT reassignment DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT PATENT SECURITY AGREEMENT Assignors: AGERE SYSTEMS LLC, LSI CORPORATION
Assigned to AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. reassignment AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LSI CORPORATION
Assigned to LSI CORPORATION, AGERE SYSTEMS LLC reassignment LSI CORPORATION TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Assignors: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Assigned to BANK OF AMERICA, N.A., AS COLLATERAL AGENT reassignment BANK OF AMERICA, N.A., AS COLLATERAL AGENT PATENT SECURITY AGREEMENT Assignors: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Assigned to AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. reassignment AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Assignors: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Assigned to BELL SEMICONDUCTOR, LLC reassignment BELL SEMICONDUCTOR, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., BROADCOM CORPORATION
Assigned to CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT reassignment CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BELL NORTHERN RESEARCH, LLC, BELL SEMICONDUCTOR, LLC, HILCO PATENT ACQUISITION 56, LLC
Assigned to BELL NORTHERN RESEARCH, LLC, HILCO PATENT ACQUISITION 56, LLC, BELL SEMICONDUCTOR, LLC reassignment BELL NORTHERN RESEARCH, LLC RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: CORTLAND CAPITAL MARKET SERVICES LLC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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US12/483,139 2009-06-11 2009-06-11 Electronic device package and method of manufacture Active 2029-12-26 US7993981B2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US12/483,139 US7993981B2 (en) 2009-06-11 2009-06-11 Electronic device package and method of manufacture
CN201010202786.7A CN101924038B (zh) 2009-06-11 2010-06-10 电子器件封装及制造方法
TW099118956A TWI413210B (zh) 2009-06-11 2010-06-10 電子裝置封裝及製造方法
KR1020100054807A KR20100133310A (ko) 2009-06-11 2010-06-10 전자 디바이스 패키지 및 제조방법
SG2013042312A SG191632A1 (en) 2009-06-11 2010-06-10 An electronic device package and method of manufacture
JP2010132552A JP5784280B2 (ja) 2009-06-11 2010-06-10 電子デバイスパッケージ及び製造方法
EP10165738A EP2261962A3 (en) 2009-06-11 2010-06-11 An electronic device package and method of manufacture
US13/174,970 US8384205B2 (en) 2009-06-11 2011-07-01 Electronic device package and method of manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/483,139 US7993981B2 (en) 2009-06-11 2009-06-11 Electronic device package and method of manufacture

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/174,970 Division US8384205B2 (en) 2009-06-11 2011-07-01 Electronic device package and method of manufacture

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8525312B2 (en) * 2011-08-12 2013-09-03 Tessera, Inc. Area array quad flat no-lead (QFN) package

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100015340A1 (en) * 2008-07-17 2010-01-21 Zenergy Power Inc. COMPOSITIONS AND METHODS FOR THE MANUFACTURE OF RARE EARTH METAL-Ba2Cu3O7-delta THIN FILMS
US7993981B2 (en) 2009-06-11 2011-08-09 Lsi Corporation Electronic device package and method of manufacture
US8525334B2 (en) * 2010-04-27 2013-09-03 International Rectifier Corporation Semiconductor on semiconductor substrate multi-chip-scale package
TWI427716B (zh) 2010-06-04 2014-02-21 矽品精密工業股份有限公司 無載具之半導體封裝件及其製法
US9142426B2 (en) * 2011-06-20 2015-09-22 Cyntec Co., Ltd. Stack frame for electrical connections and the method to fabricate thereof
US9275877B2 (en) * 2011-09-20 2016-03-01 Stats Chippac, Ltd. Semiconductor device and method of forming semiconductor package using panel form carrier
US9129951B2 (en) * 2013-10-17 2015-09-08 Freescale Semiconductor, Inc. Coated lead frame bond finger

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258273A1 (en) * 2005-04-07 2008-10-23 Jiangsu Changjiang Electronics Technology Co., Ltd Package Structure With Flat Bumps For Electronic Device and Method of Manufacture the Same
US20080268578A1 (en) * 2001-05-11 2008-10-30 Renesas Technology Corporation Manufacturing method of a semiconductor device
US20090034225A1 (en) * 2007-07-31 2009-02-05 Seiko Epson Corporation Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same
US20090053498A1 (en) * 2003-02-19 2009-02-26 Hidekazu Matsuura Adhesive film for semiconductor use, metal sheet laminated with adhesive film, wiring circuit laminated with adhesive film, and semiconductor device using same, and method for producing semiconductor device
US20090068794A1 (en) * 2005-07-21 2009-03-12 Chipmos Technologies Inc. Manufacturing process for a quad flat non-leaded chip package structure
US20090068797A1 (en) * 2005-07-21 2009-03-12 Chipmos Technologies Inc. Manufacturing process for a quad flat non-leaded chip package structure
US20090283882A1 (en) * 2008-05-19 2009-11-19 Tung-Hsien Hsieh Qfn semiconductor package and fabrication method thereof
US20100129964A1 (en) * 2008-11-26 2010-05-27 Infineon Technologies Ag Method of manufacturing a semiconductor package with a bump using a carrier

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05327224A (ja) * 1992-05-22 1993-12-10 Dainippon Printing Co Ltd 多層配線基板の製造方法及びその製造方法で製造される多層配線基板
JPH11135546A (ja) * 1997-10-31 1999-05-21 Nec Corp 樹脂封止型半導体装置及びその製造方法
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6229200B1 (en) * 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US6635957B2 (en) * 1998-06-10 2003-10-21 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6306685B1 (en) * 2000-02-01 2001-10-23 Advanced Semiconductor Engineering, Inc. Method of molding a bump chip carrier and structure made thereby
JP4653484B2 (ja) * 2002-08-05 2011-03-16 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング 電気的な基板フレームの製造のための方法、表面実装可能な半導体素子の製造のための方法及び半導体素子の製造のための方法
US7851896B2 (en) * 2005-07-14 2010-12-14 Chipmos Technologies Inc. Quad flat non-leaded chip package
US7803666B2 (en) * 2005-07-21 2010-09-28 Chipmos Technologies Inc. Manufacturing process for a Quad Flat Non-leaded chip package structure
US7795079B2 (en) * 2005-07-21 2010-09-14 Chipmos Technologies Inc. Manufacturing process for a quad flat non-leaded chip package structure
TWI255561B (en) * 2005-07-21 2006-05-21 Chipmos Technologies Inc Manufacturing process for chip package without core
TWI293237B (en) * 2005-12-30 2008-02-01 Advanced Semiconductor Eng Method for manufacturing a substrate embedded with an electronic component and device from the same
JP5113346B2 (ja) * 2006-05-22 2013-01-09 日立電線株式会社 電子装置用基板およびその製造方法、ならびに電子装置およびその製造方法
CN100524676C (zh) * 2007-01-18 2009-08-05 南茂科技股份有限公司 冲裁式无外引脚封装构造及其制造方法
US7919851B2 (en) * 2008-06-05 2011-04-05 Powertech Technology Inc. Laminate substrate and semiconductor package utilizing the substrate
US7993981B2 (en) 2009-06-11 2011-08-09 Lsi Corporation Electronic device package and method of manufacture

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080268578A1 (en) * 2001-05-11 2008-10-30 Renesas Technology Corporation Manufacturing method of a semiconductor device
US20090053498A1 (en) * 2003-02-19 2009-02-26 Hidekazu Matsuura Adhesive film for semiconductor use, metal sheet laminated with adhesive film, wiring circuit laminated with adhesive film, and semiconductor device using same, and method for producing semiconductor device
US20080258273A1 (en) * 2005-04-07 2008-10-23 Jiangsu Changjiang Electronics Technology Co., Ltd Package Structure With Flat Bumps For Electronic Device and Method of Manufacture the Same
US20090068794A1 (en) * 2005-07-21 2009-03-12 Chipmos Technologies Inc. Manufacturing process for a quad flat non-leaded chip package structure
US20090068797A1 (en) * 2005-07-21 2009-03-12 Chipmos Technologies Inc. Manufacturing process for a quad flat non-leaded chip package structure
US20090034225A1 (en) * 2007-07-31 2009-02-05 Seiko Epson Corporation Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same
US20090283882A1 (en) * 2008-05-19 2009-11-19 Tung-Hsien Hsieh Qfn semiconductor package and fabrication method thereof
US20100129964A1 (en) * 2008-11-26 2010-05-27 Infineon Technologies Ag Method of manufacturing a semiconductor package with a bump using a carrier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8525312B2 (en) * 2011-08-12 2013-09-03 Tessera, Inc. Area array quad flat no-lead (QFN) package

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EP2261962A2 (en) 2010-12-15
US20100314747A1 (en) 2010-12-16
JP2010287893A (ja) 2010-12-24
TWI413210B (zh) 2013-10-21
US8384205B2 (en) 2013-02-26
KR20100133310A (ko) 2010-12-21
EP2261962A3 (en) 2013-02-27
CN101924038A (zh) 2010-12-22
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US20110260324A1 (en) 2011-10-27
SG191632A1 (en) 2013-07-31
JP5784280B2 (ja) 2015-09-24

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