US20230307411A1 - Semiconductor module - Google Patents

Semiconductor module Download PDF

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Publication number
US20230307411A1
US20230307411A1 US18/005,048 US202118005048A US2023307411A1 US 20230307411 A1 US20230307411 A1 US 20230307411A1 US 202118005048 A US202118005048 A US 202118005048A US 2023307411 A1 US2023307411 A1 US 2023307411A1
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Prior art keywords
semiconductor elements
conductive
semiconductor
input terminal
semiconductor module
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Abandoned
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US18/005,048
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English (en)
Inventor
Kenji Hayashi
Kohei Tanikawa
Ryosuke Fukuda
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Rohm Co Ltd
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Rohm Co Ltd
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Assigned to ROHM CO., LTD. reassignment ROHM CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TANIKAWA, KOHEI, HAYASHI, KENJI, FUKUDA, Ryosuke
Publication of US20230307411A1 publication Critical patent/US20230307411A1/en
Abandoned legal-status Critical Current

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    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Definitions

  • the present disclosure relates to a semiconductor module.
  • Patent Document 1 discloses a conventional semiconductor module (power module).
  • the semiconductor module described in Patent Document 1 includes a semiconductor element and a supporting substrate (ceramic substrate).
  • the semiconductor element is an IGBT made of silicon (Si), for example.
  • the supporting substrate supports the semiconductor element.
  • the supporting substrate includes an insulating base member and conductor layers stacked on the respective surfaces of the base member.
  • the base member is made of ceramic, for example.
  • Each of the conductor layers is made of copper (Cu), for example, and the semiconductor element is bonded to one of the conductor layers.
  • Patent Document 1 JP-A-2015-220382
  • an object of the present disclosure is to provide a semiconductor module having a module structure preferable for equalizing parasitic inductance components along the path of a main circuit current and for equalizing the amount of current to a semiconductor element.
  • a semiconductor module provided by the present disclosure includes: a conductive substrate having an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction; at least one semiconductor element electrically bonded to the obverse surface and having a switching function; a conducting member that forms a path of a main circuit current switched by the plurality of semiconductor elements; a first input terminal and a second input terminal that are offset in one sense of a first direction relative to the conductive substrate, the first direction being perpendicular to the thickness direction; and at least one output terminal offset in another sense of the first direction relative to the conductive substrate.
  • the conductive substrate includes a first conductive portion and a second conductive portion that are spaced apart from each other in the first direction.
  • the at least one semiconductor element includes a plurality of first semiconductor elements electrically bonded to the first conductive portion, and a plurality of second semiconductor elements electrically bonded to the second conductive portion.
  • the plurality of first semiconductor elements are spaced apart from each other along a second direction perpendicular to the thickness direction and the first direction.
  • the plurality of second semiconductor elements are spaced apart from each other along the second direction.
  • the first input terminal is electrically connected to the first conductive portion.
  • the second input terminal has an opposite polarity to the first input terminal.
  • the output terminal is electrically connected to the second conductive portion.
  • the conducting member includes a first conducting member connected to the plurality of first semiconductor elements and the second conductive portion, and a second conducting member connected to the plurality of second semiconductor elements and the second input terminal.
  • the configuration as described above can provide a module structure preferable for equalizing parasitic inductance components along the path of a main circuit current and for equalizing the amount of current to a semiconductor element.
  • FIG. 1 is a perspective view illustrating a semiconductor module according to a first embodiment.
  • FIG. 2 is a perspective view corresponding to FIG. 1 but omitting a sealing resin, a resin member, and a resin-filling portion.
  • FIG. 3 is a perspective view corresponding to FIG. 2 but omitting a conducting member.
  • FIG. 4 is a plan view illustrating the semiconductor module according to the first embodiment.
  • FIG. 5 is a plan view corresponding to FIG. 4 but showing the sealing resin, the resin member, and the resin-filling portion with imaginary lines.
  • FIG. 6 is a partially enlarged view showing a part of FIG. 5 but omitting the imaginary lines of the sealing resin, the resin member, and the resin-filling portion.
  • FIG. 7 is a partially enlarged view showing a part of FIG. 6 .
  • FIG. 8 is a plan view corresponding to FIG. 5 but showing a part of the conducting member with an imaginary line.
  • FIG. 9 is a front view illustrating the semiconductor module according to the first embodiment.
  • FIG. 10 is a bottom view illustrating the semiconductor module according to the first embodiment.
  • FIG. 11 is a left side view illustrating the semiconductor module according to the first embodiment.
  • FIG. 12 is a right side view illustrating the semiconductor module according to the first embodiment.
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII of FIG. 5 .
  • FIG. 14 is a cross-sectional view taken along line XIV-XIV of FIG. 5 .
  • FIG. 15 is a partially enlarged view showing a part of FIG. 14 .
  • FIG. 16 is a cross-sectional view taken along line XVI-XVI of FIG. 5 .
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII of FIG. 5 .
  • FIG. 18 is a cross-sectional view taken along line XVIII-XVIII of FIG. 5 .
  • FIG. 19 is a cross-sectional view taken along line XIX-XIX of FIG. 5 .
  • FIG. 20 shows an example of the circuit configuration of the semiconductor module according to the first embodiment.
  • FIG. 21 is a plan view illustrating a step of a method for manufacturing the semiconductor module according to the first embodiment.
  • FIG. 22 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor module according to the first embodiment.
  • FIG. 23 is a plan view illustrating a step of the method for manufacturing the semiconductor module according to the first embodiment.
  • FIG. 24 is a cut end view illustrating a step of the manufacturing method according to the first embodiment, and corresponds to the cross-sectional view of FIG. 13 .
  • FIG. 25 is a partially enlarged cross-sectional view illustrating a step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross-section in FIG. 13 .
  • FIG. 26 is a partially enlarged cross-sectional view illustrating a step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross-section in FIG. 14 .
  • FIG. 27 is a partially enlarged cross-sectional view illustrating a step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross-section in FIG. 14 .
  • FIG. 28 is a partially enlarged cross-sectional view illustrating a step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross-section in FIG. 13 .
  • FIG. 29 is a partially enlarged cross-sectional view illustrating a step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross-section in FIG. 14 .
  • FIG. 30 is a plan view similar to FIG. 5 , illustrating a semiconductor module according to a second embodiment.
  • FIG. 31 is a partially enlarged view showing a part of FIG. 30 but omitting the imaginary lines of the sealing resin, the resin member, and the resin-filling portion.
  • FIG. 32 is a partially enlarged view showing a part of FIG. 31 .
  • FIG. 33 is a plan view similar to FIG. 5 , illustrating a semiconductor module according to a third embodiment.
  • FIG. 34 is a cross-sectional view taken along line XXXIV-XXXIV of FIG. 33 .
  • FIGS. 1 to 20 illustrate a semiconductor module A1 according to a first embodiment.
  • the semiconductor module A1 includes a plurality of semiconductor elements 10, a conductive substrate 2, a supporting substrate 3, a plurality of input terminals 41 to 43, a plurality of output terminals 44, a plurality of control terminals 45, a control terminal support 5, a conducting member 6, a first conductive bonding member 71, a second conductive bonding member 72, a plurality of wires 731 to 735, a sealing resin 8, resin members 87, and resin-filling portions 88.
  • FIG. 1 is a perspective view illustrating the semiconductor module A1.
  • FIG. 2 is a perspective view corresponding to FIG. 1 but omitting the sealing resin 8, the resin members 87, and the resin-filling portions 88.
  • FIG. 3 is a perspective view corresponding to FIG. 2 but omitting the conducting member 6.
  • FIG. 4 is a plan view illustrating the semiconductor module A1.
  • FIG. 5 is a plan view corresponding to FIG. 4 but showing the sealing resin 8, the resin members 87, and the resin-filling portions 88 with imaginary lines.
  • FIG. 6 is a partially enlarged view showing a part of FIG. 5 . In FIG. 6 , the imaginary lines of the sealing resin 8, the resin members 87, and the resin-filling portions 88 are omitted.
  • FIG. 6 the imaginary lines of the sealing resin 8, the resin members 87, and the resin-filling portions 88 are omitted.
  • FIG. 7 is a partially enlarged view showing a part of FIG. 6 .
  • FIG. 8 is a plan view corresponding to FIG. 5 but showing a part of the conducting member 6 (a second conducting member 62 described below) with an imaginary line.
  • FIG. 9 is a front view illustrating the semiconductor module A1.
  • FIG. 10 is a bottom view illustrating the semiconductor module A1.
  • FIG. 11 is a left side view illustrating the semiconductor module A1.
  • FIG. 12 is a right side view illustrating the semiconductor module A1.
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII of FIG. 5 .
  • FIG. 14 is a cross-sectional view taken along line XIV-XIV of FIG. 5 .
  • FIG. 15 is a partially enlarged view showing a part of FIG. 14 .
  • FIG. 16 is a cross-sectional view taken along line XVI-XVI of FIG. 5 .
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII of FIG. 5 .
  • FIG. 18 is a cross-sectional view taken along line XVIII-XVIII of FIG. 5 .
  • FIG. 19 is a cross-sectional view taken along line XIX-XIX of FIG. 5 .
  • the wires 731 to 735 are omitted.
  • FIG. 20 shows an example of the circuit configuration of the semiconductor module A1. In the circuit diagram of FIG.
  • the z direction corresponds to the thickness direction of the semiconductor module A1.
  • the x direction corresponds to the horizontal direction in the plan view (see FIG. 4 ) of the semiconductor module A1.
  • the y direction corresponds to the vertical direction in the plan view (see FIG. 4 ) of the semiconductor module A1.
  • One sense of the x direction is defined as x1 direction, and the other sense as x2 direction.
  • the same rule applies to the y direction and the z direction.
  • “as viewed in the z direction” means “plan view”.
  • the x direction is an example of a “first direction”
  • the y direction is an example of a “second direction”.
  • the semiconductor elements 10 form the functional core of the semiconductor module A1.
  • the semiconductor elements 10 are made of a semiconductor material that mainly contains silicon carbide (SiC), for example.
  • the semiconductor material is not limited to SiC, and may be silicon (Si), gallium arsenide (GaAs) or gallium nitride (GaN).
  • Each of the semiconductor elements 10 has a switching function unit Q1 (see FIG. 20 ) composed of a metal-oxide-semiconductor field-effect transistor (MOSFET), for example.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • the switching function unit Q1 is not limited to a MOSFET, and may be another transistor, which is, for example, a field-effect transistor such as a metal-insulator-semiconductor FET (MISFET) or a bipolar transistor such as an IGBT.
  • the semiconductor elements 10 are the same elements.
  • the semiconductor elements 10 are n-channel MOSFETs, for example, but may be p-channel MOSFETs instead.
  • each of the semiconductor elements 10 has an element obverse surface 101 and an element reverse surface 102.
  • the element obverse surface 101 and the element reverse surface 102 of each semiconductor element 10 are spaced apart from each other in the z direction.
  • the element obverse surface 101 faces in the z2 direction, and the element reverse surface 102 faces in the z1 direction.
  • the semiconductor elements 10 include a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B.
  • the semiconductor module A1 includes three first semiconductor elements 10A and three second semiconductor elements 10B.
  • the number of first semiconductor elements 10A and the number of second semiconductor elements 10B are not limited thereto, and may be changed as appropriate according to the performance required for the semiconductor module A1.
  • three first semiconductor elements 10A and three second semiconductor elements 10B are provided.
  • the number of first semiconductor elements 10A and the number of second semiconductor elements 10B may each be one, two, or no less than four.
  • the number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be equal or different.
  • the number of first semiconductor elements 10A and the number of second semiconductor elements 10B are determined according to the current capacity handled by the semiconductor module A1.
  • the semiconductor module A1 may be configured as a half-bridge switching circuit.
  • the first semiconductor elements 10A constitute an upper arm circuit of the semiconductor module A1
  • the second semiconductor elements 10B constitute a lower arm circuit of the semiconductor module A1.
  • the first semiconductor elements 10A are connected in parallel to each other
  • the second semiconductor elements 10B are connected in parallel to each other.
  • Each of the first semiconductor elements 10A and each of the second semiconductor elements 10B are connected in series to form a bridge layer.
  • the first semiconductor elements 10A are mounted on the conductive substrate 2.
  • the first semiconductor elements 10A are aligned in the y direction and spaced apart from each other.
  • the first semiconductor elements 10A are electrically bonded to the conductive substrate 2 (a first conductive portion 2A described below) via the second conductive bonding member 72.
  • the element reverse surfaces 102 face the first conductive portion 2A.
  • the second semiconductor elements 10B are mounted on the conductive substrate 2.
  • the second semiconductor elements 10B are aligned in the y direction and spaced apart from each other.
  • the second semiconductor elements 10B are electrically bonded to the conductive substrate 2 (a second conductive portion 2B described below) via the second conductive bonding member 72.
  • the element reverse surfaces 102 face the second conductive portion 2B.
  • the first semiconductor elements 10A and the second semiconductor elements 10B overlap with each other as viewed in the x direction, but the present disclosure is not limited to this.
  • Each of the semiconductor elements 10 has a first obverse-surface electrode 11, a second obverse-surface electrode 12, and a reverse-surface electrode 15.
  • the configurations of the first obverse-surface electrode 11, the second obverse-surface electrode 12, and the reverse-surface electrode 15, which are described below, are common to each of the semiconductor elements 10.
  • the first obverse-surface electrode 11 and the second obverse-surface electrode 12 are mounted on the element obverse surface 101.
  • the first obverse-surface electrode 11 and the second obverse-surface electrode 12 are insulated from each other by an insulating film (not illustrated).
  • the reverse-surface electrode 15 is provided on the element reverse surface 102.
  • the first obverse-surface electrode 11 is a gate electrode, for example, to which a drive signal (e.g., gate voltage) for driving the semiconductor element 10 is inputted.
  • the second obverse-surface electrode 12 is a source electrode, for example, through which a source current flows.
  • the reverse-surface electrode 15 is a drain electrode, for example, through which a drain current flows.
  • the reverse-surface electrode 15 almost entirely covers the element reverse surface 102.
  • the reverse-surface electrode 15 may be formed by Ag plating.
  • Each of the semiconductor elements 10 switches between a connected state and a disconnected state according to a drive signal (gate voltage), which is input to the first obverse-surface electrode 11 (gate electrode) via the switching function unit Q1.
  • the operation of switching between the connected state and the disconnected state is referred to as a switching operation.
  • a current flows from the reverse-surface electrode 15 (drain electrode) to the second obverse-surface electrode 12 (source electrode).
  • the current does not flow.
  • each of the semiconductor elements 10 performs a switching operation through the switching function unit Q1.
  • the semiconductor module A1 converts a first power supply voltage (DC voltage) inputted between the input terminal 41 and the two input terminals 42, 43 to a second power supply voltage (AC voltage) by the switching function units Q1 of the semiconductor elements 10, for example, and outputs the second power supply voltage from the output terminals 44.
  • the input terminals 41 to 43 and the output terminals 44 are power supply terminals that handle power supply voltage.
  • the input terminals 41 to 43 are first power supply terminals that receive the first source voltage.
  • the output terminals 44 are second power supply terminals that output the second source voltage.
  • the semiconductor elements 10 each have a diode function unit D1 (see FIG. 20 ) in addition to the switching function unit Q1.
  • one of the first semiconductor elements 10A i.e., the first semiconductor element 10A offset furthest in the y2 direction in FIG. 8
  • one of the second semiconductor elements 10B i.e., the second semiconductor element 10B offset furthest in the y1 direction in FIG. 8
  • the function and role of the diode function unit D1 is not particularly limited but one example of the diode function unit D1 is a temperature detection diode.
  • the diode D2 in FIG. 20 is, for example, a parasitic diode component of the switching function unit Q1.
  • each of the semiconductor elements 10 having the diode function units D1 has a third obverse-surface electrode 13, a fourth obverse-surface electrode 14, and a fifth obverse-surface electrode 16, in addition to the first obverse-surface electrode 11, the second obverse-surface electrode 12, and the reverse-surface electrode 15.
  • the configurations of the third obverse-surface electrode 13, the fourth obverse-surface electrode 14, and the fifth obverse-surface electrode 16, which are described below, are common to each of the semiconductor elements 10 having the diode function units D1.
  • the third obverse-surface electrode 13, the fourth obverse-surface electrode 14, and the fifth obverse-surface electrode 16 are formed on the element obverse surface 101.
  • the third obverse-surface electrode 13 and the fourth obverse-surface electrode 14 are electrically connected to the diode function unit D1.
  • the fifth obverse-surface electrode 16 is a source sense electrode, for example, through which a source current in the switching function unit Q1 flows.
  • each of the first semiconductor elements 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 in plan view.
  • FIG. 7 illustrates the first semiconductor element 10A arranged in the middle in the y direction among the first semiconductor elements 10A aligned in the y direction, but each of the other first semiconductor elements 10A also similarly has a first side 191, a second side 192, a third side 193, and a fourth side 194.
  • the first side 191 and the second side 192 extend in the y direction.
  • the first side 191 is an edge located in the x2 direction in plan view
  • the second side 192 is an edge located in the x1 direction in plan view.
  • the third side 193 and the fourth side 194 extend in the x direction.
  • the third side 193 is an edge located in the y2 direction in plan view
  • the fourth side 194 is an edge located in the y1 direction in plan view. Since each of the first semiconductor elements 10A has a rectangular shape in plan view, the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 are generally right-angled in plan view. As shown in FIG. 7 , the four corners do not overlap with the conducting member 6 (first conducting members 61 and a second conducting member 62 described below) in plan view.
  • the third side 193 and the fourth side 194 are longer than the first side 191 and the second side 192.
  • the conductive substrate 2 is also referred to as a lead frame.
  • the conductive substrate 2 supports the semiconductor elements 10.
  • the conductive substrate 2 is bonded to the supporting substrate 3 via the first conductive bonding member 71.
  • the conductive substrate 2 has a rectangular shape in plan view, for example.
  • the conductive substrate 2, together with the conducting member 6, forms the path of a main circuit current switched by the semiconductor elements 10.
  • the conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B.
  • the first conductive portion 2A and the second conductive portion 2B are plate-like members made of metal.
  • the metal is copper (Cu) or a Cu alloy, for example.
  • the first conductive portion 2A and the second conductive portion 2B form a conductive path to the semiconductor elements 10, together with the input terminals 41 to 43 and the output terminals 44.
  • the first conductive portion 2A and the second conductive portion 2B are bonded to the supporting substrate 3 via the first conductive bonding member 71.
  • the first semiconductor elements 10A are bonded to the first conductive portion 2A via the second conductive bonding member 72.
  • the second semiconductor elements 10B are bonded to the second conductive portion 2B via the second conductive bonding member 72.
  • the first conductive portion 2A and the second conductive portion 2B are spaced apart from each other in the x direction.
  • the first conductive portion 2A is offset in the x2 direction relative to the second conductive portion 2B.
  • the first conductive portion 2A and the second conductive portion 2B each have a rectangular shape in plan view, for example.
  • the first conductive portion 2A and the second conductive portion 2B overlap with each other as viewed in the x direction.
  • the first conductive portion 2A and the second conductive portion 2B may each have a dimension of 15 mm to 25 mm (preferably about 20 mm) in the x direction, a dimension of 30 mm to 40 mm (preferably about 35 mm) in the y direction, and a dimension of 1.5 mm to 3.0 mm (preferably about 2.0 mm) in the z direction.
  • the conductive substrate 2 has an obverse surface 201 and a reverse surface 202. As shown in FIGS. 13 , 14 , and 16 to 18 , the obverse surface 201 and the reverse surface 202 are spaced apart from each other in the z direction.
  • the obverse surface 201 faces in the z2 direction, and the reverse surface 202 faces in the z1 direction.
  • the obverse surface 201 is a combination of the upper surface of the first conductive portion 2A and the upper surface of the second conductive portion 2B.
  • the reverse surface 202 is a combination of the lower surface of the first conductive portion 2A and the lower surface of the second conductive portion 2B.
  • the reverse surface 202 faces the supporting substrate 3 and is bonded to the supporting substrate 3.
  • the obverse surface 201 is formed with a plurality of recessed portions 201a.
  • the recessed portions 201a are recessed from the obverse surface 201 in the z direction.
  • the degree of recession (depth) of each recessed portion 201a is greater than 0 ⁇ m and less than or equal to 100 ⁇ m, for example.
  • the recessed portions 201a are formed during molding described below, for example.
  • the recessed portions 201a include those formed in the obverse surface 201 of the first conductive portion 2A, and those formed in the obverse surface 201 of the second conductive portion 2B.
  • Two recessed portions 201a formed in the obverse surface 201 of the first conductive portion 2A are spaced apart from each other in the y direction and overlap with each other as viewed in the y direction.
  • Two recessed portions 201a formed in the obverse surface 201 of the second conductive portion 2B are spaced apart from each other in the y direction and overlap with each other as viewed in the y direction.
  • the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B) includes a base member 21, an obverse-surface bonding layer 22, and a reverse-surface bonding layer 23 that are stacked on each other.
  • the base member 21 is a plate-like member made of metal.
  • the metal is Cu or a Cu alloy.
  • the obverse-surface bonding layer 22 is formed on the upper surface of the base member 21.
  • the obverse-surface bonding layer 22 is the surface layer of the conductive substrate 2 in the z2 direction.
  • the upper surface of the obverse-surface bonding layer 22 corresponds to the obverse surface 201 of the conductive substrate 2.
  • the obverse-surface bonding layer 22 is a Ag plating layer, for example.
  • the reverse-surface bonding layer 23 is formed on the lower surface of the base member 21.
  • the reverse-surface bonding layer 23 is the surface layer of the conductive substrate 2 in the z1 direction.
  • the lower surface of the reverse-surface bonding layer 23 corresponds to the reverse surface 202 of the conductive substrate 2.
  • the reverse-surface bonding layer 23 is a Ag plating layer, for example, as is the obverse-surface bonding layer 22.
  • the supporting substrate 3 supports the conductive substrate 2.
  • the supporting substrate 3 is a direct bonded copper (DBC) substrate, for example.
  • the supporting substrate 3 includes an insulating layer 31, a first metal layer 32, a first bonding layer 321, and a second metal layer 33.
  • the insulating layer 31 is made of a ceramic with excellent thermal conductivity, for example.
  • the ceramic may be aluminum nitride (AlN).
  • the insulating layer 31 is not limited to a ceramic, and may be an insulating resin sheet, for example.
  • the insulating layer 31 has a rectangular shape in plan view, for example.
  • the first metal layer 32 is formed on the upper surface (surface facing in the z2 direction) of the insulating layer 31.
  • the material of the first metal layer 32 contains Cu, for example.
  • the material may contain Al instead of Cu.
  • the first metal layer 32 includes a first portion 32A and a second portion 32B.
  • the first portion 32A and the second portion 32B are spaced apart from each other in the x direction.
  • the first portion 32A is offset in the x2 direction relative to the second portion 32B.
  • the first portion 32A is bonded to the first conductive portion 2A and supports the first conductive portion 2A.
  • the second portion 32B is bonded to the second conductive portion 2B and supports the second conductive portion 2B.
  • the first portion 32A and the second portion 32B each have a rectangular shape in plan view, for example.
  • the first bonding layer 321 is formed on the upper surface of the first metal layer 32 (each of the first portion 32A and the second portion 32B).
  • the first bonding layer 321 is a Ag plating layer, for example.
  • the first bonding layer 321 is provided to enhance the solid-phase diffusion bonding with the first conductive bonding member 71.
  • the second metal layer 33 is formed on the lower surface of the insulating layer 31 (surface facing in the z1 direction).
  • the second metal layer 33 is made of the same material as the first metal layer 32.
  • the lower surface (a bottom surface 302 described below) of the second metal layer 33 is exposed from the sealing resin 8.
  • the lower surface may not be exposed from the sealing resin 8, and may be covered with the sealing resin 8.
  • the second metal layer 33 may overlap with the first portion 32A and the second portion 32B in plan view.
  • the supporting substrate 3 has a supporting surface 301 and a bottom surface 302.
  • the supporting surface 301 and the bottom surface 302 are spaced apart from each other in the z direction.
  • the supporting surface 301 faces in the z2 direction, and the bottom surface 302 faces in the z1 direction.
  • the bottom surface 302 is exposed from the sealing resin 8.
  • the supporting surface 301 is the upper surface of the first bonding layer 321, i.e., a combination of the upper surface of the first portion 32A and the upper surface of the second portion 32B.
  • the supporting surface 301 faces the conductive substrate 2, and is bonded to the conductive substrate 2.
  • the bottom surface 302 is the lower surface of the second metal layer 33.
  • a heat dissipating member e.g., heat sink or the like, which is not illustrated in the figure, can be attached to the bottom surface 302.
  • the dimension of the supporting substrate 3 in the z direction is 0.7 mm to 2.0 mm, for example.
  • Each of the input terminals 41 to 43 and the output terminals 44 is a plate-like metal plate.
  • the metal plate is made of Cu or a Cu alloy, for example.
  • the semiconductor module A1 includes the three input terminals 41 to 43 and the two output terminals 44.
  • the input terminal 41 is a positive electrode (P terminal), and the two input terminals 42 and 43 are negative electrodes (N terminal).
  • the input terminal 41 may be a negative terminal (N terminal), and the two input terminals 42 and 43 may be positive terminals (P terminals) .
  • the wiring in the package may be appropriately changed according to the change in the polarity of each terminal.
  • Each of the three input terminals 41 to 43 and the two output terminals 44 includes a portion covered with the sealing resin 8 and a portion exposed from a resin side surface of the sealing resin 8.
  • the input terminal 41 is formed integrally with the first conductive portion 2A. Unlike this configuration, the input terminal 41 may be separated from the first conductive portion 2A and electrically bonded to the first conductive portion 2A. As shown in FIG. 8 , for example, the input terminal 41 is offset in the x2 direction relative to the first semiconductor elements 10A and the first conductive portion 2A (conductive substrate 2). The input terminal 41 is electrically connected to the first conductive portion 2A, and is electrically connected to the reverse-surface electrodes 15 (drain electrodes) of the first semiconductor elements 10A via the first conductive portion 2A. The input terminal 41 is an example of a “first input terminal”.
  • the input terminal 41 has an input-side bonding surface 411 and input-side side surfaces 412.
  • the input-side bonding surface 411 faces in the z2 direction and extends in the x2 direction.
  • Each of the input-side side surfaces 412 is located at the periphery of the input-side bonding surface 411 as viewed in the z direction, and faces in a direction intersecting with the input-side bonding surface 411.
  • the input-side side surfaces 412 include a tip surface 413 and a pair of lateral surfaces 414.
  • the tip surface 413 is positioned at the end of the input terminal 41 in the x2 direction and faces in the x2 direction.
  • the pair of lateral surfaces 414 are located at the respective ends of the input terminal 41 in the y direction, and face in the y1 direction and the y2 direction, respectively.
  • the input-side side surfaces 412 at least one of the tip surface 413 and the pair of lateral surfaces 414 has an input-side machining mark.
  • the input-side machining mark is formed by the cutting process of a lead frame as described below.
  • the two input terminals 42 and 43 are spaced apart from the first conductive portion 2A.
  • the two input terminals 42 and 43 are bonded to the second conducting member 62.
  • the two input terminals 42 and 43 are offset in the x2 direction relative to the first semiconductor elements 10A and the first conductive portion 2A (conductive substrate 2).
  • the two input terminals 42 and 43 are electrically connected to the second conducting member 62, and are electrically connected to the second obverse-surface electrodes 12 (source electrodes) of the second semiconductor elements 10B via the second conducting member 62.
  • the input terminal 42 is an example of a “second input terminal”
  • the input terminal 43 is an example of a “third input terminal”.
  • the input terminal 42 has an input-side bonding surface 421 and input-side side surfaces 422, and the input terminal 43 has an input-side bonding surface 431 and input-side side surfaces 432.
  • the input-side bonding surfaces 421 and 431 face in the z2 direction, and extend in the x2 direction.
  • Each of the input-side side surfaces 422 is located at the periphery of the input-side bonding surface 421 as viewed in the z direction, and faces in a direction intersecting with the input-side bonding surface 421.
  • Each of the input-side side surfaces 432 is located at the periphery of the input-side bonding surface 431 as viewed in the z direction, and faces in a direction intersecting with the input-side bonding surface 431.
  • the input-side side surfaces 422 include a tip surface 423 and a pair of lateral surfaces 424.
  • the tip surface 423 is positioned at the end of the input terminal 42 in the x2 direction and faces in the x2 direction.
  • the pair of lateral surfaces 424 are located at the respective ends of the input terminal 42 in the y direction, and face in the y1 direction and the y2 direction, respectively.
  • at least one of the tip surface 423 and the pair of lateral surfaces 424 has an input-side machining mark.
  • the input-side machining mark is formed by the cutting process of a lead frame as described below.
  • the input-side side surfaces 432 include a tip surface 433 and a pair of lateral surfaces 434.
  • the tip surface 433 is positioned at the end of the input terminal 43 in the x2 direction and faces in the x2 direction.
  • the pair of lateral surfaces 434 are located at the respective ends of the input terminal 43 in the y direction, and face in the y1 direction and the y2 direction, respectively.
  • the input-side side surfaces 432 at least one of the tip surface 433 and the pair of lateral surfaces 434 has an input-side machining mark.
  • the input-side machining mark is formed by the cutting process of a lead frame as described below.
  • the three input terminals 41 to 43 of the semiconductor module A1 protrude from the sealing resin 8 in the x2 direction.
  • the three input terminals 41 to 43 are spaced apart from each other.
  • the two input terminals 42 and 43 are located opposite from each other with the input terminal 41 therebetween in the y direction.
  • the input terminal 42 is offset in the y2 direction relative to the input terminal 41, and the input terminal 43 is offset in the y1 direction relative to the input terminal 41.
  • the three input terminals 41 to 43 overlap with each other as viewed in the y direction.
  • the two output terminals 44 are integrally formed with the second conductive portion 2B. Unlike this configuration, the output terminals 44 may be separated from the second conductive portion 2B and electrically bonded to the second conductive portion 2B. As shown in FIG. 8 , for example, the two output terminals 44 are offset in the x1 direction relative to the second semiconductor elements 10B and the second conductive portion 2B (conductive substrate 2). The output terminals 44 are electrically connected to the second conductive portion 2B, and are electrically connected to the reverse-surface electrodes 15 (drain electrodes) of the second semiconductor elements 10B via the second conductive portion 2B.
  • the two output terminals 44 are examples of a “first output terminal” and a “second output terminal”.
  • Each of the output terminals 44 has an output-side bonding surface 441 and output-side side surfaces 442.
  • the output-side bonding surface 441 faces in the z2 direction and extends in the x1 direction.
  • Each of the output-side side surfaces 442 is located at the periphery of the output-side bonding surface 441 as viewed in the z direction, and faces in a direction intersecting with the output-side bonding surface 441.
  • the output-side side surfaces 442 include a tip surface 443 and a pair of lateral surfaces 444.
  • the tip surface 443 is positioned at the end of the output terminal 44 in the x1 direction and faces in the x1 direction.
  • the pair of lateral surfaces 444 are located at the respective ends of the output terminal 44 in the y direction, and face in the y1 direction and the y2 direction, respectively.
  • the output-side side surfaces 442 at least one of the tip surface 443 and the pair of lateral surfaces 444 has an output-side machining mark.
  • the output-side machining mark is formed by the cutting process of a lead frame as described below.
  • the number of output terminals 44 is not limited to two, and may be one or no less than three. When the number of output terminals 44 is one, it is desirable that the output terminal 44 be connected to the middle section of the second conductive portion 2B in the y direction.
  • the control terminals 45 are pin-like terminals for controlling the semiconductor elements 10.
  • the control terminals 45 include a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D.
  • the first control terminals 46A to 46E are used to control the first semiconductor elements 10A.
  • the second control terminals 47A to 47D are used to control the second semiconductor elements 10B.
  • the first control terminals 46A to 46E are arranged at intervals in the y direction. As shown in FIGS. 8 and 14 , for example, the first control terminals 46A to 46E are supported by the first conductive portion 2A via the control terminal support 5 (a first supporting portion 5A described below) . As shown in FIGS. 5 and 8 , the first control terminals 46A to 46E are located between the first semiconductor elements 10A and the three input terminals 41 to 43 in the x direction.
  • the first control terminal 46A is a terminal (gate terminal) used to input a drive signal for the first semiconductor elements 10A.
  • the first control terminal 46A receives the drive signal for driving the first semiconductor elements 10A (e.g., it receives application of gate voltage).
  • the first control terminal 46B is a terminal (source sense terminal) used to detect a source signal for the first semiconductor elements 10A. Voltage (corresponding to a source current) applied to the second obverse-surface electrodes 12 (source electrodes) of the first semiconductor elements 10A is detected from the first control terminal 46B.
  • the first control terminals 46C and 46D are terminals that are electrically connected to the diode function unit D1.
  • the first control terminal 46C is electrically connected to the third obverse-surface electrode 13 of the first semiconductor element 10A having the diode function unit D1
  • the first control terminal 46D is electrically connected to the fourth obverse-surface electrode 14 of the first semiconductor element 10A having the diode function unit D1.
  • the first control terminal 46E is a terminal (drain sense terminal) used to detect a drain signal for the first semiconductor elements 10A. Voltage (corresponding to a drain current) applied to the reverse-surface electrodes 15 (drain electrodes) of the first semiconductor elements 10A is detected from the first control terminal 46E.
  • the second control terminals 47A to 47D are arranged at intervals in the y direction. As shown in FIGS. 5 and 18 , for example, the second control terminals 47A to 47D are supported by the second conductive portion 2B via the control terminal support 5 (a second supporting portion 5B described below) . As shown in FIGS. 5 and 8 , the second control terminals 47A to 47D are located between the second semiconductor elements 10B and the two output terminals 44 in the x direction.
  • Each of the control terminals 45 includes a holder 451 and a metal pin 452.
  • the holder 451 is made of a conductive material. As shown in FIG. 15 , the holder 451 is bonded to the control terminal support 5 (a first metal layer 52 described below) via a conductive bonding member 459.
  • the holder 451 includes a tubular portion, an upper-end flange portion, and a lower-end flange portion. The upper-end flange portion is joined to the top of the tubular portion, and the lower-end flange portion is joined to the bottom of the tubular portion.
  • the metal pin 452 is inserted through at least the upper-end flange portion and the tubular portion of the holder 451. The upper surface of the upper-end flange portion is exposed from the sealing resin 8 (a second protruding portion 852 described below), and is covered with the resin member 87.
  • the metal pin 452 is a rod-like member extending in the z direction.
  • the metal pin 452 is supported by being pressed into the holder 451.
  • the metal pin 452 is electrically connected to the control terminal support 5 (a first metal layer 52 described below) at least via the holder 451.
  • the control terminal support 5 a first metal layer 52 described below
  • the metal pin 452 is electrically connected to the control terminal support 5 via the conductive bonding member 459.
  • the control terminal support 5 supports the control terminals 45.
  • the control terminal support 5 is provided between the obverse surface 201 (conductive substrate 2) and the control terminals 45.
  • the control terminal support 5 includes a first supporting portion 5A and a second supporting portion 5B.
  • the first supporting portion 5A is arranged on the first conductive portion 2A of the conductive substrate 2, and supports the first control terminals 46A to 46E among the control terminals 45.
  • the first supporting portion 5A is bonded to the first conductive portion 2A via a bonding member 59.
  • the bonding member 59 may be conductive or insulative.
  • the bonding member 59 may be solder.
  • the second supporting portion 5B is arranged on the second conductive portion 2B of the conductive substrate 2, and supports the second control terminals 47A to 47D among the control terminals 45.
  • the second supporting portion 5B is bonded to the second conductive portion 2B via the bonding member 59.
  • the control terminal support 5 (the first supporting portion 5A and the second supporting portion 5B) may be a DBC substrate, for example.
  • Each of the supporting portions of the control terminal support 5 includes an insulating layer 51, a first metal layer 52, and a second metal layer 53 that are stacked on each other.
  • the insulating layer 51 is made of a ceramic, for example.
  • the insulating layer 51 has a rectangular shape in plan view, for example.
  • the first metal layer 52 is formed on the upper surface of the insulating layer 51.
  • the control terminals 45 are erected on the first metal layer 52.
  • the first metal layer 52 is made of Cu or a Cu alloy, for example.
  • the first metal layer 52 includes a first portion 521, a second portion 522, a third portion 523, a fourth portion 524, and a fifth portion 525.
  • the first portion 521, the second portion 522, the third portion 523, the fourth portion 524, and the fifth portion 525 are spaced apart and insulated from each other.
  • a plurality of wires 731 are bonded to the first portion 521, so that the first portion 521 is electrically connected to the first obverse-surface electrodes 11 (gate electrodes) of the semiconductor elements 10 via the wires 731.
  • the first control terminal 46A is bonded to the first portion 521 of the first supporting portion 5A
  • the second control terminal 47A is bonded to the first portion 521 of the second supporting portion 5B.
  • a plurality of wires 732 are bonded to the second portion 522, so that the second portion 522 is electrically connected to the second obverse-surface electrodes 12 (source electrodes) of the semiconductor elements 10 via the wires 732.
  • the first control terminal 46B is bonded to the second portion 522 of the first supporting portion 5A
  • the second control terminal 47B is bonded to the second portion 522 of the second supporting portion 5B.
  • a wire 733 is bonded to the third portion 523, so that the third portion 523 is electrically connected to the third obverse-surface electrode 13 of the semiconductor element 10 having the diode function unit D1 via the wire 733.
  • the first control terminal 46C is bonded to the third portion 523 of the first supporting portion 5A
  • the second control terminal 47C is bonded to the third portion 523 of the second supporting portion 5B.
  • a wire 734 is bonded to the fourth portion 524, so that the fourth portion 524 is electrically connected to the fourth obverse-surface electrode 14 of the semiconductor element 10 having the diode function unit D1 via the wire 734.
  • the first control terminal 46D is bonded to the fourth portion 524 of the first supporting portion 5A
  • the second control terminal 47D is bonded to the fourth portion 524 of the second supporting portion 5B.
  • a wire 735 is bonded to the fifth portion 525 of the first supporting portion 5A, and the fifth portion 525 is electrically connected to the first conductive portion 2A.
  • the fifth portion 525 of the second supporting portion 5B is not electrically connected to other components.
  • the first control terminal 46E is bonded to the fifth portion 525 of the first supporting portion 5A.
  • the second metal layer 53 is formed on the lower surface of the insulating layer 51.
  • the second metal layer 53 of the first supporting portion 5A is bonded to the first conductive portion 2A via the bonding member 59.
  • the second metal layer 53 of the second supporting portion 5B is bonded to the second conductive portion 2B via the bonding member 59.
  • the conducting member 6 is separated from the obverse surface 201 (conductive substrate 2) in the z2 direction, and overlaps with the obverse surface 201 in plan view.
  • the conducting member 6 is made of a metal plate-like member.
  • the metal is Cu or a Cu alloy, for example.
  • the conducting member 6 is a metal plate-like member that is bent.
  • the conducting member 6 may be formed with a metal foil member.
  • the conducting member 6 includes a plurality of first conducting members 61 and a second conducting member 62.
  • the main circuit current includes a first main circuit current and a second main circuit current.
  • the first main circuit current flows through a path between the input terminal 41 and the output terminals 44.
  • the second main circuit current flows through a path between the output terminals 44 and the input terminals 42, 43.
  • the first conducting members 61 are connected to the second obverse-surface electrodes 12 (source electrodes) of the first semiconductor elements 10A and the second conductive portion 2B, so that the second obverse-surface electrodes 12 of the first semiconductor elements 10A are electrically connected to the second conductive portion 2B.
  • the first conducting members 61 and the second obverse-surface electrodes 12 (see FIG. 8 ) of the first semiconductor elements 10A, as well as the first conducting members 61 and the second conductive portion 2B, are bonded to each other via the conductive bonding member 69.
  • the conductive bonding member 69 may be made of solder, a metal paste material, or a sintered metal.
  • each of the first conducting members 61 has a band shape extending along the x direction in plan view.
  • each of the first conducting members 61 has a rectangular portion connecting the first semiconductor element 10A and the second conductive portion 2B, and the rectangular portion is formed with an opening 61h, as shown in FIG. 6 , for example.
  • the opening 61h may be a through-hole that penetrates through in the z direction, and is preferably formed in the center of the rectangular portion in plan view.
  • the opening 61h is formed so that when a flowable resin material is injected to form a sealing resin, the resin material can easily flow between the upper side (in the z2 direction) and the lower side (in the z1 direction) near the first conducting member 61.
  • the opening 61h may have a perfectly circular shape, or may have another shape such as an oval shape or a rectangular shape.
  • Each of the first conducting members 61 is not limited to having the configuration described above, and may not be formed with an opening 61h.
  • the number of first conducting members 61 is three so as to correspond to the number of first semiconductor elements 10A.
  • a single first conducting member 61 common to the first semiconductor elements 10A may be used, without depending on the number of first semiconductor elements 10A.
  • the second conducting member 62 electrically connects the second obverse-surface electrodes 12 of the second semiconductor elements 10B to the input terminals 42 and 43.
  • the second conducting member 62 may have a maximum dimension of 25 mm to 40 mm (preferably about 32 mm) in the x direction, and a maximum dimension of 30 mm to 45 mm (preferably about 38 mm) in the y direction.
  • the second conducting member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624.
  • the first wiring portion 621 is connected to the input terminal 42.
  • the first wiring portion 621 and the input terminal 42 are bonded with the conductive bonding member 69.
  • the first wiring portion 621 has a band shape extending in the x direction in plan view.
  • the second wiring portion 622 is connected to the input terminal 43.
  • the second wiring portion 622 and the input terminal 43 are bonded with the conductive bonding member 69.
  • the second wiring portion 622 has a band shape extending in the x direction in plan view.
  • the first wiring portion 621 and the second wiring portion 622 are spaced apart from each other in the y direction and arranged substantially in parallel to each other.
  • the second wiring portion 622 is offset in the y1 direction relative to the first wiring portion 621.
  • the third wiring portion 623 is joined to the first wiring portion 621 and the second wiring portion 622.
  • the third wiring portion 623 has a band shape extending in the y direction in plan view. As is evident from FIG. 6 , the third wiring portion 623 overlaps with the second semiconductor elements 10B in plan view. As shown in FIG. 17 , the third wiring portion 623 is connected to the second semiconductor elements 10B.
  • the third wiring portion 623 has a plurality of recessed areas 623a. As shown in FIG. 17 , the recessed areas 623a are recessed in the z1 direction relative to the other areas of the third wiring portion 623.
  • the recessed areas 623a of the third wiring portion 623 are bonded to the second semiconductor elements 10B.
  • the recessed areas 623a of the third wiring portion 623 and the second obverse-surface electrodes 12 (see FIG. 8 ) of the second semiconductor elements 10B are bonded with the conductive bonding member 69.
  • the fourth wiring portion 624 is joined to the first wiring portion 621 and the second wiring portion 622.
  • the fourth wiring portion 624 is also connected to the third wiring portion 623.
  • the fourth wiring portion 624 is offset in the x2 direction relative to the third wiring portion 623. As is evident from FIG. 6 , the fourth wiring portion 624 overlaps with the first semiconductor elements 10A in plan view.
  • the fourth wiring portion 624 includes a first band portion 625 and a plurality of second band portions 626.
  • the first band portion 625 is a part of the fourth wiring portion 624 that has a band shape in plan view, and is spaced apart from the third wiring portion 623 in the x direction.
  • the first band portion 625 is joined to the first wiring portion 621 and the second wiring portion 622.
  • the first band portion 625 overlaps with the first semiconductor elements 10A in plan view.
  • the first band portion 625 has a plurality of protruding areas 625a. As shown in FIG. 16 , the protruding areas 625a protrude in the z2 direction relative to the other areas of the first band portion 625. As shown in FIG. 6 , the protruding areas 625a overlap with the first semiconductor elements 10A in plan view.
  • first band portion 625 Since the first band portion 625 has the protruding areas 625a, areas for bonding the first conducting members 61 are provided on the first semiconductor elements 10A, as shown in FIG. 16 . This prevents the first band portion 625 from being in contact with the first conducting members 61.
  • Each of the second band portions 626 is connected to the first band portion 625 and the third wiring portion 623.
  • Each of the second band portions 626 has a band shape extending in the x direction in plan view.
  • the second band portions 626 are spaced apart from each other in the y direction and arranged substantially in parallel to each other.
  • one end of each band portion 626 is connected to a part of the first band portion 625, which is located between two first semiconductor elements 10A adjacent in the y direction
  • the other end of each band portion 626 is connected to a part of the third wiring portion 623, which is located between two second semiconductor elements 10B adjacent in the y direction.
  • the first band portion 625 has a first edge 627 and a second edge 628. As shown in FIG. 7 , the first edge 627 is offset in the x1 direction relative to the first side 191 in plan view, and extends at least from the third side 193 to the fourth side 194 in the y direction. As such, two corners 171 and 172 of each first semiconductor element 10A in the x2 direction do not overlap with the second conducting member 62 in plan view. The two corners are the corner 171 formed by the first side 191 and the third side 193, and the corner 172 formed by the first side 191 and the fourth side 194.
  • each of the first semiconductor elements 10A parts of the two sides forming each of the corners 171 and 172 are visible in plan view (specifically, when viewed as shown in FIG. 7 ; the same applies hereinafter).
  • the second edge 628 is offset in the x2 direction relative to the second side 192 in plan view, and extends at least from the third side 193 to the fourth side 194 in the y direction.
  • two corners 173 and 174 of each first semiconductor element 10A in the x1 direction do not overlap with the second conducting member 62 in plan view.
  • the two corners are the corner 173 formed by the second side 192 and the third side 193, and the corner 174 formed by the second side 192 and the fourth side 194. Accordingly, in each of the first semiconductor elements 10A, parts of the two sides forming each of the corners 173 and 174 are visible in plan view.
  • each of the visible portions of the two sides forming each of the corners 171, 172, 173, and 174 it is sufficient for each of the visible portions of the two sides forming each of the corners 171, 172, 173, and 174 to have a length greater than 0 ⁇ m and no greater than 200 ⁇ m in plan view. Furthermore, it is preferable that in plan view, the length of each of the visible portions of the two sides forming each of the corners 171, 172, 173, and 174 be no less than 5 ⁇ m and no greater than 150 ⁇ m. When the length of each of the visible portions of the two sides forming each of the corners 171, 172, 173, and 174 is no less than 2 ⁇ m, it is possible to detect the corners of each of the first semiconductor elements 10A.
  • each of the visible portions of the two sides When the length of each of the visible portions of the two sides is no less than 5 ⁇ m, it is possible to reliably detect the corners of each of the first semiconductor elements 10A.
  • the length of each of the visible portions of the two sides is greater than 200 ⁇ m, the bonding areas between the first conducting members 61 and the first semiconductor elements 10A become smaller than necessary, which is not desirable. It is preferable that the upper limit of the length of each of the visible portions of the two sides be no greater than 150 ⁇ m, because the bonding area between the first conducting members 61 and the first semiconductor elements 10A is prevented from being too small.
  • the conducting member 6 (first conducting members 61 and the second conducting member 62) has first portions 601.
  • the first portions 601 are areas that overlap with the semiconductor elements 10 (the first semiconductor elements 10A and the second semiconductor elements 10B) in plan view.
  • parts of the fourth wiring portion 624 (areas overlapping with the first semiconductor elements 10A in plan view) and parts of the third wiring portion 623 (areas overlapping with the second semiconductor elements 10B in plan view) constitute the first portions 601.
  • the obverse-surface electrodes 11, 13, 14, and 16 of one of the first semiconductor elements 10A are aligned along the y direction at the end of the first semiconductor element 10A in the x2 direction.
  • the first conducting members 61 and the second conducting member 62 do not overlap with the obverse-surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A or with the corners 171 and 172 thereof in the x2 direction.
  • the first conducting members 61 and the second conducting member 62 do not overlap with at least one of the corners 173 and 174 of the first semiconductor element 10A in the x1 direction (opposite from the side where the obverse-surface electrodes are arranged).
  • at least three corners among the four corners 171, 172, 173, and 174 of the semiconductor element 10A are visible in plan view. This makes it possible to inspect whether the first semiconductor elements 10A are correctly mounted by automatic visual inspection when the first semiconductor elements 10A, the conducting members 61, and the second conducting member 62 are mounted on the conductive substrate 2.
  • the four corners 171, 172, 173, and 174 of each of the first semiconductor elements 10A may all be visible.
  • the obverse-surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A are examples of “obverse-surface electrodes on one side”.
  • each of the second semiconductor elements 10B has a rectangular shape in plan view, similarly to the first semiconductor elements 10A, and has four corners 181, 182, 183, and 184 corresponding to the four corners 171, 172, 173, and 174 of each first semiconductor element 10A.
  • the above-described relationship in plan view between the four corners 171, 172, 173, and 174 of each first semiconductor element 10A and the first and second conducting members 61, 62 also holds for the relationship in plan view between the four corners 181, 182, 183, and 184 of each second semiconductor element 10B and the second conducting member 62.
  • the second conducting member 62 includes first portions 62A and second portions 62B.
  • the first portions 62A overlap with the obverse surface 201 of the conductive substrate 2 (the obverse surface 201 of either the first conductive portion 2A or the second conductive portion 2B) in plan view, and do not overlap with any of the semiconductor elements 10 in plan view.
  • the second portions 62B overlap with the obverse surface 201 in plan view, and overlap with the semiconductor elements 10 in plan view.
  • the first portions 62A are shown with hatching that diagonally rising to the right, and the second portions 62B are shown with hatching that diagonally falling to the right.
  • the first portions 62A have openings 63. As shown in FIGS.
  • the openings 63 are partially cut away portions in plan view.
  • the openings 63 are provided at positions that overlap with the obverse surface 201 of the first conductive portion 2A (conductive substrate 2) in plan view, and that do not overlap with the semiconductor elements 10 in plan view.
  • the openings 63 are through-holes that penetrate through in the z direction, for example.
  • the openings 63 include one formed in the first wiring portion 621 and one formed in the second wiring portion 622.
  • the openings 63 are provided in the vicinity of at least two of the four corners of the conductive substrate 2 in plan view.
  • one of the openings 63 is provided at an area of the first wiring portion 621 in the x2 direction, and the other at an area of the second wiring portion 622 in the x2 direction.
  • the planar shape of each opening 63 is not limited.
  • the openings 63 may be holes as described in the present embodiment or notches unlike the present embodiment.
  • the openings 63 may be formed by electroforming, for example.
  • the second conducting member 62 has openings 63 in areas not electrodeposited with a metal, instead of the openings 63 formed by removing portions of the second conducting member 62.
  • the second conducting member 62 is formed with openings 625h in rectangular portions that overlap with the first semiconductor elements 10A in plan view. In the present embodiment, it is preferable that the openings 625h be formed to overlap with the centers of the first semiconductor elements 10A in plan view.
  • the openings 625h are through-holes (see FIG. 6 ) formed in the protruding areas 625a of the first band portion 625 (fourth wiring portion 624), for example.
  • the openings 625h are used, when the first conducting members 61 and the first semiconductor elements 10A are bonded, to optically check the bonding state from above.
  • the second conducting member 62 is formed with openings 623h in rectangular portions that overlap with the second semiconductor elements 10B in plan view. In the present embodiment, it is preferable that the openings 623h be formed to overlap with the centers of the second semiconductor elements 10B in plan view.
  • the openings 623h are through-holes formed in the recessed areas 623a of the third wiring portion 623, for example.
  • the openings 623h are used when the second conducting member 62 is positioned relative to the conductive substrate 2.
  • each of the two types of openings 623h and 625h may have a perfectly circular shape, or may have another shape such as an oval shape or a rectangular shape.
  • the second conducting member 62 is not limited to having the configuration described above, and may not include the fourth wiring portion 624. However, the second conducting member 62 is preferably provided with the fourth wiring portion 624 in order to reduce the inductance value due to the current flowing through the second conducting member 62.
  • the first conductive bonding member 71 is provided between the conductive substrate 2 and the supporting substrate 3 to electrically bond the conductive substrate 2 and the supporting substrate 3.
  • the first conductive bonding member 71 includes a conductive bonding portion that electrically bonds the first conductive portion 2A to the first portion 32A, and a conductive bonding portion that electrically bonds the second conductive portion 2B to the second portion 32B.
  • the first conductive bonding member 71 includes a first base layer 711, a first layer 712, and a second layer 713 that are stacked on each other.
  • the creepage distance between the first metal layer 32 and the second metal layer 33 becomes undesirably small.
  • the side surface of the first metal layer 32 is positioned more outward than a side surface of the base member 21 in the conductive substrate 2.
  • the first base layer 711 is made of a metal, such as aluminum (Al) or an Al alloy.
  • the first base layer 711 is made of a sheet material.
  • the Young’s modulus of Al, which is the material of the first base layer 711, is 70.3 GPa.
  • the first layer 712 is formed on the upper surface of the first base layer 711.
  • the first layer 712 is provided between the first base layer 711 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B).
  • the first layer 712 is a Ag plating layer, for example.
  • the first layer 712 is bonded to the respective reverse-surface bonding layers 23 of the first conductive portion 2A and the second conductive portion 2B by the solid-phase diffusion of metal, for example. In other words, the first layer 712 and the reverse-surface bonding layers 23 of the first conductive portion 2A and the second conductive portion 2B are bonded by solid-phase diffusion.
  • the first layer 712 and the reverse-surface bonding layers 23 are bonded in direct contact with each other at the bonding interface.
  • “A and B are bonded by solid-phase diffusion” means that as a result of solid-phase diffusion bonding, A and B are fixed to each other in direct contact at the bonding interface, where A and B constitute a solid-phase diffusion layer.
  • solid-phase diffusion bonding is performed under an ideal condition, the bonding interface may not exist clearly due to the diffusion of metal elements.
  • an inclusion such as an oxidation film is formed on the surface layers of A and B, or when there is a gap between A and B, the inclusion or the gap may exist at the bonding interface.
  • the second layer 713 is formed on the lower surface of the first base layer 711.
  • the second layer 713 is provided between the first base layer 711 and the supporting substrate 3 (each of the first portion 32A and the second portion 32B).
  • the second layer 713 is a Ag plating layer, for example.
  • the second layer 713 is bonded to the first bonding layer 321 formed on each of the first portion 32A and the second portion 32B by solid-phase diffusion of metal. In other words, the second layer 713 and the first bonding layer 321 are bonded by solid-phase diffusion in direct contact with each other at the bonding interface.
  • the Young’s modulus of silver (Ag) which is the material of the first layer 712 and the second layer 713, is 82.7 GPa.
  • the Young’s modulus of the first base layer 711 is smaller than the Young’s modulus of each of the first layer 712 and the second layer 713.
  • the thickness (dimension in the z direction) of the first base layer 711 is greater than the thickness of each of the first layer 712 and the second layer 713.
  • an end surface of the first base layer 711 which is made of Al or an Al alloy, is not plated with Ag, so that the end surface of the first base layer 711 is exposed.
  • the end surface of the first base layer 711 may be plated with Ag.
  • the second conductive bonding member 72 is provided between the conductive substrate 2 and the semiconductor elements 10 to electrically bond the conductive substrate 2 and the semiconductor elements 10.
  • the second conductive bonding member 72 includes a conductive bonding portion that electrically bonds the first semiconductor elements 10A to the first conductive portion 2A, and a conductive bonding portion that electrically bonds the second semiconductor elements 10B to the second conductive portion 2B.
  • the second conductive bonding member 72 includes a second base layer 721, a third layer 722, and a fourth layer 723 that are stacked on each other.
  • the second base layer 721 is made of a metal, such as Al or an Al alloy.
  • the second base layer 721 is made of a sheet material.
  • the third layer 722 is formed on the upper surface of the second base layer 721.
  • the third layer 722 is provided between the second base layer 721 and the semiconductor elements 10.
  • the third layer 722 is a Ag plating layer, for example.
  • the third layer 722 is bonded to the reverse-surface electrodes 15 of the semiconductor elements 10 by the solid-phase diffusion of metal, for example. In other words, the third layer 722 and the reverse-surface electrodes 15 are bonded by solid-phase diffusion in direct contact with each other at the bonding interface.
  • the fourth layer 723 is formed on the lower surface of the second base layer 721.
  • the fourth layer 723 is provided between the second base layer 721 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B) .
  • the fourth layer 723 is a Ag plating layer, for example.
  • the fourth layer 723 is bonded to the respective obverse-surface bonding layers 22 of the first conductive portion 2A and the second conductive portion 2B by the solid-phase diffusion of metal, for example. In other words, the fourth layer 723 and the obverse-surface bonding layers 22 are bonded by solid-phase diffusion in direct contact with each other at the bonding interface.
  • the Young’s modulus of the second base layer 721 is smaller than the Young’s modulus of each of the third layer 722 and the fourth layer 723.
  • the thickness (dimension in the z direction) of the second base layer 721 is greater than the thickness of each of the third layer 722 and the fourth layer 723.
  • an end surface of the second base layer 721 which is made of Al or an Al alloy, is not plated with Ag, so that the end surface of the second base layer 721 is exposed.
  • the end surface of the second base layer 721 may be plated with Ag.
  • Each of the wires 731 to 735 electrically connects two members that are separated from each other.
  • the wires 731 to 735 are bonding wires, for example.
  • the material of each of the wires 731 to 735 contains one of gold (Au), Al, or Cu, for example.
  • each of the wires 731 is bonded to and electrically connects the first obverse-surface electrode 11 (gate electrode) of a semiconductor element 10 and a first portion 521 (first metal layer 52) of the control terminal support 5.
  • the plurality of wires 731 include a plurality of first wires 731a and a plurality of second wires 731b. Each of the first wires 731a is connected to the first obverse-surface electrode 11 (gate electrode) of one of the first semiconductor elements 10A and the first portion 521 (first metal layer 52) of the first supporting portion 5A.
  • the first control terminal 46A is electrically connected to the first obverse-surface electrodes 11 (gate electrodes) of the first semiconductor elements 10A via the first wires 731a.
  • Each of the second wires 731b is connected to the first obverse-surface electrode 11 (gate electrode) of one of the second semiconductor elements 10B and the first portion 521 (first metal layer 52) of the second supporting portion 5B.
  • the second control terminal 47A is electrically connected to the first obverse-surface electrodes 11 (gate electrodes) of the second semiconductor elements 10B via the second wires 731b.
  • each of the wires 732 is bonded to and electrically connects the second obverse-surface electrode 12 (source electrode) of a semiconductor element 10 and a second portion 522 (first metal layer 52) of the control terminal support 5.
  • the wire 732 is bonded to the fifth obverse-surface electrode 16 (source sense electrode) instead of the second obverse-surface electrode 12 (source electrode).
  • each of the wires 733 is bonded to and electrically connects the third obverse-surface electrode 13 of one of the semiconductor elements 10 having the diode function units D1 and a third portion 523 (first metal layer 52) of the control terminal support 5.
  • each of the wires 734 is bonded to and electrically connects the fourth obverse-surface electrode 14 of one of the semiconductor elements 10 having the diode function units D1 and a fourth portion 524 (first metal layer 52) of the control terminal support 5.
  • the wire 735 is bonded to and electrically connects the obverse surface 201 of the first conductive portion 2A (conductive substrate 2) and the fifth portion 525 (first metal layer 52) of the first supporting portion 5A (control terminal support 5).
  • the sealing resin 8 covers the semiconductor elements 10, the conductive substrate 2, the supporting substrate 3 (except the bottom surface 302), parts of the input terminals 41 to 43, parts of the output terminals 44, parts of the control terminals 45, the control terminal support 5, the conducting member 6, and the wires 731 to 735.
  • the sealing resin 8 is made of a black epoxy resin, for example.
  • the sealing resin 8 may be formed by molding described below.
  • the sealing resin 8 may have a dimension of about 35 mm to 60 mm in the x direction, a dimension of about 35 mm to 50 mm in the y direction, and a dimension of about 4 mm to 15 mm in the z direction. Each of these dimensions is the size of the largest portion along one of the directions.
  • the sealing resin 8 has a resin obverse surface 81, a resin reverse surface 82, and a plurality of resin side surfaces 831 to 834.
  • the resin obverse surface 81 and the resin reverse surface 82 are spaced apart from each other in the z direction.
  • the resin obverse surface 81 faces in the z2 direction
  • the resin reverse surface 82 faces in the z1 direction.
  • the control terminals 45 protrude from the resin obverse surface 81.
  • the resin reverse surface 82 has a frame shape surrounding the bottom surface 302 of the supporting substrate 3 (lower surface of the second metal layer 33) in plan view.
  • the bottom surface 302 of the supporting substrate 3 is exposed from the resin reverse surface 82, and is flush with the resin reverse surface 82, for example.
  • the resin side surfaces 831 to 834 are joined to the resin obverse surface 81 and the resin reverse surface 82, and are flanked by these surfaces in the z direction. As shown in FIG. 4 , the resin side surface 831 and the resin side surface 832 are spaced apart from each other in the x direction.
  • the resin side surface 831 faces in the x1 direction, and the resin side surface 832 faces in the x2 direction.
  • the two output terminals 44 protrude from the resin side surface 831, and the three input terminals 41 to 43 protrude from the resin side surface 832.
  • the resin side surface 833 and the resin side surface 834 are spaced apart from each other in the y direction.
  • the resin side surface 833 faces in the y1 direction
  • the resin side surface 834 faces in the y2 direction.
  • the resin side surface 832 is formed with a plurality of recessed portions 832a.
  • the recessed portions 832a are recessed in the x direction in plan view.
  • the recessed portions 832a include one formed between the input terminal 41 and the input terminal 42, and one formed between the input terminal 41 and the input terminal 43 in plan view.
  • the recessed portions 832a are provided to increase the creepage distance between the input terminal 41 and the input terminal 42 along the resin side surface 832, and to increase the creepage distance between the input terminal 41 and the input terminal 43 along the resin side surface 832.
  • the sealing resin 8 has a plurality of first protrusions 851, a plurality of second protrusions 852, and resin voids 86.
  • the first protrusions 851 protrude from the resin obverse surface 81 in the z direction.
  • the first protrusions 851 are arranged near the four corners of the sealing resin 8 in plan view.
  • the tip end (end in the z2 direction) of each of the first protrusions 851 is formed with a first protruding end surface 851a.
  • the first protruding end surfaces 851a of the first protrusions 851 are substantially parallel to the resin obverse surface 81 and positioned on the same plane (x-y plane) as the resin obverse surface 81.
  • Each of the first protrusions 851 has a bottomed hollow truncated cone shape, for example.
  • the first protrusions 851 are used for an apparatus that uses a power supply generated by the semiconductor module A1, and function as spacers when the semiconductor module A1 is mounted on, for example, a control circuit board of the apparatus.
  • Each of the first protrusions 851 has a recessed portion 851b and an inner wall surface 851c formed in the recessed portion 851b. It suffices for the first protrusions 851 to have a pillar shape, preferably a columnar shape. It is preferable that each of the recessed portions 851b have a columnar shape, and each of the inner wall surfaces 851c have a single perfect circular shape in plan view.
  • the semiconductor module A1 may be mechanically fixed to a control circuit board or the like by, for example, a screwing method.
  • the threads of female screws may be formed in the inner wall surfaces 851c of the recessed portions 851b in the first protrusions 851. It is also possible to embed an insert nut in the recessed portion 851b of each of the first protrusions 851.
  • the second protrusions 852 protrude from the resin obverse surface 81 in the z direction.
  • the second protrusions 852 overlap with the control terminals 45 in plan view.
  • the metal pins 452 of the control terminals 45 protrude from the second protrusions 852.
  • a part of each holder 451 (upper surface of each upper-end flange portion) is exposed from the upper end surface of each second protrusion 852.
  • Each of the second protrusions 852 has a truncated cone shape.
  • the resin members 87 are provided on the second protrusions 852.
  • each of the resin voids 86 passes from the resin obverse surface 81 to the recessed portion 201a formed in the obverse surface 201 of the conductive substrate 2 in the z direction.
  • Each of the resin voids 86 is formed to be tapered such that the cross-sectional area thereof decreases along the z direction from the resin obverse surface 81 to the recessed portion 201a.
  • the resin voids 86 are portions that are formed in a molding process described below, and in which the sealing resin 8 is not formed during the molding process.
  • the resin members 87 are provided on the second protrusions 852 of the sealing resin 8.
  • the resin members 87 cover parts of the control terminals 45, i.e., parts (upper surfaces of the upper-end flange portions) of the holders 451 that are exposed from the sealing resin 8, and parts of the metal pins 452.
  • the resin members 87 are made of epoxy resin, as with the sealing resin 8, but may be made of a material different from the material of the sealing resin 8.
  • the resin-filling portions 88 are provided for the resin voids 86 to fill the resin voids 86.
  • the resin-filling portions 88 are made of epoxy resin, as with the sealing resin 8, but may be made of a material different from the material of the sealing resin 8.
  • FIG. 21 is a plan view illustrating a step of the method for manufacturing the semiconductor module A1.
  • FIG. 22 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor module A1.
  • FIG. 23 is a plan view illustrating a step of the method for manufacturing the semiconductor module A1.
  • FIG. 24 is a cut end view illustrating a step of the method for manufacturing the semiconductor module A1.
  • FIG. 24 corresponds to the cross section shown in FIG. 13 .
  • FIGS. 25 and 28 is a partially enlarged cross-sectional view illustrating a step of the method for manufacturing the semiconductor module A1, and corresponds to an enlarged view of a part of the cross-section in FIG.
  • FIGS. 26 , 27 , and 29 is a partially enlarged cross-sectional view illustrating a step of the method for manufacturing the semiconductor module A1, and corresponds to an enlarged view of a part of the cross-section in FIG. 14 .
  • a plurality of semiconductor elements 10, a conductive substrate 2, a supporting substrate 3, a plurality of input terminals 41 to 43, and a plurality of output terminals 44 are prepared.
  • the configurations of the semiconductor elements 10, the conductive substrate 2, and the supporting substrate 3 are as described above.
  • the semiconductor elements 10, the conductive substrate 2, and the supporting substrate 3 are separately prepared and not bonded to each other.
  • the conductive substrate 2, the input terminals 41 to 43, and the output terminals 44 are connected to each other, and may be made of the same lead frame.
  • no recessed portion 201a is formed in the obverse surface 201 of the conductive substrate 2.
  • the conductive substrate 2 is placed on the supporting substrate 3 via a first conductive bonding member 71, and the semiconductor elements 10 are placed on the conductive substrate 2 via a second conductive bonding member 72. Then, heat is applied while the lower surface of the supporting substrate 3 and the upper surfaces of the semiconductor elements 10 are held (see the thick arrows in FIG. 22 ). As a result, the semiconductor elements 10 and the conductive substrate 2 are bonded to each other by solid-phase diffusion, and the conductive substrate 2 and the supporting substrate 3 are bonded to each other by solid-phase diffusion.
  • the following elements are collectively bonded to each other by solid-phase diffusion: a first bonding layer 321 (supporting substrate 3) on a first metal layer 32 and a second layer 713 (first conductive bonding member 71); a first layer 712 (first conductive bonding member 71) and a reverse-surface bonding layer 23 (conductive substrate 2); a fourth layer 723 (second conductive bonding member 72) and an obverse-surface bonding layer 22 (conductive substrate 2); and a third layer 722 (second conductive bonding member 72) and reverse-surface electrodes 15 of the semiconductor elements 10.
  • the heat temperature during bonding may be in the range of 200° C. to 350° C.
  • the pressure applied (force for the holding) during the bonding may be in the range of 1 MPa to 100 MPa inclusive.
  • the solid-phase diffusion bonding is assumed to be performed in the atmosphere, but it may be performed in vacuum instead.
  • the conductive substrate 2 is bonded to the supporting substrate 3 via the first conductive bonding member 71, and the semiconductor elements 10 are bonded to the conductive substrate 2 via the second conductive bonding member 72.
  • the bonding between the conductive substrate 2 and the supporting substrate 3, and the bonding between the conductive substrate 2 and the semiconductor elements 10 may be performed separately rather than collectively. However, it is more preferable to perform the bonding collectively in order to improve manufacturing efficiency.
  • individual second conductive bonding members 72 corresponding to the respective semiconductor elements 10 may be provided as shown in FIGS. 16 and 17 .
  • bonding of a control terminal support 5, bonding of a plurality of holders 451 of a plurality of control terminals 45, bonding of a plurality of wires 731 to 735, bonding of a plurality of first conducting members 61, and bonding of a second conducting member 62 are performed.
  • the bonding of these elements may be performed in any suitable order.
  • a sealing resin 8 is formed.
  • the sealing resin 8 is formed by molding, for example.
  • a mold 91 for a molding process is provided with pressing pins 911 as pressing members.
  • the tip ends of the pressing pins 911 are in contact with the obverse surface 201 of the conductive substrate 2.
  • recessed portions 201a are formed in the obverse surface 201 by the pressing force of the pressing pins 911 to the obverse surface 201.
  • the degree of recession (depth) of the recessed portions 201a changes depending on the strength of the pressing force or the like.
  • the pressing pins 911 in contact with the obverse surface 201 of a first conductive portion 2A are inserted through openings 63 of the second conducting member 62.
  • the sealing resin 8 thus formed has first protrusions 851, second protrusions 852, and resin voids 86, which are all described above, as shown in FIGS. 25 and 26 .
  • a resin void edge 861 of each of the resin voids 86, which is in contact with the obverse surface 201, and a recess edge 201b of each of the recessed portions 201a, which is in contact with the obverse surface 201 coincide with each other.
  • FIG. 25 a resin void edge 861 of each of the resin voids 86, which is in contact with the obverse surface 201, and a recess edge 201b of each of the recessed portions 201a, which is in contact with the obverse surface 201, coincide with each other.
  • FIG. 25 a resin void edge 861 of each of the resin voids 86, which is in contact with the obverse surface 201, and a recess edge 201b of each of the recessed portions
  • each of the holders 451 is exposed from a second protrusion 852 and flush with the upper surface of the second protrusion 852.
  • the resin voids 86 are formed by the pressing pins 911 as a result of the flowable resin material not being filled.
  • the pressing pins 911 may be movable pins.
  • the pressing pins 911 are preferably provided in holes formed in the mold 91 and supported elastically.
  • Each of the pressing members does not necessarily have a pin shape, and may have a block shape instead.
  • the mold 91 is opened, and a molded body is taken out, where the molded body contains the lead frame including the conductive substrate 2, and the sealing resin 8.
  • the sealing resin 8 is separated from the resin that has solidified at the resin flow channel and the resin inlet.
  • one or more resin separation marks are formed at either a first position or a second position on a resin side surface 831 of the sealing resin 8 in the x1 direction.
  • the first position may correspond to at least one of two positions each close to a respective end of the resin side surface 831 in the y direction, or at least one of the edges of the respective ends.
  • the separation mark In the case where the separation mark is formed at one of the edges of the respective ends, it may be formed at a surface formed along the edge (C chamfered portion in plan view) . Such an inclined surface may be a part of the resin side surface 831 of the sealing resin 8 in the x1 direction.
  • the second position is located between the two output terminals 44 at the resin side surface 831 shown in FIG. 1 .
  • the resin separation mark corresponds to the position of a resin inlet of the mold 91, and is formed by separating the sealing resin 8 from the resin that has solidified at the resin inlet. In order to prevent unevenness of the resin flow, it is preferable that the resin be injected from the central position of the mold in the y direction. In this case, a resin separation mark is formed between the two output terminals 44.
  • metal pins 452 of the control terminals 45 are pressed into the respective holders 451.
  • the metal pins 452 each of which has a cross-sectional dimension slightly larger than the inner diameter of a tubular portion (see FIG. 26 ) of each of the holders 451, are inserted with pressure.
  • the holders 451 and the metal pins 452 are mechanically fixed and electrically connected to each other.
  • the holders 451 and the metal pins 452 may be electrically connected with solder, for example.
  • resin members 87 and resin-filling portions 88 are formed as shown in FIGS. 28 and 29 .
  • the resin members 87 and the resin-filling portions 88 may be formed by potting.
  • the lead frame is cut appropriately to separate the input terminals 41 to 43 and the output terminals 44.
  • the area near the connecting portion (portion indicated by a dashed line in FIG. 21 ) between the terminal and the outer frame portion of the lead frame may be cut with a die or the like.
  • the input terminals 41 to 43 are formed with tip surfaces 413, 423, and 433, respectively, that have input-side machining marks.
  • Each of the output terminals 44 is formed with a tip surface 443 that has an output-side machining mark.
  • the tie bars When the lead frame has tie bars that connect, in the y direction, terminals which are adjacent in the y direction, the tie bars may be cut with a die or the like. In this case, for each of the terminals, machining marks are formed on two side surfaces that face in the y direction.
  • the semiconductor module A1 shown in FIGS. 1 to 20 is manufactured through the steps described above.
  • the semiconductor module A1 is mounted on a circuit board for control, for example.
  • the metal pins 452 are inserted into pin holes of the circuit board on which the semiconductor module A1 is mounted, and are connected to terminals near the pin holes.
  • the input terminals 41, 42, and 43 have the input-side bonding surfaces 411, 421, and 431, respectively, that face in one sense (z2 direction) of the z direction.
  • Each of the output terminals 44 has the output-side bonding surface 441 facing in one sense (z2 direction) of the z direction.
  • the input-side bonding surfaces 411, 421, 431, and the output-side bonding surfaces 441 are connected with solder, for example, to the terminals of the circuit board on which the semiconductor module A1 is mounted.
  • the first main circuit current flows through a path that includes the input terminal 41, the first conductive portion 2A, the first semiconductor elements 10A, the first conducting members 61, the second conductive portion 2B, and the output terminals 44.
  • the first main circuit current flows along the x direction between the second obverse-surface electrodes 12 of the first semiconductor elements 10A and the second conductive portion 2B via the first conducting members 61.
  • the first main circuit current flows along the x direction and a direction slightly inclined from the x direction between the portions to which the first conducting members 61 are bonded and the output terminals 44.
  • the path of a current from the output terminals 44 to the input terminal 42 and the input terminal 43 is described below.
  • the second main circuit current flows through a path that includes the output terminals 44, the second conductive portion 2B, the second semiconductor elements 10B, the second conducting member 62, the input terminal 42, and the input terminal 43.
  • the second conducting member 62 forming the path of the second main circuit current, includes the third wiring portion 623 extending in the y direction and the first and second wiring portions 621, 622 joined to the respective ends of the third wiring portion 623 so as to extend in the x2 direction.
  • the second main circuit current flows through the third wiring portion 623 as well as the first wiring portion 621 and the second wiring portion 622.
  • the path of the second main circuit current includes the two second band portions 626 disposed between the first wiring portion 621 and the second wiring portion 622 so as to extend in the x direction and also includes the first band portion 625 disposed between the first wiring portion 621 and the second wiring portion 622 so as to extend in the y direction.
  • the second main circuit current flows through the first wiring portion 621 and the second wiring portion 622.
  • the second main circuit current flows between the input terminals 42, 43, and the second obverse-surface electrodes 12 of the second semiconductor elements 10B via a path including the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, the two second band portions 626, and the first band portion 625 in the second conducting member 62.
  • the second main circuit current flows along the x direction. The direction in which the first main circuit current flows is opposite from the direction in which the second main circuit current flows.
  • the direction in which the first main circuit current flows in the first conducting members 61 is the x direction, and the direction in which the second main circuit current flows in the first wiring portion 621, the second wiring portion 622, and the two second band portions 626 in the second conducting member 62 is also the x direction.
  • the semiconductor module A1 includes the conductive substrate 2, the input terminals 41 to 43, the output terminals 44, and the conducting member 6.
  • the conductive substrate 2 includes the first conductive portion 2A to which the first semiconductor elements 10A are bonded, and the second conductive portion 2B to which the second semiconductor elements 10B are bonded.
  • the input terminal 41 is joined to the first conductive portion 2A, and is electrically connected to the first semiconductor elements 10A via the first conductive portion 2A.
  • the input terminal 42 and the input terminal 43 are electrically connected to the second semiconductor elements 10B via the second conductive member 62 (conducting member 6).
  • the output terminals 44 are joined to the second conductive portion 2B, and are electrically connected to the second semiconductor elements 10B via the second conductive portion 2B.
  • the conducting member 6 includes the first conducting members 61 that electrically connect the first semiconductor elements 10A and the second conductive portion 2B, and the second conducting member 62 that electrically connects the second semiconductor elements 10B and the input terminals 42 and 43.
  • the input terminals 41 to 43 are offset in the x2 direction relative to the conductive substrate 2, and the output terminals 44 are offset in the x1 direction relative to the conductive substrate 2.
  • the two input terminals 42 and 43 are located opposite from each other with the input terminal 41 therebetween in the y direction.
  • a semiconductor module has a configuration different from the semiconductor module A1 in a manner such that no input terminal 43 is provided, and the input terminals 41 and 42 are arranged side by side in the y direction.
  • the semiconductor module A1 includes the two input terminals 42 and 43, and the two input terminals 42 and 43 flank the input terminal 41. This makes it possible to reduce variations in the path of a current flowing from the input terminal 41 to the output terminals 44 via the first semiconductor elements 10A, and to reduce variations in the path of a current flowing from the output terminals 44 to the input terminals 42 and 43 via the second semiconductor elements 10B. As a result, the parasitic inductance components of the semiconductor module A1 can be reduced. In other words, the semiconductor module A1 has a package configuration preferable for reducing parasitic inductance components.
  • the upper arm current path is the path of a current flowing from the input terminal 41 to the output terminals 44 via the first conductive portion 2A, the first semiconductor elements 10A, the first conducting members 61, and the second conductive portion 2B.
  • the upper arm current path extends from the x2 direction side to the x1 direction side.
  • the lower arm current path is the path of a current flowing from the output terminals 44 to the input terminal 42 via the second semiconductor elements 10B and the second conductive member 62.
  • the lower arm current path extends from the x1 direction side to the x2 direction side.
  • the conducting member 6 (each of the first conducting members 61 and the second conducting member 62) in the semiconductor module A1 is made of a metal plate-like member, so that an area where the upper arm current path and the lower arm current path overlap with each other in plan view can be provided appropriately.
  • the semiconductor module A1 has a package configuration preferable for reducing parasitic inductance components.
  • the second conducting member 62 that forms the lower arm current path includes the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624.
  • the first wiring portion 621 and the second wiring portion 622 extend in the x direction, and are respectively connected to the input terminal 42 and the input terminal 43 that are arranged opposite from each other with the input terminal 41 therebetween in the y direction.
  • the third wiring portion 623 is joined to the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to the second semiconductor elements 10B.
  • the fourth wiring portion 624 is joined to the first wiring portion 621 and the second wiring portion 622, and overlaps with the first semiconductor elements 10A in plan view.
  • the second conductive member 62 including the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624 is spaced apart from the obverse surface 201 (conductive substrate 2) in the z direction, and overlaps with a wide area of the obverse surface 201 in plan view.
  • This configuration can appropriately reduce variations in the path of a current flowing from the output terminals 44 to the input terminals 42 and 43 via the second semiconductor elements 10B, and therefore is suitable in reducing parasitic inductance components.
  • the first semiconductor elements 10A and the second semiconductor elements 10B overlap with each other as viewed in the x direction.
  • This configuration can suppress an increase in the dimension in the y direction of the conductive substrate 2 (first conductive portion 2A and the second conductive portion 2B) on which the first semiconductor elements 10A and the second semiconductor elements 10B are arranged, and can therefore reduce the size of the semiconductor module A1.
  • the fourth wiring portion 624 of the second conductive member 62 has the first band portion 625 and the second band portions 626.
  • the first band portion 625 is joined to the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and overlaps with the first semiconductor elements 10A in plan view.
  • Each of the second band portions 626 is connected to the first band portion 625 and the third wiring portion 623, and has a band shape extending in the x direction in plan view.
  • the second band portions 626 are spaced apart from each other in the y direction and arranged substantially in parallel to each other.
  • each band portion 626 is connected to a part of the first band portion 625, which is located between two first semiconductor elements 10A adjacent in the y direction, and the other end of each band portion 626 is connected to a part of the third wiring portion 623, which is located between two second semiconductor elements 10B adjacent in the y direction.
  • This configuration can increase the size of the fourth wiring portion 624 (second conductive member 62) in plan view. This is more preferable for reducing parasitic inductance components.
  • the first band portion 625 has the protruding areas 625a protruding in the z2 direction relative to the other areas.
  • the protruding areas 625a overlap with the first semiconductor elements 10A in plan view. According to the configuration in which the first band portion 625 has the protruding areas 625a, the first band portion 625 is prevented from making improper contact with the first conducting members 61 bonded to the first semiconductor elements 10A.
  • the third wiring portion 623 has the recessed areas 623a recessed in the z1 direction relative to the other areas.
  • the recessed areas 623a are bonded to the respective second semiconductor elements 10B.
  • This configuration can increase the size of the third wiring portion 623 (second conductive member 62) in plan view while electrically connecting the third wiring portion 623 (second conductive member 62) and the second semiconductor elements 10B in a suitable manner.
  • the semiconductor module A1 includes the conducting member 6 (first conducting members 61 and the second conducting member 62) having the configuration described above, and further includes the first control terminals 46A to 46E and the second control terminals 47A to 47D for controlling the first semiconductor elements 10A and the second semiconductor elements 10B.
  • the first control terminals 46A to 46E and the second control terminals 47A to 47D are provided on the obverse surface 201 of the conductive substrate 2 and extend along the z direction.
  • the semiconductor module A1 having this configuration can have a smaller size in plan view, and therefore is suitable for reducing the size in plan view while reducing parasitic inductance components.
  • the first control terminals 46A to 46E are supported by the first conductive portion 2A and offset in the x2 direction relative to the first semiconductor elements 10A.
  • the second control terminals 47A to 47D are supported by the second conductive portion 2B and offset in the x1 direction relative to the second semiconductor elements 10B.
  • the first control terminals 46A to 46E are arranged at intervals in the y direction, and the second control terminals 47A to 47D are also arranged at intervals in the y direction.
  • the first control terminals 46A to 46E and the second control terminals 47A to 47D are appropriately arranged in an area corresponding to the first semiconductor elements 10A that constitute the upper arm circuit, and in an area corresponding to the second semiconductor elements 10B that constitute the lower arm circuit, respectively.
  • the semiconductor module A1 having this configuration is more preferable for downsizing while reducing parasitic inductance components.
  • Each of the first semiconductor elements 10A and the second semiconductor elements 10B has a first obverse-surface electrode 11 (gate electrode) facing in the z2 direction.
  • the first control terminal 46A is connected to the first obverse-surface electrodes 11 (gate electrodes) of the first semiconductor elements 10A via the first wires 731a.
  • the second control terminal 47A is connected to the first obverse-surface electrodes 11 (gate electrodes) of the second semiconductor elements 10B via the second wires 731b.
  • the metal pins 452 are inserted into the pin holes of the circuit board on which the semiconductor module A1 is mounted, and are connected to terminals near the pin holes.
  • the input terminals 41, 42, and 43 have the input-side bonding surfaces 411, 421, and 431, respectively, that face in one sense (z2 direction) of the z direction.
  • the output terminals 44 have the output-side bonding surfaces 441 facing in one sense (z2 direction) of the z direction.
  • the input-side bonding surfaces 411, 421, 431, and the output-side bonding surfaces 441 are connected with solder, for example, to the terminals of the circuit board on which the semiconductor module A1 is mounted.
  • the power system circuit board to which the input terminals 41 to 43 and the output terminals 44 are connected and the control system circuit board to which the metal pins 452 are connected can be arranged in separation in the z direction.
  • This achieves the following improvements. Firstly, an improvement is made in the degree of freedom regarding the arrangement of a signal terminal in the semiconductor module A1. Secondly, an improvement is made in the degree of freedom regarding the routing and length of a signal wire in the semiconductor module A1. Thirdly, an improvement is made in the degree of freedom regarding the arrangement of a circuit board by a user when the semiconductor module A1 is used.
  • the control terminals 45 protrude from the resin obverse surface 81 and extend along the z direction.
  • the control terminals 45 may be arranged to extend along a plane (x-y plane) perpendicular to the z direction. This configuration has a limit to the size reduction in plan view.
  • the control terminals 45 can be arranged to extend along the z direction, so that the size of the semiconductor module A1 can be reduced in plan view.
  • the semiconductor module A1 has a package configuration preferable for the size reduction in plan view.
  • control terminal support 5 is provided between the control terminals 45 and the obverse surface 201 (conductive substrate 2).
  • the control terminal support 5 has the insulating layer 51, and the control terminals 45 are supported by the conductive substrate 2 via the control terminal support 5.
  • the configuration with the control terminal support 5 can support the control terminals 45 on the conductive substrate 2 appropriately while maintaining insulation from the conductive substrate 2.
  • the control terminal support 5 has a layup structure in which the insulating layer 51, the first metal layer 52, and the second metal layer 53 are stacked on each other.
  • the control terminals 45 are bonded to the first metal layer 52, which is formed as the upper surface of the control terminal support 5, via the conductive bonding member 459. According to the configuration, the control terminals 45 can be electrically bonded to the control terminal support 5 (first metal layer 52) while utilizing an existing layup structure (e.g., DBC substrate) as the control terminal support 5.
  • an existing layup structure e.g., DBC substrate
  • Each of the semiconductor elements 10 has an element obverse surface 101 facing in the z2 direction, and an element reverse surface 102 facing in the z1 direction.
  • a first obverse-surface electrode 11 (gate electrode) is provided on the element obverse surface 101.
  • the first obverse-surface electrode 11 of each of the semiconductor elements 10 and the first metal layer 52 (first portion 521) are connected by a wire 731 that is electrically conductive. This makes it possible to input a drive signal for driving the semiconductor elements 10 having a switching function to the first obverse-surface electrodes 11 appropriately, via the control terminals 45, the first metal layer 52, and the wires 731.
  • Each of the control terminals 45 includes a holder 451 and a metal pin 452.
  • the holder 451 is made of a conductive material, and includes a tubular portion.
  • the metal pin 452 is a rod-like member extending in the z direction, and is pressed into the holder 451. A part (the upper surface of the upper-end flange portion) of the holder 451 is exposed from the sealing resin 8.
  • the sealing resin 8 is formed (by molding) such that the holder 451 is covered with the sealing resin 8 except a part (upper end surface) of the holder 451, and the upper end surface of the holder 451 is exposed from the sealing resin 8.
  • This makes it possible to insert the metal pin 452 into the holder 451 after the sealing resin 8 is formed. Accordingly, with the configuration in which the control terminals 45 include the holders 451 and the metal pins 452, it is possible to avoid complexity of the mold 91 for a molding process. For this reason, this configuration is suitable for efficiently manufacturing the semiconductor module A1.
  • the semiconductor module A1 of the present embodiment includes the resin members 87 bonded to the sealing resin 8.
  • the resin members 87 cover parts (upper surfaces of the upper-end flange portions) of the holders 451 that are exposed from the sealing resin 8, and parts of the metal pins 452. This configuration prevents foreign matter from entering the connecting portions between the holders 451 and the metal pins 452.
  • the semiconductor module A1 having the above configuration is preferable for improving durability and reliability.
  • the sealing resin 8 has the second protrusions 852 protruding from the resin obverse surface 81.
  • the second protrusions 852 surround the respective control terminals 45 in plan view.
  • the metal pins 452 of the control terminals 45 protrude from the second protrusions 852.
  • the resin members 87 are provided on the second protrusions 852. According to this configuration, the creepage distance between adjacent control terminals 45 along the resin obverse surface 81 can be increased. This is preferable for increasing the withstand voltage of the adjacent control terminals 45.
  • the conductive substrate 2 includes the first conductive portion 2A and the second conductive portion 2B that are spaced apart from each other in the x direction.
  • the first conductive portion 2A is offset in the x2 direction relative to the second conductive portion 2B.
  • the semiconductor elements 10 include the first semiconductor elements 10A bonded to the first conductive portion 2A, and the second semiconductor elements 10B bonded to the second conductive portion 2B.
  • the control terminals 45 include the first control terminals 46A to 46E, and the second control terminals 47A to 47D.
  • the first control terminals 46A to 46E are supported by the first conductive portion 2A, and arranged between the first semiconductor elements 10A and the input terminals 41, 42, etc., in the x direction.
  • the second control terminals 47A to 47D are provided between the second semiconductor elements 10B and the output terminals 44 in the x direction.
  • the control terminals 45 (the first control terminals 46A to 46E, and the second control terminals 47A to 47D) are appropriately arranged in an area corresponding to the first semiconductor elements 10A that constitute the upper arm circuit, and in an area corresponding to the second semiconductor elements 10B that constitute the lower arm circuit.
  • the configuration is preferable for downsizing the semiconductor module A1.
  • the sealing resin 8 has the first protrusions 851 protruding from the resin obverse surface 81.
  • the tip end of each of the first protrusions 851 is formed with a first protruding end surface 851a.
  • the first protruding end surfaces 851a of the first protrusions 851 are substantially parallel to the resin obverse surface 81 and positioned on the same plane (x-y plane) as the resin obverse surface 81.
  • the semiconductor module A1 includes the conductive substrate 2 to which the semiconductor elements 10 are bonded. With this configuration, the heat generated by energization of the semiconductor elements 10 is transferred from the semiconductor elements 10 to the conductive substrate 2 and diffused at the conductive substrate 2. As such, the semiconductor module A1 has a package configuration preferable for improving the heat dissipation property of the semiconductor elements 10.
  • the conductive substrate 2 and the supporting substrate 3 are bonded to each other via the first conductive bonding member 71.
  • the first conductive bonding member 71 includes the first layer 712 and the second layer 713.
  • the first layer 712 is bonded to the conductive substrate 2 by the solid-phase diffusion of metal, and is in direct contact with the conductive substrate 2 at the bonding interface.
  • the second layer 713 is bonded to the supporting substrate 3 by the solid-phase diffusion of metal, and is in direct contact with the supporting substrate 3 at the bonding interface.
  • This configuration can increase the bonding strength between the conductive substrate 2 and the supporting substrate 3 as compared to the case where the conductive substrate 2 and the supporting substrate 3 are bonded by a bonding material such as solder. Accordingly, the semiconductor module A1 has a package configuration preferable for suppressing the peeling between the conductive substrate 2 and the support substrate 3.
  • the semiconductor elements 10 and the conductive substrate 2 are bonded to each other via the second conductive bonding member 72.
  • the second conductive bonding member 72 includes the third layer 722 and the fourth layer 723.
  • the third layer 722 is bonded to the semiconductor elements 10 (reverse surface electrodes 15) by the solid-phase diffusion of metal, and is in direct contact with the semiconductor elements 10 at the bonding interface.
  • the fourth layer 723 is bonded to the conductive substrate 2 by the solid-phase diffusion of metal, and is in direct contact with the conductive substrate 2 at the bonding interface.
  • This configuration can increase the bonding strength between the semiconductor elements 10 and the conductive substrate 2 as compared to the case where the semiconductor elements 10 and the conductive substrate 2 are bonded by a bonding material such as solder. Accordingly, the semiconductor module A1 has a package configuration preferable for suppressing the peeling between the semiconductor elements 10 and the conductive substrate 2.
  • the Young’s modulus of the first base layer 711 in the first conductive bonding member 71 is smaller than the Young’s modulus of the material of each of the first layer 712 and the second layer 713. According to the configuration, when the first conductive bonding member 71 is bonded to the conductive substrate 2 and the supporting substrate 3 by solid-phase diffusion, the stress is alleviated by the relatively soft first base layer 711, and the bonding boundary portion is thereby smoothed. As a result, the first layer 712 and the conductive substrate 2, as well as the second layer 713 and the supporting substrate 3, are more firmly bonded by solid-phase diffusion.
  • the first base layer 711 is thicker than each of the first layer 712 and the second layer 713. Accordingly, when bonding by solid-phase diffusion is performed, the pressing force acting on the boundary portion between the first layer 712 and the conductive substrate 2 (reverse-surface bonding layer 23) and on the boundary portion between the second layer 713 and the supporting substrate 3 (first bonding layer 321) is made more uniform. As a result, the first layer 712 and the conductive substrate 2, as well as the second layer 713 and the supporting substrate 3, can be in a stronger conductive bonding state.
  • each of the first layer 712 and the second layer 713 contains silver. With this composition, when bonding by solid-phase diffusion is performed with the first conductive bonding member 71, oxidation of the first layer 712 and the second layer 713 is suppressed, thus enabling excellent solid-phase diffusion bonding.
  • the Young’s modulus of the second base layer 721 in the second conductive bonding member 72 is smaller than the Young’s modulus of the material of each of the third layer 722 and the fourth layer 723.
  • the stress is alleviated by the relatively soft second base layer 721, and the bonding boundary portion is thereby smoothed.
  • the third layer 722 and the semiconductor elements 10 (reverse-surface electrodes 15), as well as the fourth layer 723 and the conductive substrate 2 are more firmly bonded by solid-phase diffusion.
  • the second base layer 721 is thicker than each of the third layer 722 and the fourth layer 723. Accordingly, when bonding by solid-phase diffusion is performed, the pressing force acting on the boundary portion between the third layer 722 and the semiconductor elements 10 (reverse-surface electrodes 15) and on the boundary portion between the fourth layer 723 and the conductive substrate 2 (obverse-surface bonding layers 22) is made more uniform. As a result, the third layer 722 and the semiconductor elements 10 (reverse-surface electrodes 15), as well as the fourth layer 723 and the conductive substrate 2, can be in a stronger conductive bonding state.
  • each of the third layer 722 and the fourth layer 723 contains silver. With this material composition, when bonding by solid-phase diffusion is performed with the second conductive bonding member 72, oxidation of the third layer 722 and the fourth layer 723 is suppressed, thus enabling excellent solid-phase diffusion bonding.
  • the first conductive bonding member 71 has a configuration where the first layer 712 and the second layer 713, which are Ag plating layers, are formed on the surfaces (both surfaces) of the first base layer 711, which is made of a sheet material containing A1.
  • the second conductive bonding member 72 has a configuration where the third layer 722 and the fourth layer 723, which are Ag plating layers, are formed on the surfaces (both surfaces) of the second base layer 721, which is made of a sheet material containing A1. With this configuration, the first conductive bonding member 71 and the second conductive bonding member 72 can be easily prepared.
  • the second conducting member 62 is formed with the openings 63.
  • the openings 63 overlap with the obverse surface 201 (conductive substrate 2) in plan view, and do not overlap with the semiconductor elements 10 in plan view.
  • the pressing pins 911 of the mold 91 can be inserted into the openings 63. This allows the pressing pins 911 to press the conductive substrate 2 without interfering with the second conducting member 62, thus suppressing the warpage of the supporting substrate 3 to which the conductive substrate 2 is bonded.
  • the warpage occurs, for example, such that the outer sides of the supporting substrate 3 in the y direction are positioned more upward than the center thereof in the y direction. If warpage occurs on the supporting substrate 3, the bonding strength between the conductive substrate 2 and the supporting substrate 3 may be lowered. Furthermore, during a molding process, a part of the sealing resin 8 may be formed on the bottom surface 302 due to resin leakage, causing a bonding failure of a heat dissipating member (e.g., heat sink) that can be bonded to the bottom surface 302.
  • a heat dissipating member e.g., heat sink
  • the semiconductor module A1 has a package configuration that is preferable for improving the bonding strength between the conductive substrate 2 and the supporting substrate 3 by suppressing the warpage of the supporting substrate 3, and that is also preferable for suppressing the leakage of the sealing resin 8 to an unintended location.
  • the conductive substrate 2 includes the first conductive portion 2A to which the first semiconductor elements 10A are bonded, and the second conductive portion 2B to which the second semiconductor elements 10B are bonded.
  • the first conductive portion 2A and the second conductive portion 2B are spaced apart from each other in the x direction, and the first conductive portion 2A is offset in the x2 direction relative to the second conductive portion 2B.
  • the second conducting member 62 is connected to the second semiconductor elements 10B and the input terminals 42 and 43, and the openings 63 in the second conducting member 62 overlap with the obverse surface 201 of the first conductive portion 2A in plan view.
  • the pressing pins 911 of the mold 91 can press the conductive substrate 2 without interfering with the second conducting member 62 during the formation (during the molding process) of the sealing resin 8. Note that the parasitic resistance components of the second conducting member 62 (conductive member 6) that forms the path of the main circuit current can be suppressed by increasing the size of the second conducting member 62 in plan view.
  • the second conducting member 62 includes the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624.
  • the first wiring portion 621 and the second wiring portion 622 extend in the x direction, and are respectively connected to the input terminal 42 and the input terminal 43 that are arranged opposite from each other with the input terminal 41 therebetween in the y direction.
  • the third wiring portion 623 is joined to the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to the second semiconductor elements 10B.
  • the openings 63 are formed in the areas of the first wiring portion 621 and the second wiring portion 622 that are offset in the x2 direction.
  • the openings 63 are provided near two corners of the conductive substrate 2 (first conductive portion 2A) at respective outer sides of the conductive substrate 2 in the y direction. Accordingly, the openings 63 are provided near two corners of the supporting substrate 3 supporting the conductive substrate 2 (first conductive portion 2A) at the respective outer sides of the supporting substrate 3 in the y direction.
  • the configuration as described above allows the size of the second conducting member 62 to be relatively large in plan view and, during the formation of the sealing resin 8 (molding process), areas near the two corners of the conductive substrate 2 (first conductive portion 2A) at the respective outer sides of the conductive substrate 2 in the y direction can be pressed with the pressing pins 911 of the mold 91 which are inserted into the openings 63.
  • the warpage of the supporting substrate 3 to which the conductive substrate 2 is bonded occurs such that the outer sides of the supporting substrate 3 in the y direction are positioned more upward than the center thereof in the y direction.
  • the configuration described above can effectively suppress the warpage of the supporting substrate 3 during the molding process.
  • the conducting member 6 (the first conducting members 61 and the second conducting member 62) is made of a metal plate-like member. This facilitates formation of the openings 63 in the second conducting member 62. Furthermore, the conducting member 6 (the first conducting members 61 and the second conducting member 62) made of a metal plate-like member can easily adapt to various shapes and sizes, and can increase the reliability of a bonding portion with another component by securing a sufficient bonding area with the other component.
  • the recessed portions 201a are marks left by the pressing pins 911 applying a pressing force to the obverse surface 201 during the molding process.
  • the sealing resin 8 is formed with the resin voids 86 passing from the resin obverse surface 81 to the recessed portions 201a.
  • Each of the resin voids 86 is tapered such that the cross-sectional area thereof decreases from the resin obverse surface 81 to the recessed portion 201a.
  • the resin voids 86 are formed during a molding process (when the sealing resin 8 is formed) . After the molding, the surfaces of the recessed portions 201a in the obverse surface 201 of the conductive substrate 2 are exposed from the sealing resin 8.
  • the resin-filling portions 88 are provided for the resin voids 86 to fill the resin voids 86. This configuration can prevent foreign matter (such as moisture) from entering the recessed portions 201a exposed from the sealing resin 8.
  • the semiconductor module A1 having the above configuration is preferable for improving durability and reliability.
  • the openings 63 in the second conducting member 62 (conducting member 6) are through-holes that penetrate through in the z direction. This configuration can prevent a deviation of the current path caused by forming the openings 63 in the second conducting member 62 (conducting member 6) that forms the path of a main circuit current.
  • the semiconductor module A1 includes the conducting member 6.
  • the conducting member 6 forms the path of a main circuit current switched by the semiconductor elements 10.
  • the conducting member 6 includes the first conducting members 61 connected to the first semiconductor elements 10A, and the second conducting member 62 connected to the second semiconductor elements 10B.
  • the conducting member 6 (each of the first conducting members 61 and the second conducting member 62) is made of a metal plate-like member.
  • the main circuit current described above may have a relatively large value. In this case, it is preferable to suppress the parasitic resistance components in the conducting member 6 that forms the path of the main circuit current in order to reduce the power consumption of the semiconductor module A1.
  • the conducting member 6 is made of a metal plate-like member instead of a bonding wire as described above to suppress the parasitic resistance components of the conducting member 6.
  • the semiconductor module A1 has a package configuration preferable for suppressing the parasitic resistance components.
  • each of the first semiconductor elements 10A has a rectangular shape in plan view, and the four corners of each of the first semiconductor elements 10A in plan view do not overlap with the second conducting member 62. According to this configuration, during the manufacturing process of the semiconductor module A1, it is possible to conduct visual inspection before forming the sealing resin 8 so as to check whether the first semiconductor elements 10A are properly bonded. In other words, the semiconductor module A1 allows for visual inspection regarding the bonding state of the first semiconductor elements 10A during the manufacturing process (e.g., the stage shown in FIG. 23 ). This makes it possible to determine whether the first semiconductor elements 10A are properly bonded.
  • the semiconductor module A1 can conduct visual inspection during the manufacturing process, and therefore has package configuration preferable for improving reliability. During the visual inspection, it is sufficient if at least three of the four corners of each of the first semiconductor elements 10A are visible in plan view. For this reason, it is sufficient if three corners of each of the first semiconductor elements 10A do not overlap with the second conducting member 62. Similarly, as shown in FIG. 5 , four corners of each of the second semiconductor elements 10B do not overlap with the second conducting member 62. Accordingly, during the manufacturing process of the semiconductor module A1, it is possible to conduct visual inspection before forming the sealing resin 8 so as to check whether the second semiconductor elements 10B are properly bonded.
  • the visual inspection may be automatic visual inspection that uses image-capturing and image processing.
  • the second conducting member 62 includes the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624.
  • the first wiring portion 621 and the second wiring portion 622 extend in the x direction, and are respectively connected to the input terminal 42 and the input terminal 43 that are arranged opposite from each other with the input terminal 41 therebetween in the y direction.
  • the third wiring portion 623 is joined to the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to the second semiconductor elements 10B.
  • the fourth wiring portion 624 is joined to the first wiring portion 621 and the second wiring portion 622.
  • the fourth wiring portion 624 is offset in the x2 direction relative to the third wiring portion 623, and overlaps with the first semiconductor elements 10A in plan view.
  • the second conductive member 62 including the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624 overlaps with a wide area of the obverse surface 201 in plan view, and has a relatively large size in plan view. Increasing the size of the second conducting member 62 in plan view is preferable in terms of suppressing the parasitic resistance components of the second conducting member 62 (conductive member 6) that forms the path of the main circuit current.
  • Each of the first semiconductor elements 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 in plan view.
  • the first side 191 and the second side 192 extend in the y direction.
  • the first side 191 is an edge located in the x2 direction in plan view
  • the second side 192 is an edge located in the x1 direction in plan view.
  • the third side 193 and the fourth side 194 extend in the x direction.
  • the third side 193 is an edge located in the y2 direction in plan view
  • the fourth side 194 is an edge located in the y1 direction in plan view.
  • each of the first semiconductor elements 10A has a rectangular shape in plan view, the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 are generally right-angled in plan view.
  • the fourth wiring portion 624 (the first band portion 625) of the second conducting member 62 has a first edge 627 and a second edge 628.
  • the first edge 627 is an edge of the fourth wiring portion 624 located in the x2 direction, and is offset in the x1 direction relative to the first side 191 in plan view.
  • the first edge 627 extends at least from the third side 193 to the fourth side 194 in the y direction.
  • the second edge 628 is an edge of the fourth wiring portion 624 (first band portion 625) located in the x1 direction, and is offset in the x2 direction relative to the second side 192 in plan view.
  • the second edge 628 extends at least from the third side 193 to the fourth side 194 in the y direction.
  • two corners 173 and 174 of each first semiconductor element 10A in the x1 direction do not overlap with the second conducting member 62 in plan view.
  • each of the first semiconductor elements 10A in plan view do not overlap with the second conducting member 62 while the size of the second conducting member 62 in plan view is increased by providing the fourth wiring portion 624 with areas that overlap with the first semiconductor elements 10A in plan view.
  • This makes it possible to effectively suppress the parasitic resistance components of the second conducting member 62 (conducting member 6), and to conduct visual inspection to check the bonding state of the first semiconductor elements 10A during the manufacturing process of the semiconductor module A1.
  • the fourth wiring portion 624 (first band portion 625) has the protruding areas 625a protruding in the z2 direction relative to the other areas.
  • the protruding areas 625a overlap with the first semiconductor elements 10A in plan view. According to the configuration in which the fourth wiring portion 624 has the protruding areas 625a, the fourth wiring portion 624 is prevented from making improper contact with the first conducting members 61 bonded to the first semiconductor elements 10A.
  • the third wiring portion 623 has the recessed areas 623a recessed in the z1 direction relative to the other areas.
  • the recessed areas 623a are bonded to the respective second semiconductor elements 10B.
  • This configuration can increase the size of the third wiring portion 623 (second conductive member 62) in plan view while electrically connecting the third wiring portion 623 (second conductive member 62) and the second semiconductor elements 10B in a suitable manner.
  • the first semiconductor elements 10A and the second semiconductor elements 10B overlap with each other as viewed in the x direction.
  • This configuration can suppress an increase in the dimension in the y direction of the conductive substrate 2 (first conductive portion 2A and the second conductive portion 2B) on which the first semiconductor elements 10A and the second semiconductor elements 10B are arranged, and can therefore reduce the size of the semiconductor module A1.
  • the semiconductor module A1 includes the conductive substrate 2, the two input terminals 41 and 42 (or the two input terminals 41 and 43), the output terminals 44, and the conducting member 6.
  • the conductive substrate 2 includes the first conductive portion 2A and the second conductive portion 2B aligned in the x direction in plan view.
  • the first semiconductor elements 10A are electrically bonded to the first conductive portion 2A.
  • the second semiconductor elements 10B are electrically bonded to the second conductive portion 2B.
  • the first semiconductor elements 10A and the second semiconductor elements 10B are arranged at intervals in the y direction.
  • the two input terminals 41 and 42 (or the two input terminals 41 and 43) are offset in the x2 direction relative to the first conductive portion 2A.
  • the input terminal 41 is a positive electrode, and is connected to the first conductive portion 2A.
  • the input terminal 42 (or the input terminal 43) is a negative electrode.
  • the output terminals 44 are offset in the x1 direction relative to the second conductive portion 2B.
  • the conducting member 6 includes the first conducting members 61 connected to the first semiconductor elements 10A and the second conductive portion 2B, and the second conducting member 62 connected to the second semiconductor elements 10B and the input terminal 42 (or the input terminal 43). According to this configuration, the path of the main circuit current switched by the semiconductor elements 10 (the first semiconductor elements 10A and the second semiconductor elements 10B) is formed along the x direction in plan view, and the axis of symmetry (see an auxiliary line L1 in FIG.
  • the semiconductor module A1 has a package configuration preferable for equalizing the parasitic inductance components in the path of the main circuit current and for equalizing the amount of current to the semiconductor elements 10.
  • the first semiconductor elements 10A and the second semiconductor elements 10B are spaced apart in the x direction.
  • the first semiconductor elements 10A and the second semiconductor elements 10B are aligned along the y direction. Accordingly, the direction in which the semiconductor elements 10 are aligned is perpendicular to the direction in which the first main circuit current or the second main circuit current flows. In this way, when a plurality of switching elements are connected in parallel for use as in the present embodiment, the difference in the length of the path of the first main circuit current between the three first semiconductor elements 10A can be reduced. This makes it possible to suppress the parasitic resistance components in the conducting member 6 that forms the path of the main circuit current.
  • the second conducting member 62 which connects the output terminals 44 to the input terminals 42 and 43 that are negative electrode terminals to let the second main circuit current flow, is arranged above the area (the first conductive portion 2A, the first conducting members 61, and the second conductive portion 2B) in which the first main circuit current flows.
  • the direction in which the first main circuit current flows is opposite from the direction in which the second main circuit current flows.
  • the semiconductor module A1 of the present embodiment includes the two input terminals 42 and 43.
  • the input terminals 42 and 43 are negative electrodes and flank the input terminal 41 in the y direction.
  • the two input terminals 42 and 43 are connected to the second conducting member 62. This configuration can further reduce variations in the path of a current flowing from the output terminals 44 to the input terminals 42 and 43 via the second semiconductor elements 10B and the second conducting member 62.
  • the second conducting member 62 includes the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624.
  • the first wiring portion 621 and the second wiring portion 622 extend in the x direction, and are respectively connected to the input terminal 42 and the input terminal 43 that are arranged opposite from each other with the input terminal 41 therebetween in the y direction.
  • the third wiring portion 623 is joined to the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to the second semiconductor elements 10B.
  • the fourth wiring portion 624 is offset in the x2 direction relative to the third wiring portion 623, and is joined to the first wiring portion 621, the second wiring portion 622, and the third wiring portion 623.
  • the second conductive member 62 including the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624 overlaps with a wide area of the obverse surface 201 in plan view, and has a relatively large size in plan view.
  • This configuration can appropriately reduce variations in the path of a current flowing from the output terminals 44 to the input terminals 42 and 43 via the second semiconductor elements 10B and the second conducting member 62.
  • the semiconductor module A1 of the present embodiment is more preferable for equalizing the parasitic inductance components in the path (second conducting member 62) of the main circuit current and for equalizing the amount of current to the semiconductor elements 10B.
  • the fourth wiring portion 624 is joined to the first wiring portion 621 and the second wiring portion 622, and overlaps with the first semiconductor elements 10A in plan view.
  • the fourth wiring portion 624 (first band portion 625) has the protruding areas 625a protruding in the z2 direction relative to the other areas.
  • the protruding areas 625a overlap with the first semiconductor elements 10A in plan view.
  • This configuration can increase the size of the fourth wiring portion 624 (second conductive member 62) in plan view, and can prevent the fourth wiring portion 624 from making improper contact with the first conducting members 61 bonded to the first semiconductor elements 10A.
  • the first semiconductor elements 10A and the second semiconductor elements 10B overlap with each other as viewed in the x direction.
  • This configuration can suppress an increase in the dimension in the y direction of the conductive substrate 2 (first conductive portion 2A and the second conductive portion 2B) on which the first semiconductor elements 10A and the second semiconductor elements 10B are arranged, and can therefore reduce the size of the semiconductor module A1.
  • FIGS. 30 to 32 illustrate a semiconductor module according to a second embodiment.
  • a semiconductor module A2 of the present embodiment is different from the semiconductor module A1 of the first embodiment in the configuration of the second conducting member 62.
  • the present embodiment is different from the first embodiment in the area occupied by the fourth wiring portion 624 of the second conducting member 62.
  • the dimension of the first band portion 625 in the x direction is larger than that of the semiconductor module A1.
  • the second edge 628 of the first band portion 625 is offset in the x1 direction as compared to the second edge 628 in the semiconductor module A1.
  • the second edge 628 is offset in the x1 direction relative to the second sides 192 of the first semiconductor elements 10A in plan view.
  • two corners of each first semiconductor element 10A in the x1 direction overlap with the second conducting member 62 (first band portion 625) in plan view.
  • the semiconductor module A2 of the present embodiment has the same advantages as the semiconductor module A1 of the first embodiment. Furthermore, in the semiconductor module A2, the first band portion 625 (second conducting member 62) of the fourth wiring portion 624 can have a larger size in plan view. This is more preferable for reducing parasitic inductance components.
  • FIGS. 33 and 34 illustrate a semiconductor module according to a third embodiment.
  • a semiconductor module A3 of the present embodiment is different from the semiconductor module A1 of the first embodiment mainly in the configuration of the second conducting member 62.
  • the second conducting member 62 of the semiconductor module A3 does not have any openings 63.
  • the mold 91 used to form the sealing resin 8 (by molding) in the manufacturing of the semiconductor module A3 is not provided with the pressing pins 911. Accordingly, as shown in FIG. 34 , the sealing resin 8 is not formed with the resin voids 86, and the obverse surface 201 of the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B) is not formed with the recessed portions 201a. Since the sealing resin 8 is not formed with the resin voids 86, the semiconductor module A3 of the present embodiment does not have any resin-filling portions 88 which are used to fill the resin voids 86 in the first embodiment.
  • the semiconductor module A3 of the present embodiment has the same advantages as the semiconductor module A1 of the first embodiment.
  • the semiconductor module according to the present disclosure is not limited to the above embodiments. Various design changes can be made to the specific configurations of the elements of the semiconductor module in the present disclosure.
  • the configuration described in the above embodiments includes two input terminals 42 and 43 (N terminals) to which the second conducting member 62 is connected, the present disclosure is not limited to this. It is possible to employ a configuration that includes only the input terminal 42 (N terminal), and the second conducting member 62 may be connected to the input terminal 42.
  • control terminals 45 extend along the z direction, but the present disclosure is not limited to this.
  • the control terminals 45 may extend along the plane (x-y plane) perpendicular to the z direction.
  • the second conducting member 62 includes the two second band portions 626 and the first band portion 625, but the two second band portions 626 and the first band portion 625 do not always need to be provided.
  • providing the two second band portions 626 and the first band portion 625 can suppress the misalignment of the semiconductor elements 10 and reduce inductance as compared to the configuration without the two second band portions 626 and the first band portion 625.
  • a semiconductor module comprising:
  • Clause 3 The semiconductor module according to clause 1 or 2, wherein the path of the main circuit current switched by the plurality of first semiconductor elements and the plurality of second semiconductor elements is formed along the first direction as viewed in the thickness direction.
  • Clause 4 The semiconductor module according to any of clauses 1 to 3, wherein the first conducting member includes a plurality of conducting portions respectively corresponding to the plurality of first semiconductor elements.
  • Clause 5 The semiconductor module according to any of clauses 1 to 4, further comprising a third input terminal that is offset in the one sense of the first direction relative to the plurality of first semiconductor elements, and that is connected to the second conducting member,
  • first input terminal is provided between the second input terminal and the third input terminal in the second direction.
  • the second conducting member includes a first wiring portion connected to the second input terminal and extending in the first direction, a second wiring portion connected to the third input terminal and extending in the first direction, a third wiring portion joined to the first wiring portion and the second wiring portion, extending in the second direction, and connected to the plurality of second semiconductor elements, and a fourth wiring portion offset in the one sense of the first direction relative to the third wiring portion, and joined to the first wiring portion, the second wiring portion, and the third wiring portion.
  • Clause 7 The semiconductor module according to clause 6, wherein the fourth wiring portion overlaps with the plurality of first semiconductor elements as viewed in the thickness direction.
  • Clause 8 The semiconductor module according to clause 7, wherein the fourth wiring portion has a plurality of protruding areas protruding in the thickness direction relative to other areas of the fourth wiring portion, each of the protruding areas overlapping with a corresponding one of the plurality of first semiconductor elements as viewed in the thickness direction.
  • Clause 10 The semiconductor module according to clause 9, wherein the plurality of first semiconductor elements and the plurality of second semiconductor elements overlap with each other as viewed in the first direction.
  • Clause 11 The semiconductor module according to any of clauses 5 to 10, wherein the first input terminal, the second input terminal, and the third input terminal overlap with each other as viewed in the second direction.
  • each of the first conducting member and the second conducting member is made of a metal plate-like member.
  • Clause 13 The semiconductor module according to clause 1, further comprising a control terminal connected to one of the plurality of first semiconductor elements and the plurality of second semiconductor elements,
  • control terminal is arranged on the obverse surface and extends along the thickness direction.
  • each of the first input terminal and the second input terminal has an input-side bonding surface extending in the one sense of the first direction and facing in one sense of the thickness direction, and
  • the output terminal has an output-side bonding surface extending in the other sense of the first direction and facing in the one sense of the thickness direction.
  • each of the first input terminal and the second input terminal has an input-side side surface and an input-side machining mark, the input-side side surface being located at a periphery of the input-side bonding surface as viewed in the thickness direction and facing in a direction intersecting with a normal of the input-side bonding surface, the input-side machining mark being formed on the input-side side surface, and
  • the output terminal has an output-side side surface and an output-side machining mark, the output-side side surface being located at a periphery of the output-side bonding surface as viewed in the thickness direction and facing in a direction intersecting with a normal of the output-side bonding surface, the output-side machining mark formed on the output-side side surface.
  • Clause 16 The semiconductor module according to any of clauses 1 to 15, further comprising a sealing resin covering at least a part of each of the first and second conductive portions, the plurality of first semiconductor elements, the plurality of second semiconductor elements, the first conducting member, and the second conducting member.
  • the sealing resin has a first resin side surface and a second resin side surface that are spaced apart from each other in the first direction, the second resin side surface is positioned closer to the second conductive portion than the first resin side surface, the second resin side surface has two ends spaced apart from each other in the second direction, and at least one of the ends is formed with a resin separation mark.
  • a semiconductor module comprising:
  • Clause 21 The semiconductor module according to clause 19 or 20, further comprising a third input terminal that is offset in the one sense of the first direction relative to the plurality of first semiconductor elements, and that is connected to the second conducting member,
  • the second conducting member includes a first wiring portion connected to the second input terminal and extending in the first direction, a second wiring portion connected to the third input terminal and extending in the first direction, a third wiring portion joined to the first wiring portion and the second wiring portion, extending in the second direction, and connected to the plurality of second semiconductor elements, and a fourth wiring portion that is offset in the one sense of the first direction relative to the third wiring portion, and that is joined to the first wiring portion, the second wiring portion, and the third wiring portion.
  • Clause 23 The semiconductor module according to clause 22, wherein the fourth wiring portion overlaps with the plurality of first semiconductor elements as viewed in the thickness direction.
  • Clause 24 The semiconductor module according to clause 23, wherein the fourth wiring portion has a plurality of protruding areas protruding in the thickness direction relative to other areas of the fourth wiring portion, each of the protruding areas overlapping with a corresponding one of the plurality of first semiconductor elements as viewed in the thickness direction.
  • Clause 26 The semiconductor module according to clause 25, wherein the plurality of first semiconductor elements and the plurality of second semiconductor elements overlap with each other as viewed in the first direction.
  • Clause 27 The semiconductor module according to any of clauses 21 to 26, wherein the first input terminal, the second input terminal, and the third input terminal overlap with each other as viewed in the second direction.
  • each of the first conducting member and the second conducting member is made of a metal plate-like member.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Inverter Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
US18/005,048 2020-10-14 2021-09-27 Semiconductor module Abandoned US20230307411A1 (en)

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JP2020173339 2020-10-14
JP2020-173339 2020-10-14
PCT/JP2021/035261 WO2022080122A1 (ja) 2020-10-14 2021-09-27 半導体モジュール

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US18/457,841 Active US11955451B2 (en) 2020-10-14 2023-08-29 Semiconductor module
US18/457,856 Active US11955452B2 (en) 2020-10-14 2023-08-29 Semiconductor module
US18/421,658 Active US12057426B2 (en) 2020-10-14 2024-01-24 Semiconductor module
US18/671,652 Pending US20240321811A1 (en) 2020-10-14 2024-05-22 Semiconductor module

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US18/421,658 Active US12057426B2 (en) 2020-10-14 2024-01-24 Semiconductor module
US18/671,652 Pending US20240321811A1 (en) 2020-10-14 2024-05-22 Semiconductor module

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JP (4) JP7354464B2 (ja)
CN (4) CN117525033A (ja)
DE (4) DE202021004377U1 (ja)
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
WO2024029274A1 (ja) * 2022-08-05 2024-02-08 ローム株式会社 半導体装置
WO2024057847A1 (ja) * 2022-09-15 2024-03-21 ローム株式会社 半導体装置

Family Cites Families (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5927563A (ja) 1982-08-07 1984-02-14 Mitsubishi Electric Corp 半導体装置
JPH0540903A (ja) * 1991-08-07 1993-02-19 Canon Inc 磁界発生装置
JP2993278B2 (ja) 1992-06-26 1999-12-20 富士電機株式会社 半導体装置
US5408141A (en) 1993-01-04 1995-04-18 Texas Instruments Incorporated Sensed current driving device
US5544412A (en) 1994-05-24 1996-08-13 Motorola, Inc. Method for coupling a power lead to a bond pad in an electronic module
US5532512A (en) 1994-10-03 1996-07-02 General Electric Company Direct stacked and flip chip power semiconductor device structures
JPH09148523A (ja) 1995-11-21 1997-06-06 Toshiba Corp 半導体装置
JPH104167A (ja) 1996-06-18 1998-01-06 Toshiba Corp 半導体装置
JP3491481B2 (ja) 1996-08-20 2004-01-26 株式会社日立製作所 半導体装置とその製造方法
CA2255441C (en) 1997-12-08 2003-08-05 Hiroki Sekiya Package for semiconductor power device and method for assembling the same
JP3547333B2 (ja) 1999-02-22 2004-07-28 株式会社日立産機システム 電力変換装置
JP4220094B2 (ja) 1999-04-05 2009-02-04 三菱電機株式会社 パワー半導体モジュール
JP3630070B2 (ja) 2000-03-30 2005-03-16 株式会社デンソー 半導体チップおよび半導体装置
DE10101086B4 (de) * 2000-01-12 2007-11-08 International Rectifier Corp., El Segundo Leistungs-Moduleinheit
JP4465906B2 (ja) * 2001-04-18 2010-05-26 株式会社日立製作所 パワー半導体モジュール
JP4177571B2 (ja) 2001-09-20 2008-11-05 三菱電機株式会社 半導体装置
DE10231091A1 (de) 2002-07-10 2004-01-22 Robert Bosch Gmbh Aktivgleichrichter-Modul für Drehstromgeneratoren von Fahrzeugen
JP2004107728A (ja) 2002-09-18 2004-04-08 Ebara Corp 接合材料及び接合方法
US6992283B2 (en) 2003-06-06 2006-01-31 Micromass Uk Limited Mass spectrometer
JP2005136264A (ja) 2003-10-31 2005-05-26 Mitsubishi Electric Corp 電力用半導体装置及び電力用半導体モジュール
JP4004460B2 (ja) 2003-12-16 2007-11-07 三菱電機株式会社 半導体装置
JP4196001B2 (ja) 2004-02-17 2008-12-17 パナソニック株式会社 半導体パワーモジュール
JP2006108247A (ja) 2004-10-01 2006-04-20 Ryosan Co Ltd 液冷ヒートシンク
JP2006190972A (ja) 2004-12-08 2006-07-20 Mitsubishi Electric Corp 電力用半導体装置
US7262444B2 (en) 2005-08-17 2007-08-28 General Electric Company Power semiconductor packaging method and structure
JP4429251B2 (ja) 2005-10-17 2010-03-10 三菱電機株式会社 電力変換装置
JP4450230B2 (ja) 2005-12-26 2010-04-14 株式会社デンソー 半導体装置
US8680666B2 (en) 2006-05-24 2014-03-25 International Rectifier Corporation Bond wireless power module with double-sided single device cooling and immersion bath cooling
CN101819965B (zh) 2006-06-09 2013-01-16 本田技研工业株式会社 半导体装置
JP5076440B2 (ja) 2006-10-16 2012-11-21 富士電機株式会社 半導体装置及び半導体装置の製造方法
JP5252819B2 (ja) 2007-03-26 2013-07-31 三菱電機株式会社 半導体装置およびその製造方法
US7759777B2 (en) 2007-04-16 2010-07-20 Infineon Technologies Ag Semiconductor module
JP4250191B2 (ja) * 2007-11-05 2009-04-08 株式会社ルネサステクノロジ Ｄｃ／ｄｃコンバータ用半導体装置
JP4924411B2 (ja) 2007-12-27 2012-04-25 三菱電機株式会社 電力半導体装置
EP2340560B1 (en) 2008-01-25 2013-07-10 Letrika Lab d.o.o. Power switching module
JP4683059B2 (ja) * 2008-02-21 2011-05-11 富士電機システムズ株式会社 樹脂封止型半導体装置の設置方法
JP2009200416A (ja) 2008-02-25 2009-09-03 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
JP4576448B2 (ja) 2008-07-18 2010-11-10 三菱電機株式会社 電力用半導体装置
JP4988665B2 (ja) * 2008-08-06 2012-08-01 日立オートモティブシステムズ株式会社 半導体装置および半導体装置を用いた電力変換装置
JP4634498B2 (ja) * 2008-11-28 2011-02-16 三菱電機株式会社 電力用半導体モジュール
JP4766162B2 (ja) 2009-08-06 2011-09-07 オムロン株式会社 パワーモジュール
JP2011086889A (ja) 2009-10-19 2011-04-28 Renesas Electronics Corp 半導体装置およびその製造方法
EP2548678B1 (en) 2010-03-15 2018-07-11 DOWA Electronics Materials Co., Ltd. Bonding material and bonding method using same
JP5319601B2 (ja) 2010-05-10 2013-10-16 株式会社東芝 半導体装置及び電力用半導体装置
JP5253455B2 (ja) 2010-06-01 2013-07-31 三菱電機株式会社 パワー半導体装置
US9018985B2 (en) 2010-08-04 2015-04-28 Rohm Co., Ltd. Power module and output circuit
JP5601376B2 (ja) 2010-12-01 2014-10-08 株式会社安川電機 電力変換装置
JP5464159B2 (ja) 2011-03-08 2014-04-09 三菱電機株式会社 パワーモジュール
JP5287919B2 (ja) 2011-04-01 2013-09-11 トヨタ自動車株式会社 ヒートシンク、およびヒートシンク付き電子部品
CN102201396A (zh) * 2011-05-31 2011-09-28 常州瑞华电力电子器件有限公司 一种大规格igbt模块及其封装方法
JP5602095B2 (ja) 2011-06-09 2014-10-08 三菱電機株式会社 半導体装置
JP5642022B2 (ja) 2011-06-17 2014-12-17 カルソニックカンセイ株式会社 半導体装置および半導体装置の製造方法
JP2013183023A (ja) 2012-03-01 2013-09-12 Toyota Industries Corp 電力変換装置
JP2013258387A (ja) * 2012-05-15 2013-12-26 Rohm Co Ltd パワーモジュール半導体装置
JP5924164B2 (ja) 2012-07-06 2016-05-25 株式会社豊田自動織機 半導体装置
EP4167279A3 (en) 2012-09-20 2023-09-13 Rohm Co., Ltd. Power semiconductor device module
JP2012248907A (ja) 2012-09-21 2012-12-13 Mitsubishi Electric Corp 電力半導体装置
JP6195767B2 (ja) * 2013-09-09 2017-09-13 新電元工業株式会社 半導体装置の端子案内部材、半導体装置及び半導体装置の製造方法
CN105794094B (zh) 2013-12-04 2018-09-28 三菱电机株式会社 半导体装置
JP6252293B2 (ja) 2014-03-26 2017-12-27 株式会社デンソー 半導体装置
JP2014135527A (ja) 2014-04-30 2014-07-24 Rohm Co Ltd 半導体パワーモジュールおよびその製造方法
JP6300633B2 (ja) 2014-05-20 2018-03-28 三菱電機株式会社 パワーモジュール
JP2016039202A (ja) 2014-08-06 2016-03-22 スズキ株式会社 インバータ装置
WO2016152258A1 (ja) 2015-03-23 2016-09-29 株式会社日立製作所 半導体装置
DE112016005570T5 (de) * 2016-01-05 2018-10-25 Hitachi Automotive Systems, Ltd. Leistungshalbleitervorrichtung
JP6920790B2 (ja) 2016-05-24 2021-08-18 ローム株式会社 インテリジェントパワーモジュール、電気自動車またはハイブリッドカー、およびインテリジェントパワーモジュールの組み立て方法
JP6834462B2 (ja) 2016-12-22 2021-02-24 住友金属鉱山株式会社 放熱基板
US10074590B1 (en) 2017-07-02 2018-09-11 Infineon Technologies Ag Molded package with chip carrier comprising brazed electrically conductive layers
JP6717270B2 (ja) 2017-07-27 2020-07-01 株式会社デンソー 半導体モジュール
DE112018005978T5 (de) * 2017-11-20 2020-08-06 Rohm Co., Ltd. Halbleitervorrichtung
JP6836201B2 (ja) * 2017-12-19 2021-02-24 株式会社デンソー 電力変換装置
WO2019235146A1 (ja) * 2018-06-08 2019-12-12 ローム株式会社 半導体モジュール
WO2020044668A1 (ja) * 2018-08-31 2020-03-05 ローム株式会社 半導体装置
EP3861638A4 (en) * 2018-10-01 2022-06-29 John Mezzalingua Associates, Llc D/B/A Jma Wireless Turbo decoder with reduced processing and minimal re-transmission
JP7273055B2 (ja) 2018-10-24 2023-05-12 ローム株式会社 半導体装置
JP7284566B2 (ja) * 2018-10-29 2023-05-31 ローム株式会社 半導体装置
DE112019006032T5 (de) 2018-12-03 2021-10-07 Rohm Co., Ltd. Halbleiterbauteil
JP2020092108A (ja) 2018-12-03 2020-06-11 ローム株式会社 半導体装置
WO2022080055A1 (ja) 2020-10-14 2022-04-21 ローム株式会社 半導体モジュール

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CN116825768B (zh) 2024-02-23
DE112021002942T5 (de) 2023-04-20
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JP2023181544A (ja) 2023-12-21
US20240321811A1 (en) 2024-09-26
CN117525033A (zh) 2024-02-06
DE212021000238U1 (de) 2022-05-19
CN116195051A (zh) 2023-05-30
US12057426B2 (en) 2024-08-06
JP2023168644A (ja) 2023-11-27
JP7382534B1 (ja) 2023-11-16
DE202021004377U1 (de) 2024-01-05
DE202021004375U1 (de) 2023-12-21
JP7354464B2 (ja) 2023-10-02
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CN116845058A (zh) 2023-10-03
JP2023145716A (ja) 2023-10-11
US20230402421A1 (en) 2023-12-14
US20230411339A1 (en) 2023-12-21
CN116845058B (zh) 2024-08-27
US11955452B2 (en) 2024-04-09
US20240170441A1 (en) 2024-05-23
CN116825768A (zh) 2023-09-29
WO2022080122A1 (ja) 2022-04-21

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