US20200203529A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20200203529A1
US20200203529A1 US16/568,737 US201916568737A US2020203529A1 US 20200203529 A1 US20200203529 A1 US 20200203529A1 US 201916568737 A US201916568737 A US 201916568737A US 2020203529 A1 US2020203529 A1 US 2020203529A1
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US
United States
Prior art keywords
semiconductor
layer
wiring
floating
semiconductor device
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Abandoned
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US16/568,737
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English (en)
Inventor
Takao Sueyama
Naohiro Matsukawa
Keiko Kaneda
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Kioxia Corp
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Toshiba Memory Corp
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Assigned to TOSHIBA MEMORY CORPORATION reassignment TOSHIBA MEMORY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANEDA, KEIKO, MATSUKAWA, NAOHIRO, SUEYAMA, TAKAO
Assigned to KIOXIA CORPORATION reassignment KIOXIA CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: TOSHIBA MEMORY CORPORATION
Publication of US20200203529A1 publication Critical patent/US20200203529A1/en
Priority to US18/316,610 priority Critical patent/US20230282747A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region

Definitions

  • the embodiment described herein relate to a semiconductor device.
  • a semiconductor wiring that connects between circuit elements is provided.
  • the embodiment provides a semiconductor device including a semiconductor wiring that suppresses an increase in resistance value occurring when a high voltage signal is transmitted.
  • FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor wiring provided in a semiconductor device according to an embodiment
  • FIG. 2 is a diagram showing an arrangement relationship between a poly wiring and a floating N-well layer
  • FIG. 3A is a diagram conceptually showing an energy band related to the poly wiring with a high voltage applied thereto and substrate hot electrons;
  • FIG. 3B is a diagram conceptually showing an energy band related to the poly wiring with a high voltage applied thereto and the floating N-well layer;
  • FIG. 4 is a block diagram showing an example of an entire configuration of a semiconductor memory device according to the embodiment.
  • FIG. 5 is a block diagram showing an example of a circuit configuration of a memory cell array of the semiconductor memory device
  • FIG. 6 is a diagram of a configuration example of a booster circuit
  • FIG. 7 is a cross-sectional diagram showing a modified example of the semiconductor wiring that applies an application voltage to the floating N-well layer
  • FIG. 8 is a diagram also describing an energy band when an intermediate voltage VM is applied in addition to the energy band related to the poly wiring with the high voltage applied thereto and the floating N-well layer;
  • FIG. 9 is a diagram showing an example of an output control circuit that performs feedback control.
  • the embodiment is applied to a region where there is disposed a semiconductor wiring whose resistance is reduced by impurity introduction processing or the like, for example, a poly wiring formed of a semiconductor material including polycrystalline silicon, that is, poly silicon.
  • the poly wiring is, for example, a poly wiring that electrically connects between circuit elements or a poly wiring used as a resistor element of circuit elements.
  • the poly wiring that electrically connects between circuit elements will be described as an example.
  • the poly wiring allows the value of wiring resistance to be adjusted by introducing impurities.
  • the embodiment is to suppress generation of hot electrons that affect the wiring or the like when the poly wiring transmits a high voltage signal, for example, a write signal Vpgm boosted to 20 V or more.
  • the hot electrons generated here are referred to as substrate hot electrons (SHE) because they are released from a P-type semiconductor substrate.
  • SHE substrate hot electrons
  • the substrate hot electrons occur, for example, when a high voltage signal is applied to the poly wiring formed on the P-type semiconductor substrate (or P-type well layer) and a surface of the semiconductor substrate becomes a deep depletion state (deeply depleted state).
  • a phenomenon occurs in which the substrate hot electrons generated there jump into the poly wiring and raise wiring resistance. It is presumed that the rise in wiring resistance is affected by release of hydrogen in the poly silicon partly caused by the hot electrons.
  • the rise in wiring resistance due to the generation of the substrate hot electrons may lower the voltage value of the signal being transmitted below a set voltage value, causing a possibility of occurrence of malfunction.
  • FIG. 1 shows a cross-sectional structure of a wiring formed on a semiconductor substrate
  • FIG. 2 shows a relationship between the wiring and a floating layer.
  • a poly wiring layer 33 composed of a poly silicon wiring layer is formed on a P-type semiconductor substrate (hereinafter referred to as a P substrate) 31 , via, for example, an insulating layer 32 composed of a silicon oxide film.
  • a P substrate P-type semiconductor substrate
  • an insulating layer 32 composed of a silicon oxide film.
  • an electrically floating impurity layer which is not used as a circuit element and which signals are not input into or output from is formed in the P substrate 31 in contact with the insulating layer 32 in a region where the poly wiring layer 33 and P substrate 31 face each other.
  • this impurity layer for example, an N-type layer which is an N-type semiconductor layer or an N-well layer 34 is formed. That is, in FIG.
  • a semiconductor wiring (or semiconductor resistor layer described later) having an integrated laminate structure of the N-well layer 34-insulating layer 32-poly wiring layer 33 is formed on the P substrate (P-well layer).
  • the semiconductor wiring is not limited to a structure in which the semiconductor wiring is horizontally extended and each layer is stacked in a depth direction (or height direction) and may have a structure in which the semiconductor wiring is extended in a direction intersecting with the horizontal direction and each layer is disposed in a side direction (or horizontal direction).
  • the N-well layer is described as an example, the same function and effect can be obtained even with an N-type layer.
  • the N-well layer 34 is referred to as floating N-well layer 34 because it is not connected with other circuit elements and electrically floating.
  • the P-type semiconductor and N-type semiconductor are referred to as semiconductor of a first conductivity type and semiconductor of a second conductivity type.
  • the P-type semiconductor and N-type semiconductor may be any conductivity types opposite to each other. That is, if the P-type semiconductor is the first conductivity type, the N-type semiconductor is the second conductivity type. Conversely, if the P-type semiconductor is the second conductivity type, the N-type semiconductor is the first conductivity type.
  • the embodiment shows an example in which the floating N-well layer, i.e.
  • the N-type floating layer is formed in the P substrate, on the contrary, a floating P-well layer, i.e. a P-type floating layer may be formed in the N substrate.
  • a floating P-well layer i.e. a P-type floating layer may be formed in the N substrate.
  • the N-type floating layer or P-type floating layer is referred to as floating layer.
  • impurities such as a pentavalent element, for example, phosphorus (P) or arsenic (As) are introduced, for example, by an ion injection process.
  • P phosphorus
  • As arsenic
  • Impurity concentration of the floating N-well layer 34 is appropriately set at the time of circuit element design, and, for example, it may be the same concentration as circuit elements such as a source and a drain included in an ordinary transistor.
  • the floating N-well layer 34 can be simultaneously formed in the same process in a step of forming N-well layers of other circuit elements of a transistor or the like.
  • the floating N-well layer 34 is boosted to a high voltage by capacitive coupling with the poly wiring layer 33 via the insulating layer 32 , and as shown in FIG. 3B described later, thereby substantially eliminating bending of a band in the vicinity of the insulating layer 32 of the semiconductor substrate immediately below the poly wiring layer 33 , suppressing generation of substrate hot electrons and substantially eliminating the band bending, and making it difficult for electrons cross a potential barrier.
  • a high voltage signal transmitted to the poly wiring layer 33 is presumed to be a pulse signal such as a clock signal, and one example is a write signal Vpgm transmitted to a word line WL.
  • a width W 2 of the floating N-well layer 34 is desired to be equal to or substantially equal to a width W 1 of the poly wiring layer 33 .
  • the width W 2 of the floating N-well layer 34 is less than the width W 1 of the poly wiring layer 33 , as long as a width W 3 obtained by adding a width of a depletion layer 35 generated around the floating N-well layer 34 to the width W 2 of the floating N-well layer 34 is equal to or more than the width W 1 of the poly wiring layer 33 , the same function and effect can be obtained.
  • one floating N-well layer 34 is formed as a pair below one poly wiring layer 33
  • one floating N-well layer 34 of a width encompassing the large number of poly wiring layers 33 may be formed. Because, when a high voltage signal is applied to the poly wiring layer 33 , by reducing capacitance with the P substrate 31 , the floating N-well layer 34 can be expected to raise potential, a thin layer thickness is desirable within a range in which there is an effect to suppress release of substrate hot electrons (SHE).
  • SHE substrate hot electrons
  • a layer thickness of the insulating layer 32 is appropriately set according to a withstand voltage with respect to the magnitude of a signal (voltage value and current value) transmitted to the poly wiring layer 33 and the impurity concentration and capacitance value of the floating N-well layer 34 .
  • a signal voltage value and current value
  • the insulating layer 32 needs a thickness that prevents the electric field from exceeding 5-6 MV/cm.
  • 6 MV corresponds to 40 nm. Therefore, the layer thickness of the insulating layer 32 needs to be a thickness of 40 nm or more.
  • the floating N-well layer 34 is formed in the P substrate, but it is not limited to the substrate. If a formation target of the wiring is a structure of stacking circuit elements, for example, a structure of stacking memory cell arrays 11 , the floating N layer or floating N-well layer 34 may be formed in a P-type semiconductor layer (or P-type semiconductor region) disposed at a position facing a wiring to be formed in the stacking layer.
  • the floating N-well layer 34 is formed on only one surface (surface facing the P substrate) side of the poly wiring layer 33 is described, but it is not limited to this.
  • the formation position of the floating N-well layer 34 shown in FIG. 1 is below the poly wiring layer 33 having a rectangular cross-sectional shape.
  • the floating N-well layer 34 may be formed in a P-type semiconductor layer in contact on the side of the rectangle, or the floating N-well layer 34 may be formed in a P-type semiconductor layer in contact on the upper side of the rectangle.
  • the floating N-well layer 34 is not limited to being disposed facing one surface side of the poly wiring layer 33 and may be provided so as to face one or more surfaces such as the upper and lower surfaces.
  • the poly wiring layer 33 is not limited to the rectangular cross-sectional shape, and may be formed, for example, in a circular shape or an elliptical shape. In that case, the floating N-well layer 34 may be formed so as to surround a half circumference or about a 1 ⁇ 3 circumference via the insulating layer.
  • FIG. 3A is a diagram conceptually showing an energy band related to the wiring with a high voltage applied thereto and substrate hot electrons
  • FIG. 3B is a diagram conceptually showing an energy band related to the wiring with a high voltage applied thereto and the floating N-well layer.
  • An energy band B shown in FIG. 3A shows characteristics of the wiring when a high voltage is applied to the poly wiring layer for which the floating N-well layer 34 is not provided.
  • the upper limit shows the characteristics of the energy of a conduction band bottom
  • the lower limit shows a valence electron band top.
  • the energy band B has band bending in which the level of an energy eV sharply decreases in the vicinity of an interface of the P substrate in contact with the insulating layer.
  • electrons (SHE) cross the potential barrier formed by the insulating layer 32 from within the P substrate 31 and jump into the poly wiring layer.
  • the hot electrons (SHE) affect characteristics of the intruded poly layer to increase its resistance value. That is, the resistance value of the poly wiring layer increases.
  • An energy band A shown in FIG. 3B when a high voltage is applied to the poly wiring layer 33 of the embodiment has band bending in which an energy eV decreases from the P substrate 31 to the interface of the floating N-well layer 34 by the floating N-well layer 34 .
  • the band bending of the energy eV the inclination of the bending changes due to the impurity concentration of the floating N-well layer 34 .
  • the band bending of the energy eV flattens, as shown in FIG. 3B , as the impurity concentration of the floating N-well layer 34 becomes higher.
  • the energy eV substantially does not increase or decrease, transits in parallel below the potential barrier (upper limit) of the interface of the insulating layer 32 , and is in contact with the potential barrier of the interface of the insulating layer 32 . Therefore, even if a high voltage signal is applied to the poly wiring layer, because the band bending of the energy eV is flattened, it is possible to suppress the release of substrate hot electrons (SHE) to the poly wiring layer 33 from the P substrate 31 via the N-well layer 34 due to the band bending.
  • SHE substrate hot electrons
  • the wiring of the embodiment suppresses the generation of substrate hot electrons, thereby can prevent an increase in wiring resistance of the poly wiring, prevent a reduction in voltage of a high voltage signal being transmitted, and transmit the signal of a voltage value preset to circuit elements. Furthermore, it can prevent an increase in power consumption amount and heat generation due to voltage rise to cope with high resistance of the wiring and also prevent acceleration of speed increasing the resistance value caused by an increase in SHE due to the voltage rise.
  • a semiconductor memory device As one example of the semiconductor device in which the semiconductor wiring according to the embodiment is provided, a semiconductor memory device will be described below.
  • FIG. 4 shows an example of the entire configuration of the semiconductor memory device 1 .
  • the semiconductor memory device 1 is controlled by, for example, an external memory controller 2 , and is a NAND flash memory capable of storing data in a nonvolatile manner.
  • the semiconductor memory device 1 includes, for example, a memory cell array 11 and peripheral circuits.
  • the peripheral circuits include, for example, a row decoder 12 , a sense amplifier 13 , a sequencer 14 , and a booster circuit 15 .
  • the memory cell array 11 includes a plurality of blocks BLK 0 -BLKn described later, where “n” is an integer of one or more.
  • a block BLK is a group of nonvolatile memory cells and is used as, for example, an erase unit of data.
  • a plurality of bit lines and a plurality of word lines are provided in a matrix.
  • One memory cell is associated with one bit line and one word line.
  • the row decoder 12 selects one block BLK on the basis of address information ADD received from the memory controller 2 by the semiconductor memory device 1 .
  • the row decoder 12 then applies a preset voltage, for example, an intermediate pass voltage Vpass (write inhibition signal) or a high voltage write voltage Vpgm (write signal) to, for example, each of selected word lines WL and unselected word lines WL.
  • a preset voltage for example, an intermediate pass voltage Vpass (write inhibition signal) or a high voltage write voltage Vpgm (write signal) to, for example, each of selected word lines WL and unselected word lines WL.
  • the sense amplifier 13 holds write data DAT received from the memory controller 2 by the semiconductor memory device 1 , and applies a write signal of a set voltage to the bit line on the basis of the write data DAT.
  • the sense amplifier 13 determines data stored in the memory cell on the basis of a voltage of the bit line and outputs read data DAT based on the determination result to the memory controller 2 .
  • the sequencer 14 controls overall operation of the semiconductor memory device 1 on the basis of a command CMD received from the memory controller 2 by the semiconductor memory device 1 .
  • Communication between the semiconductor memory device 1 and memory controller 2 supports, for example, a NAND interface standard.
  • communication between the semiconductor memory device 1 and memory controller 2 uses a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready busy signal RBn, and an input/output signal I/O.
  • the input/output signal I/O is, for example, a signal of eight bits and includes a command CMD, address information ADD, data DAT, and the like.
  • the command latch enable signal CLE is a signal indicating that an input/output signal I/O received by the semiconductor memory device 1 is a command CMD.
  • the address latch enable signal ALE is a signal indicating a signal I/O received by the semiconductor memory device 1 is address information ADD.
  • the write enable signal WEn is a signal instructing the semiconductor memory device 1 to input an input/output signal I/O.
  • the read enable signal REn is a signal instructing the semiconductor memory device 1 to output an input/output signal I/O.
  • the ready busy signal. RBn is a signal notifying the memory controller 2 whether the semiconductor memory device 1 is in a ready state of receiving an instruction from the memory controller 2 or in a busy state of not receiving the instruction.
  • the booster circuit 15 is a circuit that boosts a clock signal (pulse signal) ⁇ or / ⁇ (inverted signal of ⁇ ) or the like output from an oscillation circuit disposed in a previous stage to a voltage value set to each component and supplies a boosted voltage signal.
  • the boosted voltage signal is supplied to the memory cell array 11 , row decoder 12 , and sense amplifier 13 .
  • the wiring of the embodiment is used in part of the output side of the booster circuit 15 .
  • the semiconductor memory device 1 and memory controller 2 described above may form one semiconductor memory device by a combination of them.
  • Examples of such a semiconductor memory device include a memory card like an SDTM card (registered trademark), and an SSD (Solid State Drive).
  • the block BLK 0 includes, for example, four string units SU (SU 0 -SU 3 ).
  • Each of the string units SU includes a plurality of NAND strings NS.
  • Each of the NAND strings NS includes, for example, 64 memory cell transistors MT 0 -MT 63 , 5 dummy memory cell transistors MTDD 0 a, MTDD 0 b, MTDD 1 , MTDS 0 and MTDS 1 , and select transistors ST 1 and ST 2 .
  • the memory cell transistors MT 0 -MT 63 are not limited, they are represented as memory cell transistor MT.
  • the dummy memory cell transistors MTDD 0 a, MTDD 0 b, MTDD 1 , MTDS 0 , and MTDS 1 are not limited, they are represented as dummy memory cell transistor MTD.
  • the memory cell transistor MT and dummy memory cell transistor MTD each include a control gate and a charge storage layer.
  • the memory cell transistor MT holds data in a non-volatile manner.
  • the dummy memory cell transistor MTD has the same configuration as the memory cell transistor MT but is used as a dummy and is not used to hold data.
  • the memory cell transistor MT and dummy memory cell transistor MTD may be a MONOS type using an insulating layer for the charge storage layer, or may be an FG type using a conductive layer for the charge storage layer.
  • the MONOS type is described below as an example.
  • the number of memory cell transistors MT may be 8, 16, 32, 96, 128, or the like, and the number is not limited.
  • the numbers of the dummy memory cell transistors MTD and select transistors ST 1 and ST 2 are arbitrary. Regarding the select transistors ST 1 and ST 2 , one or more each should be provided.
  • Gates of the select transistors ST 1 of the string units SU 0 -SU 3 are connected to select gate lines SGD 0 -SGD 3 , respectively. Gates of the select transistors ST 2 of the string units SU 0 -SU 3 are commonly connected to a select gate line SGS.
  • select gate lines SGD 0 -SGD 3 are not limited, they are represented as select gate line GSD Note that the gates of the select transistors ST 2 of the string units SU 0 -SU 3 may be connected to different select gate lines SGS 0 -SGS 3 , respectively.
  • Control gates of the memory cell transistors MT 0 -MT 63 in the blocks BLK are commonly connected to word lines WL 0 -WL 63 , respectively.
  • Control gates of the dummy memory cell transistors MTDD 0 a and MTDD 0 b disposed in the blocks ELK are commonly connected to a dummy word line DD 0 .
  • Control gates of the dummy memory cell transistors MTDD 1 , MTDS 0 , and MTDS 1 disposed in the blocks BLK are commonly connected to dummy word lines DD 1 , DS 0 , and DS 1 , respectively.
  • word line WL when any of the word lines WL 0 -WL 63 is not limited, it is generically referred to as word line WL.
  • DD when any of the dummy word lines DD 0 and DD 1 is not limited, it is generically referred to as dummy word line DD, and when any of the dummy word lines DS 0 and DS 1 is not limited, it is referred to as dummy word line DS in the same manner.
  • dummy memory cell transistors MTDD 0 a and MTDD 0 b when any of the dummy memory cell transistors MTDD 0 a and MTDD 0 b is not limited, it is generically referred to as dummy memory cell transistor MTDD 0 .
  • Drains of the select transistors ST 1 of each NAND string NS in the string unit SU are connected to different bit lines BL 0 -BL (N ⁇ 1, where “N” is an integer of two or more), respectively.
  • bit lines BL 0 -BL (N ⁇ 1) is not limited, it is represented as bit line BL.
  • Each bit line EL commonly connects one NAND string NS in each string unit SU among the plurality of blocks ELK.
  • sources of the plurality of select transistors ST 2 are commonly connected to a source line SL. That is, the string unit SU is an aggregation of NAND strings NS connected to different bit lines EL and connected to the same select gate line SGD.
  • the block BLK is an aggregation of a plurality of string units SU sharing the word line WL.
  • the memory cell array 10 is a group of a plurality of blocks BLK sharing the bit line BL.
  • FIG. 6 is a diagram indicating an example of configuration example of the booster circuit 15 .
  • the booster circuit 15 is equivalent to a charge pump circuit.
  • the booster circuit 15 boosts an input pulse signal or the like to a positive voltage larger than a supplied external voltage Vcc to generate a high voltage signal VP.
  • the booster circuit 15 that generates a positive voltage will be described as an example, but a negative voltage smaller than the external voltage Vcc can be also generated by arranging an anode and a cathode in the opposite direction with respect to a diode D shown in FIG. 6 .
  • the diode D is shown as a circuit element in the embodiment, it is also possible to substitute a MOS transistor.
  • the MOS transistor When the MOS transistor is used, it can be implemented by connecting its gate to the drain, causing the drain to function as a cathode, and causing the source to function as an anode. Therefore, a diode can be manufactured by changing connection of a circuit element formed as a transistor without adding a manufacturing step for creating the diode.
  • Diodes D 1 -Dn of the booster circuit 15 are connected in series so as to connect the cathode of a previous stage diode, for example, the diode D 1 to the anode of the subsequent stage diode D 2 .
  • the anode of the first stage diode D 1 is connected to a supply terminal 21 and supplied with the external voltage Vcc.
  • the cathode serving as an output end of the last stage diode Dn is connected to an output terminal 22 .
  • the clock signal ⁇ is input into the cathodes of the odd-numbered stage diodes D 1 , D 3 , . . . via capacitor elements C 1 , C 3 , . . . .
  • the inverted clock signal / ⁇ is input into the cathodes of the even-numbered stage diodes D 2 , D 4 , . . . via the capacitor elements C 2 , C 4 , . . .
  • the poly wiring layer 33 including the floating N-well layer 34 i.e. the wiring of the embodiment is applied to a wiring shown by a thick line connecting the cathode of the last stage diode Dn and the output terminal 22 .
  • the booster circuit 15 outputs signals VP boosted to any given voltage values set for each supply destination to the memory cell array 11 , row decoder 12 , and sense amplifier 13 .
  • the row decoder 12 outputs the write signal Vpgm of 20 V or more to the word line WL.
  • the row decoder 12 selects the word line WL 62 , applies the write signal Vpgm of a high voltage of 24 V or so, and applies the pass voltage signal Vpass of an intermediate voltage of, for example, 10 V to each of the unselected word lines WL 0 , WL 1 , WL 61 , WL 63 . Consequently, the semiconductor wiring layer 33 including the floating N-well layer 34 of the embodiment is applied to the word lines WL 0 -WL 63 .
  • a wiring connecting the booster circuit 15 (for example, a first circuit) and a circuit element, for example, the row decoder 12 (for example, a second circuit) when there is a wiring having long wiring distance including interlayer connection that connects an upper layer and a lower layer, for example, a metal wiring is also used.
  • the poly wiring layer 33 in the embodiment may be used as a partial or short line when used to connect among a plurality of circuits or when used as a wiring around circuit elements viewed from the whole wiring.
  • the semiconductor wiring of the embodiment can be applied to a memory cell array developed two-dimensionally and word lines WL in each layer of memory cells of a hierarchical structure in which such memory cells are hierarchically stacked.
  • Using the semiconductor wiring for the word line WL can suppress substrate hot electrons (SHE) due to a high voltage signal such as the write signal Vpgm, prevent a rise in voltage value and an increase in power consumption, and eliminate one cause of heat generation.
  • SHE substrate hot electrons
  • FIG. 7 shows a cross-sectional configuration of the poly wiring layer 33 including an island N-well layer 36 which is a modified example.
  • This modified example shows the N-well layer 36 in which part of the insulating layer 32 on the P substrate 31 shown in FIG. 1 is removed, an exposed window 32 a is opened to the floating N-well layer 34 (or N-type layer), and an external terminal Vapp is connected.
  • the N-well layer 36 is not used as a circuit element either, signals (such as an information signal and a control signal) are not input or output, and so it is in an island state. Therefore, the N-well layer 36 is normally an impurity layer of a floating potential.
  • the N-well layer 36 becomes electrically charged up state when an arbitrary voltage VM is applied from the external terminal Vapp.
  • the floating N-well layer 34 with a voltage applied thereto is referred to as island N-well layer 36 (island impurity layer).
  • the island N-well layer 36 is good as long as it is in a charged up state when a high voltage is applied to the poly wiring layer 33 . Therefore, application of the arbitrary voltage to the island N-well layer 36 needs to be applied at least when a high voltage is applied to the poly wiring layer 33 , and it is not essential to constantly apply the arbitrary voltage to the island N-well layer 36 .
  • FIG. 8 is a diagram also describing an energy band when an intermediate voltage VM, for example, 18 V or so is applied to the island N-well layer 36 from the outside through the external terminal Vapp in addition to the energy band shown in FIG. 3B described before.
  • an intermediate voltage VM for example, 18 V or so
  • the energy level rises and an energy level of a forbidden band due to the insulating layer 32 also rises.
  • the thickness of the insulating layer 32 is preferably 40 nm or more.
  • the concentration of the P substrate 31 is low, that is, the concentration of the P substrate 31 «the concentration of the island N-well layer 36 , Cox»Cpn. Therefore, the potential VN-well ⁇ 24 V, which is almost no voltage difference from 24 V of the poly wiring layer 33 , and so almost no voltage is applied to the insulating layer 32 .
  • the capacitance Cpn becomes larger, that is, Cox/(Cox+Cpn) becomes smaller than one, thereby the potential VN-well is also decreased and the effect is also reduced.
  • a second application example uses the semiconductor wiring according to the embodiment as a resistor element.
  • FIG. 9 shows an example of an output control circuit that performs feedback control.
  • the semiconductor wiring according to the embodiment allows a desired resistance value to be obtained by appropriately setting concentration of the impurities, length of the resistor element in the direction of flow of current, element cross-sectional area, and the like.
  • the semiconductor wiring is used as a resistor element
  • the resistor element causes a voltage drop corresponding to the resistance value to a signal being transmitted.
  • the resistor element can be set to, for example, a resistance value of several tens k ⁇ .
  • the second application example is an example in which the semiconductor wiring is used for resistors R 1 and R 2 as the resistor element.
  • the output control circuit includes the resistors R 1 and R 2 that branch off and obtain the output of the booster circuit 15 and detect a monitor potential, and an operation amplifier M 1 that performs control so as to eliminate a difference between the detected monitor potential and a reference potential.
  • the resistors R 1 and R 2 of the output control circuit are connected in series and detect a voltage applied to a connection point between the resistor R 1 and resistor R 2 as the monitor potential.
  • a voltage division ratio of the resistors R 1 and R 2 is set so that the monitor voltage becomes the same potential as the reference voltage.
  • the booster circuit 15 outputs, for example, the output signal of the high voltage of 24 V as described before. For this reason, the same output signal is also applied to a voltage dividing resistance line as well as an output line to which the output signal of the boosted potential is transmitted. Therefore, in the voltage dividing resistance line composed of the resistors R 1 and R 2 , if a semiconductor wiring (poly wiring) having a conventional structure is used, the above-described substrate hot electrons occur and the resistance values of the resistors R 1 and R 2 fluctuate including individual different increase. The fluctuation of the resistance values also varies the voltage division ratio of the resistors R 1 and R 2 , and also has an impact on the monitor potential. If the monitor voltage inappropriately fluctuates, the output of the booster circuit 15 is made unstable.
  • the semiconductor wiring (poly layer+insulating layer+floating N-type layer) is used as resistance elements for the resistors R 1 and R 2 so that the resistance values do not fluctuate due to the generation of substrate hot electrons.
  • the poly layer When the poly layer is used as a resistor, it causes a voltage drop in its layer, causing regions from a high voltage to a low voltage to exist.
  • the floating N-type layer is more effective if it is placed just under the high voltage region. A similar effect is obtained if the floating N-type layer of the high voltage region is separated from the floating N-type layer of the low voltage region.
  • the layer thickness of the insulating layer is set to a thickness of 40 nm or more.
  • the floating N-type layer preferably has an impurity concentration of 10 or more times of the P substrate, and has a thickness by which the depletion layer does not reach the insulating layer when a maximum voltage is applied.
  • the semiconductor wiring including the floating N-type layer as a resistor element
  • the generation of substrate hot electrons is prevented and thereby the fluctuation of the resistance value can be suppressed.
  • the fluctuation of the resistance value of the resistor element used as a circuit element By suppressing the fluctuation of the resistance value of the resistor element used as a circuit element, deterioration in operation and characteristic of the circuit element is prevented, and desired performance can be maintained. An increase in power consumption due to the fluctuation of the resistance value can be prevented, and one cause of heat generation can be prevented.
  • the semiconductor wiring of the embodiment described as the second application example is not only used as the resistor element, but also it is preferable for a circuit element and wiring to which a high voltage is applied, and can be applied to, for example, a NOR-type memory circuit and a CMOS circuit.

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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