US20180012974A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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US20180012974A1
US20180012974A1 US15/527,105 US201515527105A US2018012974A1 US 20180012974 A1 US20180012974 A1 US 20180012974A1 US 201515527105 A US201515527105 A US 201515527105A US 2018012974 A1 US2018012974 A1 US 2018012974A1
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source
region
trench
semiconductor device
source trench
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Yuki Nakano
Ryota Nakamura
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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Definitions

  • the present invention relates to a semiconductor device that has a trench gate structure, and relates to a method for manufacturing the semiconductor device.
  • the highly-concentrated impurity region as electric-charge path to the channel region. It is possible to restrain variation in gate threshold voltage by using the region that is lower in resistance than impurity region of the bottom part and the side part of the source trench as an electric-charge path. As a result, it is possible to restrain variation in ⁇ Vth between chips in a semiconductor wafer plane, and therefore, if a module is formed by use of a plurality of chips that are individual pieces created from a semiconductor wafer in which the thus formed structure has been employed, it is possible to reduce a switching time lag in the module.
  • the source trench may be formed as a single source trench or as two source trenches in a cutting plane that appears when the semiconductor layer is cut in a direction of a depth of the source trench.
  • the contact portion is selectively formed at a part of the source region.
  • the contact portion is formed so as to extend in at least two directions from an upper side of the source trench.
  • the source trench may be formed in a quadrangle or a quadrangular ring shape in a plan view in an inner region of the gate trench formed in the grid-shaped manner, and the contact portion may be formed so as to extend outwardly from four sides of the source trench.
  • a repeated pattern of a line-and-space shape may be formed by the gate trench and the source trench, or a repeated pattern of a hexagon may be formed by the gate trench.
  • the electrode-film residue may be formed so as to selectively cover a peripheral edge part of the second contact portion.
  • the highly-concentrated impurity region includes a second contact portion formed at at-least one part of a peripheral part of the source trench, and the semiconductor device may include an electrode-film residue disposed in the source trench.
  • the source trench is formed in a stripe manner
  • the semiconductor device includes a convex portion formed between the source trench and the source trench both of which are adjacent to each other, and the second contact portion may be formed at a surface part of the convex portion.
  • the source trench may have a depth equal to a depth of the gate trench, and, meanwhile, may have a width greater than a width of the gate trench.
  • a method for manufacturing a semiconductor device of the present invention provides a semiconductor-device manufacturing method that includes a step of forming a source region of a first conductivity type and a channel region of a second conductivity type in order from a surface of a semiconductor layer, a step of forming a gate trench that defines the source region so as to have a predetermined shape and a source trench located in the source region, a step of forming an impurity region at a bottom part and a side part of the source trench by implanting an impurity of the second conductivity type into the source trench in a state in which a surface of the source region is masked, and a step of forming a highly-concentrated impurity region, which passes through the source region and extends to a position deeper than the source region and which has a concentration higher than the impurity region, by implanting an impurity of the second conductivity type in a state in which the surface of the source region is partially masked.
  • This method makes it possible to manufacture a semiconductor device according to one preferred embodiment of the present invention.
  • FIG. 2 is a view to describe one preferred embodiment of the semiconductor device.
  • FIG. 3 is a flowchart to describe a method for manufacturing the semiconductor device.
  • FIG. 4 is a view to describe the step that forms the p type region.
  • FIG. 7 is a view to describe a step of forming a p type region.
  • FIG. 8 is a view to describe a step of forming a p + type channel contact region.
  • FIG. 10 is a view to describe one preferred embodiment of the semiconductor device.
  • FIG. 11 is a view to describe a variation improvement effect of ⁇ Vth.
  • FIG. 1 is a schematic plan view of a semiconductor device 1 according to one preferred embodiment of the present invention.
  • the semiconductor device 1 includes a SiC substrate 2 as an example of a semiconductor layer.
  • the SiC substrate 2 is composed of an active portion 3 that is disposed at its central part and that functions as a field-effect transistor and an outer peripheral portion 4 that surrounds the active portion 3 .
  • a source electrode 5 made of, for example, aluminum is formed so as to cover substantially the whole area of the active portion 3 .
  • the source electrode 5 has a substantially square shape in a plan view.
  • a removal region 6 that surrounds a central part of the source electrode 5 along the outer peripheral portion 4 is formed at a peripheral edge of the source electrode 5 .
  • the removal region 6 has its part selectively hollowed toward the central part of the source electrode 5 .
  • a gate pad 7 is placed at this hollowed part.
  • a gate finger 8 made of, for example, aluminum extends over the entire removal region 6 from the gate pad 7 along the outer peripheral portion 4 .
  • a pair of gate fingers 8 are formed in a symmetrical shape with respect to the gate pad 7 .
  • a gate trench 9 is formed in the SiC substrate 2 directly under the source electrode 5 etc.
  • the gate trench 9 is formed at the active portion 3 .
  • the gate trench 9 is formed in a grid-shaped manner.
  • the pattern of the gate trench 9 is not limited to that of the grid-shaped manner.
  • the gate trench 9 may be formed in a stripe-shaped manner or a honeycomb-shaped manner.
  • FIG. 2 is a view that shows one preferred embodiment of the semiconductor device 1 in detail, in which the source trench 13 has the first pattern.
  • the source trench 13 is formed at a central part of each unit cell 10 .
  • the source trench 13 has the same depth as the gate trench 9 , and, on the other hand, has a width larger than the gate trench 9 .
  • the source trench 13 integrally includes a side surface 21 , a bottom surface 22 , and a corner portion 23 that is an intersection portion between the side surface 21 and the bottom surface 22 .
  • the source trench 13 is formed in the shape of the letter U in cross section so that the corner portion 23 becomes a curved plane.
  • An insulating-film residue 24 and an electrode-film residue 25 remain at a lower part of the source trench 13 .
  • the insulating-film residue 24 is selectively present at the corner portion 23 and around the corner portion 23 so as to expose a central part of the bottom surface 22 .
  • the electrode-film residue 25 is present only on the insulating-film residue 24 . In other words, the flat surface pattern of the insulating-film residue 24 and that of the electrode-film residue 25 match each other.
  • n + type source region 11 , the p type channel region 12 , and an n ⁇ type drain region 26 are formed in this order at each unit cell 10 from the front surface of the n ⁇ type active layer 15 toward the reverse surface thereof. These regions 11 , 12 , and 26 are contiguous to each other.
  • the n ⁇ type drain region 26 is a part of the n ⁇ type active layer 15 that is positionally lower than the p type channel region 12 .
  • a trench-gate type MOS transistor structure is thus formed in which the n + type source region 11 and the n ⁇ type drain region 26 are disposed apart from each other through the p type channel region 12 in the vertical direction perpendicular to a front surface of the SiC substrate 2 .
  • n + type source region 11 forms a part of the side surface 16 of the gate trench 9 and a part of the side surface 21 of the source trench 13 .
  • the p type channel region 12 forms a part of the side surface 16 of the gate trench 9 and a part of the side surface 21 of the source trench 13 .
  • the n ⁇ type drain region 26 forms the corner portion 18 and the bottom surface 17 of the gate trench 9 and the corner portion 23 and the bottom surface 22 of the source trench 13 .
  • the n ⁇ type drain region 26 and the p type channel region 12 connected to the p type region 27 are present in an intermediate region between the outer surface and the gate trench 9 .
  • the thickness of the p type region 27 (depth in the lateral direction from the side surface 21 or depth in the longitudinal direction from the bottom surface 22 ) is, for example, 0.4 ⁇ m to 1.5 ⁇ m.
  • a p + type channel contact region 28 is further formed at the n ⁇ type active layer 15 (for example, a concentration of 1 ⁇ 10 18 cm ⁇ 3 to 5 ⁇ 10 21 cm ⁇ 3 ).
  • the p + type channel contact region 28 has a concentration higher than the p type channel region 12 and the p type region 27 .
  • the p + type channel contact region 28 integrally includes a first contact portion 29 , a longitudinal extension portion 30 , and a second contact portion 31 .
  • the first contact portion 29 is selectively formed at a part of the outer peripheral portion (n + type source region 11 ) that surrounds the source trench 13 . In the present preferred embodiment, it is formed so as to extend outwardly from central parts of four sides of the quadrangular source trench 13 in a plan view. An arrangement is formed such that the first contact portion 29 is formed at only a part of the outer peripheral portion of the source trench 13 , and therefore it is possible to widely secure a contact region with respect to the n + type source region 11 in the front surface of the SiC substrate 2 while it is possible to connect the source electrode 5 to the p + type channel contact region 28 . Therefore, it is possible to restrain a rise in source contact resistance.
  • a forward end of the first contact portion 29 is disposed apart inwardly from the gate trench 9 .
  • the n + type source region 11 having a predetermined width is secured between the forward end of the first contact portion 29 and the gate trench 9 , and therefore, likewise, in this position, it is possible to electrically connect the source electrode 5 to the n + type source region 11 .
  • the forward end of the first contact portion 29 is further disposed on an inner side than the outer surface on the longitudinal side of the p type region 27 . Additionally, the thickness of the first contact portion 29 (depth in the longitudinal direction from the front surface of the n ⁇ type active layer 15 ) is 0.1 ⁇ m to 0.3 ⁇ m.
  • the longitudinal extension portion 30 extends from the first contact portion 29 to a position deeper than the n + type source region 11 , and faces the p type channel region 12 beside the gate trench 9 .
  • the longitudinal extension portion 30 extends along the inner surface of the source trench 13 with substantially the same width as the first contact portion 29 , and is connected to the second contact portion 31 in a central part of a region surrounded by the outer peripheral sides of the source trench 13 .
  • the longitudinal extension portion 30 is exposed to the inner surface of the source trench 13 , and, on the other hand, is disposed apart inwardly from the gate trench 9 .
  • the first contact portion 29 is arranged as a drawn portion drawn outwardly from the longitudinal extension portion 30 in an upper part of the source trench 13 . Additionally, the thickness (depth in the lateral direction from the side surface 21 of the source trench 13 ) of the longitudinal extension portion 30 is smaller than the thickness of the first contact portion 29 , and is, for example, 0.05 ⁇ m to 0.25 ⁇ m.
  • the second contact portion 31 is formed in the region surrounded by the outer peripheral sides of the source trench 13 .
  • the source trench 13 has a shape defined by only the outer peripheral sides in a plan view, and the second contact portion 31 is selectively formed at the central part of the bottom surface 22 of the source trench 13 .
  • the second contact portion 31 is formed so as to have a size large enough to straddle the inside and outside of the insulating-film residue 24 .
  • the thickness (depth in the longitudinal direction from the bottom surface 22 of the source trench 13 ) of the second contact portion 31 is 0.1 ⁇ m to 0.3 ⁇ m.
  • This thickness is smaller than the thickness of the p type region 27 , and therefore the second contact portion 31 is formed in a state of floating to a surface part of the p type region 27 .
  • the second contact portion 31 is formed in the p type region 27 , and, as a result, it is possible to reduce the sheet resistance of the p type region 27 of a bottom part of the source trench 13 . Therefore, it is possible to reduce the resistance of a body diode formed by the pn junction between the p type region 27 and the n ⁇ type drain region 26 .
  • An interlayer film 32 is formed on the SiC substrate 2 so as to cover the gate electrode 20 .
  • the interlayer film 32 is made of, for example, an insulating material, such as silicon oxide (SiO 2 ).
  • a contact hole 33 larger in diameter than the source trench 13 is formed in the interlayer film 32 . As a result, the n + type source region 11 , the first contact portion 29 , and the second contact portion 31 of each unit cell 10 are exposed in the contact hole 33 .
  • the source electrode 5 is formed on the interlayer film 32 .
  • the source electrode 5 is connected to the n + type source region 11 , to the first contact portion 29 , and to the second contact portion 31 together in the contact hole 33 .
  • the source electrode 5 has a layered structure consisting of a barrier layer 34 and a metal layer 35 .
  • the barrier layer 34 is stacked on the interlayer film 32 , and the metal layer 35 is formed thereon.
  • the barrier layer 34 is made of, for example, titanium/titanium nitride (Ti/TiN), and the metal layer 35 is made of, for example, aluminum (Al) or an aluminum-copper alloy (Al—Cu).
  • a drain electrode 36 is formed at a reverse surface of the SiC substrate 2 .
  • the drain electrode 36 is an electrode shared among all unit cells 10 .
  • the drain electrode 36 has a layered structure consisting of a metal silicide layer 37 and a metal layer 38 .
  • the metal silicide layer 37 is stacked on the SiC substrate 2 , and the metal layer 38 is formed thereon.
  • the metal silicide layer 37 is made of, for example, nickel (Ni) silicide, titanium (Ti) silicide, or the like, and the metal layer 38 is made of, for example, aluminum (Al) or an aluminum-copper alloy (Al—Cu).
  • FIG. 3 is a flowchart to describe a method for manufacturing the semiconductor device 1 .
  • a SiC crystal is grown on the base substrate 14 while being doped with an n type impurity (for example, N (nitrogen), P (phosphorus), As (arsenic), or the like) according to an epitaxial growth method, such as a CVD method, an LPE method, or an MBE method (step S 1 ).
  • an epitaxial growth method such as a CVD method, an LPE method, or an MBE method (step S 1 ).
  • the n type active layer 15 is formed on the base substrate 14 .
  • a p type impurity for example, Al (aluminum), B (boron), or the like
  • a p type impurity for example, Al (aluminum), B (boron), or the like
  • an n type impurity is implanted into the n ⁇ type active layer 15 .
  • the SiC substrate 2 is annealed at, for example, 1400° C. to 2000° C. (step S 2 ).
  • the p type impurity and the n type impurity that have been implanted into the n ⁇ type active layer 15 are activated, and the p type channel region 12 and the n + type source region 11 are simultaneously formed in accordance with places into which those impurities have been implanted.
  • the n ⁇ type drain region 26 that maintains the state of the n ⁇ type active layer 15 that has already made epitaxial growth is formed at a lower part of the p type channel region 12 .
  • step S 3 the gate trench 9 and the source trench 13 are formed.
  • the SiC substrate 2 is etched by use of a mask that has an opening in a region in which the gate trench 9 and the source trench 13 are to be formed.
  • the SiC substrate 2 undergoes dry etching from its front surface, and the gate trench 9 and the source trench 13 are simultaneously formed.
  • many unit cells 10 are formed in the SiC substrate 2 .
  • a mixed gas including sulfur hexafluoride (SF 6 ) and oxygen (O 2 ) or a mixed gas (SF 6 /O 2 /HBr gas) including SF 6 , O 2 , and hydrogen bromide (HBr) as an etching gas.
  • a mask 39 with which the whole area of the SiC substrate 2 excluding the source trench 13 is covered is formed on the SiC substrate 2 .
  • an outlined part is the opening portion of the mask 39 .
  • the p type impurity is implanted toward the source trench 13 exposed from the opening portion of the mask 39 .
  • the implantation of this impurity is performed by diagonal implantation in which the impurity is allowed to strike in an inclined direction with respect to a normal direction of the front surface of the SiC substrate 2 .
  • the incident angle of the impurity is controlled by, for example, a magnetic field.
  • the p type impurity is implanted into the entire inner surface of the source trench 13 .
  • the SiC substrate 2 is annealed at, for example, 1400° C. to 2000° C. (step S 4 ).
  • the p type impurity implanted thereinto is activated, and the p type region 27 is formed.
  • a mask 40 that selectively exposes the source trench 13 and a part of the n + type source region 11 is formed on the SiC substrate 2 .
  • an outlined part is the opening portion of the mask 40 .
  • the p type impurity is implanted toward the source trench 13 and the n + type source region 11 exposed from the opening portion of the mask 40 .
  • the p type impurity is implanted under the condition that it is higher in dose amount and is lower in energy than when the p type region 27 is formed.
  • the implantation of this impurity is performed by diagonal implantation in which the impurity is allowed to strike in an inclined direction with respect to the normal direction of the front surface of the SiC substrate 2 .
  • the SiC substrate 2 is annealed at, for example, 1400° C. to 2000° C. (step S 5 ).
  • the p type impurity implanted thereinto is activated, and the p + type channel contact region 28 that integrally includes the first contact portion 29 , the longitudinal extension portion 30 , and the second contact portion 31 is formed.
  • the gate insulating film 19 and the gate electrode 20 are formed (step S 6 ).
  • a SiO 2 material is deposited on the SiC substrate 2 according to, for example, the CVD method.
  • the gate insulating film 19 is formed.
  • a polysilicon material is deposited on the SiC substrate 2 according to, for example, the CVD method.
  • the polysilicon material continues to be deposited at least until the gate trench 9 and the source trench 13 are completely filled therewith. Thereafter, the polysilicon material is etchbacked until an etchback surface becomes flush with the front surface of the SiC substrate 2 .
  • the gate electrode 20 is formed.
  • an electrode-film residue 25 made of a remaining polysilicon material is formed at the source trench 13 .
  • the interlayer film 32 that has the contact hole 33 is formed (step S 7 ).
  • a SiO 2 material is deposited on the SiC substrate 2 according to, for example, the CVD method.
  • the interlayer film 32 is formed.
  • the interlayer film 32 and the gate insulating film 19 continuously undergo patterning.
  • the contact hole 33 that passes through the interlayer film 32 and through the gate insulating film 19 is formed.
  • a part of the gate insulating film 19 remains as the insulating-film residue 24 at a part sandwiched between the electrode-film residue 25 and the inner surface of the source trench 13 .
  • step S 8 the semiconductor device 1 shown in FIG. 2 is obtained.
  • the semiconductor device 1 it is possible to use the first contact portion 29 and the longitudinal extension portion 30 as an electric-charge path to the p type channel region 12 .
  • the p + type channel contact region 28 is formed according to diagonal implantation under the condition that it is higher in dose amount and is lower in energy than when the p type region 27 is formed. This makes it possible to also efficiently implant the impurity into the side surface 21 of the source trench 13 in which an impurity-implantation amount is liable to become smaller than in the front surface of the SiC substrate 2 or in the bottom surface 22 of the source trench 13 , and makes it possible to form the longitudinal extension portion 30 along the side surface 21 of the source trench 13 without disconnection.
  • the p type region 27 is formed according to diagonal implantation, there is a case in which disconnection occurs particularly in the side surface 21 of the source trench 13 because it has a wider range and a smaller dose amount than the p + type channel contact region 28 .
  • the first contact portion 29 is formed so as to extend from the four sides of the source trench 13 in different four directions. Therefore, for example, even if the mask 40 positionally deviates downwardly in the sheet of the drawing so that the formation region of one first contact portion 29 is covered with the mask 40 when the mask 40 of FIG. 5 is formed, it is possible to reliably expose the formation regions of the remaining three first contact portions 29 . Therefore, it is possible to reliably format least three first contact portions 29 . It is possible to achieve this effect, for example, even when the first contact portion 29 extends only in different two directions along the left-right direction of the drawing sheet. In other words, it is possible to reliably form at least right-hand first contact portions 29 placed on the right side of the drawing sheet even if the mask 40 positionally deviates in the left-right direction of the drawing sheet.
  • FIG. 6 is a view showing one preferred embodiment of the semiconductor device 1 in detail, in which the source trench 13 has the second pattern.
  • the same reference sign is given to a component corresponding to each component shown in FIGS. 1 to 5 mentioned above, and a description of this component is omitted.
  • the source trench 13 is formed in a quadrangular ring shape in a plan view. As a result, a convex portion 41 (mesa portion) defined by inner peripheral sides of the source trench 13 is formed in an inner region of the source trench 13 . Additionally, the source trench 13 has the same depth and width as the gate trench 9 .
  • the p type region 27 is formed at an outer edge part of the source trench 13 and in the whole of its inner region in the same way as the arrangement of FIG. 2 . Therefore, the p type region 27 has an outer surface that extends from the p type channel region 12 in the longitudinal direction along the side surface 21 and that extends in the lateral direction along the bottom surface 22 , and, in addition, has an outer surface that extends in the lateral direction along the front surface of the SiC substrate 2 below the convex portion 41 . As a result, the semiconductor device 1 of FIG. 6 has the p type region 27 formed deeper than the source trench 13 below the convex portion 41 . In the present preferred embodiment, the convex portion 41 has its most parts consisting of the p type region 27 , which exclude its surface part.
  • the second contact portion 31 is formed at the whole of the surface part of the convex portion 41 .
  • the longitudinal extension portion 30 is formed so as to come around through the bottom part of the source trench 13 from the outer edge part to the inner edge part of the source trench 13 . It is connected to the first contact portion 29 at the outer edge part thereof, and is connected to the second contact portion 31 at the inner edge part thereof.
  • the longitudinal extension portion 30 includes parts that are formed at the side part and the bottom part on the outer side of the source trench 13 and that are formed at the side part on the inner side of the source trench 13 in a side portion (cross section A-A) of the source trench 13 .
  • the longitudinal extension portion 30 includes parts that are not formed at the side part and the bottom part on the outer side of the source trench 13 and that are selectively formed at the side part on the inner side of the source trench 13 in a corner portion (cross section B-B) of the source trench 13 .
  • the insulating-film residue 24 is formed at the entire inner surface of the source trench 13 , and the electrode-film residue 25 is embedded in the inside thereof.
  • the insulating-film residue 24 and the electrode-film residue 25 have the same arrangement as the gate insulating film 19 and the gate electrode 20 , except that those residues are not covered with the interlayer film 32 .
  • a mask 42 with which the whole area of the n + type source region 11 excluding both the source trench 13 and the convex portion 41 is covered as shown in FIG. 7 when a p type impurity is implanted.
  • a mask 43 by which the whole of the convex portion 41 is exposed and by which the source trench 13 and a part of the n+ type source region 11 are selectively exposed as shown in FIG. 8 when a p type impurity is implanted.
  • the gate trench 9 may be formed in a stripe manner, and two stripe-shaped source trenches 13 may be formed between the gate trenches 9 .
  • a repeated pattern of a line-and-space shape may be formed by the gate trench 9 and the source trench 13 .
  • a convex portion 44 stripe mesa portion defined by the inner peripheral sides of the source trench 13 is formed between the two source trenches 13 .
  • the second contact portion 31 may be formed at the surface part of the convex portion 44 , of course, in the same way as in FIG. 6 .
  • the gate trench 9 may be formed in a honeycomb manner, and, as a result, a repeated pattern of a regular hexagonal unit cell 10 may be formed.
  • the source trench 13 may have a regular hexagonal shape or a regular hexagonal ring shape in a plan view.
  • the longitudinal extension portion 30 is not required to be exposed to the inner surface of the source trench 13 if the p + type channel contact region 28 is formed such that the first contact portion 29 is able to make contact with the front surface of the SiC substrate 2 .
  • the first contact portion 29 is not necessarily required to be formed at the peripheral edge part of the source trench 13 , and can be formed at an arbitrary position of the n + type source region 11 .
  • the second contact portion 31 that has a longer distance from the p type channel region 12 than the first contact portion 29 can also be excluded if necessary.
  • the p type part may be an n type part
  • the n type part may be a p type part
  • a semiconductor employed in the semiconductor device 1 is not limited to SiC, and may be, for example, Si, GaN, diamond, or the like.
  • chips 47 hatchched chips
  • chips 48 outlined chips
  • variation in ⁇ Vth between chips in a wafer plane was remarkable.

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US11189709B2 (en) 2021-11-30
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CN107004714A (zh) 2017-08-01
WO2016080322A1 (ja) 2016-05-26
US20220052177A1 (en) 2022-02-17
CN107004714B (zh) 2021-09-28
JP6763779B2 (ja) 2020-09-30

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