US20160308013A1 - Semiconductor device and production method - Google Patents
Semiconductor device and production method Download PDFInfo
- Publication number
- US20160308013A1 US20160308013A1 US15/191,853 US201615191853A US2016308013A1 US 20160308013 A1 US20160308013 A1 US 20160308013A1 US 201615191853 A US201615191853 A US 201615191853A US 2016308013 A1 US2016308013 A1 US 2016308013A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor layer
- insulating film
- film
- columnar
- planar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 823
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 116
- 229910052751 metal Inorganic materials 0.000 claims abstract description 328
- 239000002184 metal Substances 0.000 claims abstract description 328
- 238000005530 etching Methods 0.000 claims abstract description 67
- 239000010410 layer Substances 0.000 claims description 797
- 238000000034 method Methods 0.000 claims description 171
- 230000008569 process Effects 0.000 claims description 65
- 239000000758 substrate Substances 0.000 claims description 42
- 239000011229 interlayer Substances 0.000 claims description 23
- 239000002019 doping agent Substances 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 315
- 229910052710 silicon Inorganic materials 0.000 description 268
- 239000010703 silicon Substances 0.000 description 268
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 47
- 229920005591 polysilicon Polymers 0.000 description 47
- 150000001875 compounds Chemical class 0.000 description 43
- 230000004888 barrier function Effects 0.000 description 40
- 150000004767 nitrides Chemical class 0.000 description 40
- 239000000203 mixture Substances 0.000 description 36
- 238000011109 contamination Methods 0.000 description 26
- 230000003071 parasitic effect Effects 0.000 description 14
- SWXQKHHHCFXQJF-UHFFFAOYSA-N azane;hydrogen peroxide Chemical compound [NH4+].[O-]O SWXQKHHHCFXQJF-UHFFFAOYSA-N 0.000 description 13
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 13
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 9
- 229910052785 arsenic Inorganic materials 0.000 description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 9
- 229910052796 boron Inorganic materials 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 238000010438 heat treatment Methods 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 229910052715 tantalum Inorganic materials 0.000 description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910020177 SiOF Inorganic materials 0.000 description 3
- 229910020175 SiOH Inorganic materials 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000006263 metalation reaction Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
- H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Definitions
- This application relates generally to a semiconductor device and a method of producing such.
- MOS transistors in integrated circuits have been downsized to nano sizes as the integration level is increased.
- problems arise arise such as difficulty in leaking current control. For that reason, further downsizing is difficult.
- SGT surrounding gate transistor
- Patent Literature 1 discloses a method for producing an SGT satisfying to a certain extent the various conditions stated above.
- Patent Literature 1 International Laid-Open Patent Publication 2009/110049
- Patent Literature 1 the protection of semiconductor manufacturing equipment and semiconductor devices from metal contamination is imperfect.
- the gate electrode is formed by planarizing the gate metal using CMP (Chemical Mechanical Polishing) and then etching this material.
- CMP Chemical Mechanical Polishing
- the gate metal is not covered by other materials and is exposed.
- the gate metal is similarly exposed during the process of wet etching the nitride film hard mask and nitride film sidewall. Consequently, there is a concern that the CMP device, the gate etching device and the nitride film wet etching device could be contaminated by metal in the course of producing the SGT.
- a semiconductor device produced through such a metal device could be contaminated by metal.
- the gate metal when forming a metal-semiconductor compound through etching in Patent Literature 1, the gate metal is exposed. Consequently, per Patent Literature 1, the gate metal needs to be tantalum or some other material that is not etched by the chemicals used when forming the metal-semiconductor compound.
- the semiconductor device includes a first planar layer comprising a first planar semiconductor layer, a second planar semiconductor layer, and a planar insulating layer separating the first and second planar semiconductor layers;
- first insulating film overlying the planar insulating layer and between the first gate electrode and the first planar semiconductor layer, the first insulating film comprising an insulating material different from the first gate insulating film.
- the semiconductor device according to another aspect of the present invention is a semiconductor device provided with:
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first gate electrode composed of the first metal film and the first semiconductor film
- a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround the upper region of the first columnar semiconductor layer;
- a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film;
- first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film.
- the thickness of the second insulating film is preferable for the thickness of the second insulating film to be thicker than the sum of the thickness of the first gate insulating film and the thickness of the first metal film.
- the semiconductor device prefferably has a first metal-semiconductor compound formed on the upper surface of the first high concentration semiconductor layer.
- the length from the center of the first columnar semiconductor layer to the edge of the first planar semiconductor layer is larger than the sum of the length from the center to the sidewall of the first columnar semiconductor layer, the thickness of the first gate insulating film, the thickness of the first gate electrode and the thickness of the third insulating film.
- the semiconductor device prefferably has a third metal-semiconductor compound formed on the top surface of the first gate electrode.
- the semiconductor device prefferably has a second metal-semiconductor compound formed on the top surface of the second high concentration semiconductor layer.
- the semiconductor device according to a yet another aspect of the present invention is provided with a first transistor and a second transistor, wherein:
- the first transistor has:
- a first high concentration semiconductor layer of second conductive type formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a second high concentration semiconductor layer of second conductive type formed on the upper region of the first columnar semiconductor layer
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first gate electrode composed of the first metal film and the first semiconductor film
- a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround upper region of the first columnar semiconductor layer;
- a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film;
- the second transistor has:
- a third high concentration semiconductor layer of first conductive type formed on the lower region of the second columnar semiconductor layer and on the region of the second planar semiconductor layer below the second columnar semiconductor layer;
- a second gate insulating film formed on the sidewall of the second columnar semiconductor layer between the third high concentration semiconductor layer and the fourth high concentration semiconductor layer, so as to surround the second columnar semiconductor layer;
- a second gate electrode composed of the second metal film and the second semiconductor film
- a fifth insulating film formed in sidewall shape contacting the upper sidewall of the second columnar semiconductor layer and the top surface of the second gate electrode so as to surround the top region of the second columnar semiconductor layer;
- a sixth insulating film formed in a sidewall shape contacting the sidewall of the fourth insulating film and the second gate electrode so as to surround the second gate electrode and the fourth insulating film;
- first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, and
- the second gate insulating film and the second metal film are covered by the second columnar semiconductor layer, the second semiconductor film, the fourth insulating film and the fifth insulating film.
- first gate insulating film and the first metal film are formed from materials that make the first transistor enhancement-type, and
- the second gate insulating film and the second metal film to be formed from materials that make the second transistor enhancement-type.
- the thickness of the second insulating film is preferable for the thickness of the second insulating film to be thicker than the sum of the thickness of the first gate insulating film and the thickness of the first metal film.
- the semiconductor device prefferably be such that the length from the center of the first columnar semiconductor layer to the edge of the first planar semiconductor layer is larger than the sum of the length from the center to the sidewall of the first columnar semiconductor layer, the thickness of the first gate insulating film, the thickness of the first gate electrode and the thickness of the third insulating film.
- the semiconductor device prefferably:
- the first conductive type is n+ type
- the second conductive type is p+ type
- the first and second columnar semiconductor layers and the first and second planar semiconductor layers are made of silicon
- the method of producing a semiconductor device according to an aspect of the present invention is a method of producing the semiconductor device according to the present invention and includes:
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a seventh insulating film etching process for etching the seventh insulating film and leaving a sidewall shape on the sidewall of the first columnar semiconductor layer
- the semiconductor device production method according to the present invention to include:
- the method of producing a semiconductor device according to another aspect of the present invention is a method of producing the semiconductor device according to the present invention and includes:
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall in the middle region of the first columnar semiconductor layer so as to surround the first columnar semiconductor layer;
- a process for forming a second high concentration semiconductor layer of the same conductive type as the first high concentration semiconductor layer on the upper region of the first columnar semiconductor layer on the second structure by injecting a dopant at an angle of 10 degrees to 60 degrees, with a line orthogonal to the substrate being 0 degrees.
- the method of producing a semiconductor device according to a yet another aspect of the present invention is a method of producing the semiconductor device according to the present invention and includes:
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- the method of producing a semiconductor device according to a further aspect of the present invention is a method of producing the semiconductor device according to the present invention and includes:
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first gate electrode composed of the first metal film and the first semiconductor film
- a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround the top region of the first columnar semiconductor layer;
- a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film;
- the semiconductor device is provided with:
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first gate electrode composed of the first metal film and the first semiconductor film
- a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround the upper region of the first columnar semiconductor layer;
- a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film;
- the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film.
- an SGT structure uses metal in the gate electrode while controlling metal contamination, lowers the resistance of the gate, source and drain, and reduces parasitic capacitance.
- the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film.
- the metal film is etched by a mixture, such as, a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture when the metal-semiconductor compound is formed.
- a mixture such as, a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture
- the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, so the first metal film is not etched by the sulfuric acid hydrogen peroxide mixture or the ammonia hydrogen peroxide mixture when the compound of metal and semiconductor is formed.
- the first gate insulating film and the first metal film are formed only surrounding the first columnar semiconductor layer, and the first metal film is covered by a semiconductor film such as polysilicon, so when the semiconductor film is planarized using a CMP device during gate formation, it is possible to prevent metal contamination of the CMP device.
- the first gate insulating film and the first metal film are formed only surrounding the first columnar semiconductor layer, and the first metal film is covered by a semiconductor film such as polysilicon, so when the semiconductor film is etched during gate etching, it is possible to prevent metal contamination of the gate etching device.
- the first gate insulating film and the first metal film are formed only surrounding the first columnar semiconductor layer, and the first metal film is covered by a semiconductor film such as polysilicon, so when the nitride film hard mask and the nitride film sidewalls are wet etched, it is possible to prevent metal contamination of the nitride film wet etching device.
- the thickness of the second insulating film is thicker than the sum of the thickness of the first gate insulating film and the thickness of the first metal film.
- the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, so the first metal film is not etched by the sulfuric acid hydrogen peroxide mixture or the ammonia hydrogen peroxide mixture when the compound of metal and semiconductor is formed.
- the first metal film is not etched by the sulfuric acid hydrogen peroxide mixture or the ammonia hydrogen peroxide mixture when the compound of metal and semiconductor is formed.
- the length from the center of the first columnar semiconductor layer to the edge of the first planar semiconductor layer is larger than the sum of the length from the center to the sidewall of the first columnar semiconductor layer, the thickness of the first gate insulating film, the thickness of the first gate electrode and the thickness of the third insulating film.
- the first metal-semiconductor compound on the first high concentration semiconductor layer formed on the first planar semiconductor layer, and to lower the resistance of the first high concentration semiconductor layer.
- the semiconductor device is provided with a first transistor and a second transistor, wherein:
- the first transistor has:
- a first high concentration semiconductor layer of second conductive type formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a second high concentration semiconductor layer of second conductive type formed on the upper region of the first columnar semiconductor layer
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first gate electrode composed of the first metal film and the first semiconductor film
- a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround upper region of the first columnar semiconductor layer;
- a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film;
- the second transistor has:
- a third high concentration semiconductor layer of first conductive type formed on the lower region of the second columnar semiconductor layer and on the region of the second planar semiconductor layer below the second columnar semiconductor layer;
- a second gate insulating film formed on the sidewall of the second columnar semiconductor layer between the third high concentration semiconductor layer and the fourth high concentration semiconductor layer, so as to surround the second columnar semiconductor layer;
- a second gate electrode composed of the second metal film and the second semiconductor film
- a fifth insulating film formed in sidewall shape contacting the upper sidewall of the second columnar semiconductor layer and the top surface of the second gate electrode so as to surround the top region of the second columnar semiconductor layer;
- a sixth insulating film formed in a sidewall shape contacting the sidewall of the fourth insulating film and the second gate electrode so as to surround the second gate electrode and the fourth insulating film;
- first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, and
- the second gate insulating film and the second metal film are covered by the second columnar semiconductor layer, the second semiconductor film, the fourth insulating film and the fifth insulating film.
- an SGT structure uses metal in the gate electrode while controlling metal contamination, lowers the resistance of the gate, source and drain, and reduces parasitic capacitance.
- the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film.
- the metal film is etched by a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture when the metal-semiconductor compound is formed.
- the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, so the first metal film is not etched by the sulfuric acid hydrogen peroxide mixture or the ammonia hydrogen peroxide mixture when the compound of metal and semiconductor is formed.
- the second gate insulating film and the second metal film are covered by the second columnar semiconductor layer, the second semiconductor film, the fourth insulating film and the fifth insulating film. If the metal film is exposed when the metal-semiconductor compound is formed, the metal film is etched by a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture when the metal-semiconductor compound is formed.
- the second gate insulating film and the second metal film are covered by the second columnar semiconductor layer, the second semiconductor film, the fourth insulating film and the fifth insulating film, so the second metal film is not etched by the sulfuric acid hydrogen peroxide mixture or the ammonia hydrogen peroxide mixture when the metal-semiconductor compound is formed.
- a metal-semiconductor compound on the third high concentration semiconductor layer, the second gate electrode and the fourth high concentration semiconductor layer, to control depletion of the channel region by using metal in the second gate electrode, to reduce the resistance of the second gate electrode and to reduce the resistance of the gate, source and drain through a compound of metal and silicon.
- the first gate insulating film and the first metal film are formed from materials that make the first transistor enhancement-type, and
- the second gate insulating film and the second metal film are formed from materials that make the second transistor enhancement-type.
- the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, so the first metal film is not etched by the sulfuric acid hydrogen peroxide mixture or the ammonia hydrogen peroxide mixture when the compound of metal and semiconductor is formed.
- the length from the center of the first columnar semiconductor layer to the edge of the first planar semiconductor layer be larger than the sum of the length from the center to the sidewall of the first columnar semiconductor layer, the thickness of the first gate insulating film, the thickness of the first gate electrode and the thickness of the third insulating film, it is possible to form the first metal-semiconductor compound on the third high concentration semiconductor layer formed on the first planar semiconductor layer, and to lower the resistance of the third high concentration semiconductor layer.
- the semiconductor device prefferably:
- the first conductive type is n+ type
- the second conductive type is p+ type
- the first and second columnar semiconductor layers and the first and second planar semiconductor layers are made of silicon.
- the method of producing a semiconductor device according to the present invention includes:
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a seventh insulating film etching process for etching the seventh insulating film and leaving a sidewall shape on the sidewall of the first columnar semiconductor layer
- the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the hard mask.
- the high-k film is a source of metal contamination, so it is possible to control metal contamination by the first gate insulating film and the first metal film, which are sources of contamination, being covered by the first columnar semiconductor layer, the fourth semiconductor film, the first insulating film and the hard mask.
- the semiconductor device production method according to the present invention may include:
- first gate insulating film and the first metal film are formed only around the first columnar silicon layer and the first metal film is covered by polysilicon, so it is possible to reduce metal contamination of the gate etching device by etching the polysilicon during gate etching.
- the first gate insulating film and the first metal film are formed only around the columnar semiconductor layer and the first metal film is covered by the first columnar semiconductor layer and the third and fourth semiconductor films, so it is possible to reduce metal contamination of the nitride film wet etching device when wet etching the nitride film hard mask and the nitride film sidewall.
- the method of producing a semiconductor device according to the present invention includes:
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall in the middle region of the first columnar semiconductor layer so as to surround the first columnar semiconductor layer;
- a process for forming a second high concentration semiconductor layer of the same conductive type as the first high concentration semiconductor layer on the upper region of the first columnar semiconductor layer on the second structure by injecting a dopant at an angle of 10 degrees to 60 degrees, with a line orthogonal to the substrate being 0 degrees.
- the method of producing a semiconductor device according to the present invention includes:
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- the second high concentration silicon layer and the first gate electrode are separated from the first gate insulating film, to have an overlap and to minimize that overlap.
- the method of producing a semiconductor device according to the present invention includes:
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first gate electrode composed of the first metal film and the first semiconductor film
- a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround the top region of the first columnar semiconductor layer;
- a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film;
- the contact holes on the first planar semiconductor layer and the first gate wiring are formed through different processes, so it is possible to optimize etching conditions for forming the first contact hole on the first columnar semiconductor layer and etching conditions for forming the second contact hole on the first planar semiconductor layer and the third contact hole on the first gate wiring.
- FIG. 1A is a planar view of the semiconductor device according to an embodiment of the present invention.
- FIG. 1B is a cross-sectional view along line X-X′ in FIG. 1A ;
- FIG. 1C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 1A ;
- FIG. 1D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 1A ;
- FIG. 2A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 2B is a cross-sectional view along line X-X′ in FIG. 2A ;
- FIG. 2C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 2A ;
- FIG. 2D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 2A ;
- FIG. 3A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 3B is a cross-sectional view along line X-X′ in FIG. 3A ;
- FIG. 3C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 3A ;
- FIG. 3D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 3A ;
- FIG. 4A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 4B is a cross-sectional view along line X-X′ in FIG. 4A ;
- FIG. 4C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 4A ;
- FIG. 4D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 4A ;
- FIG. 5A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 5B is a cross-sectional view along line X-X′ in FIG. 5A ;
- FIG. 5C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 5A ;
- FIG. 5D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 5A ;
- FIG. 6A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 6B is a cross-sectional view along line X-X′ in FIG. 6A ;
- FIG. 6C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 6A ;
- FIG. 6D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 6A ;
- FIG. 7A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 7B is a cross-sectional view along line X-X′ in FIG. 7A ;
- FIG. 7C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 7A ;
- FIG. 7D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 7A ;
- FIG. 8A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 8B is a cross-sectional view along line X-X′ in FIG. 8A ;
- FIG. 8C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 8A ;
- FIG. 8D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 8A ;
- FIG. 9A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 9B is a cross-sectional view along line X-X′ in FIG. 9A ;
- FIG. 9C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 9A ;
- FIG. 9D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 9A ;
- FIG. 10A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 10B is a cross-sectional view along line X-X′ in FIG. 10A ;
- FIG. 10C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 10A ;
- FIG. 10D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 10A ;
- FIG. 11A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 11B is a cross-sectional view along line X-X′ in FIG. 11A ;
- FIG. 11C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 11A ;
- FIG. 11D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 11A ;
- FIG. 12A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 12B is a cross-sectional view along line X-X′ in FIG. 12A ;
- FIG. 12C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 12A ;
- FIG. 12D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 12A ;
- FIG. 13A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 13B is a cross-sectional view along line X-X′ in FIG. 13A ;
- FIG. 13C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 13A ;
- FIG. 13D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 13A ;
- FIG. 14A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 14B is a cross-sectional view along line X-X′ in FIG. 14A ;
- FIG. 14C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 14A ;
- FIG. 14D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 14A ;
- FIG. 15A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 15B is a cross-sectional view along line X-X′ in FIG. 15A ;
- FIG. 15C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 15A ;
- FIG. 15D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 15A ;
- FIG. 16A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 16B is a cross-sectional view along line X-X′ in FIG. 16A ;
- FIG. 16C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 16A ;
- FIG. 16D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 16A ;
- FIG. 17A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 17B is a cross-sectional view along line X-X′ in FIG. 17A ;
- FIG. 17C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 17A ;
- FIG. 17D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 17A ;
- FIG. 18A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 18B is a cross-sectional view along line X-X′ in FIG. 18A ;
- FIG. 18C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 18A ;
- FIG. 18D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 18A ;
- FIG. 19A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 19B is a cross-sectional view along line X-X′ in FIG. 19A ;
- FIG. 19C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 19A ;
- FIG. 19D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 19A ;
- FIG. 20A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 20B is a cross-sectional view along line X-X′ in FIG. 20A ;
- FIG. 20C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 20A ;
- FIG. 20D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 20A ;
- FIG. 21A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 21B is a cross-sectional view along line X-X′ in FIG. 21A ;
- FIG. 21C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 21A ;
- FIG. 21D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 21A ;
- FIG. 22A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 22B is a cross-sectional view along line X-X′ in FIG. 22A ;
- FIG. 22C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 22A ;
- FIG. 22D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 22A ;
- FIG. 23A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 23B is a cross-sectional view along line X-X′ in FIG. 23A ;
- FIG. 23C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 23A ;
- FIG. 23D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 23A ;
- FIG. 24A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 24B is a cross-sectional view along line X-X′ in FIG. 24A ;
- FIG. 24C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 24A ;
- FIG. 24D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 24A ;
- FIG. 25A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 25B is a cross-sectional view along line X-X′ in FIG. 25A ;
- FIG. 25C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 25A ;
- FIG. 25D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 25A ;
- FIG. 26A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 26B is a cross-sectional view along line X-X′ in FIG. 26A ;
- FIG. 26C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 26A ;
- FIG. 26D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 26A ;
- FIG. 27A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 27B is a cross-sectional view along line X-X′ in FIG. 27A ;
- FIG. 27C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 27A ;
- FIG. 27D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 27A ;
- FIG. 28A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 28B is a cross-sectional view along line X-X′ in FIG. 28A ;
- FIG. 28C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 28A ;
- FIG. 28D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 28A ;
- FIG. 29A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 29B is a cross-sectional view along line X-X′ in FIG. 29A ;
- FIG. 29C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 29A ;
- FIG. 29D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 29A ;
- FIG. 30A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 30B is a cross-sectional view along line X-X′ in FIG. 30A ;
- FIG. 30C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 30A ;
- FIG. 30D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 30A ;
- FIG. 31A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 31B is a cross-sectional view along line X-X′ in FIG. 31A ;
- FIG. 31C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 31A ;
- FIG. 31D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 31A ;
- FIG. 32A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 32B is a cross-sectional view along line X-X′ in FIG. 32A ;
- FIG. 32C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 32A ;
- FIG. 32D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 32A ;
- FIG. 33A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 33B is a cross-sectional view along line X-X′ in FIG. 33A ;
- FIG. 33C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 33A ;
- FIG. 33D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 33A ;
- FIG. 34A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 34B is a cross-sectional view along line X-X′ in FIG. 34A ;
- FIG. 34C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 34A ;
- FIG. 34D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 34A ;
- FIG. 35A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 35B is a cross-sectional view along line X-X′ in FIG. 35A ;
- FIG. 35C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 35A ;
- FIG. 35D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 35A ;
- FIG. 36A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 36B is a cross-sectional view along line X-X′ in FIG. 36A ;
- FIG. 36C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 36A ;
- FIG. 36D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 36A ;
- FIG. 37A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 37B is a cross-sectional view along line X-X′ in FIG. 37A ;
- FIG. 37C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 37A ;
- FIG. 37D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 37A ;
- FIG. 38A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 38B is a cross-sectional view along line X-X′ in FIG. 38A ;
- FIG. 38C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 38A ;
- FIG. 38D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 38A ;
- FIG. 39A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 39B is a cross-sectional view along line X-X′ in FIG. 39A ;
- FIG. 39C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 39A ;
- FIG. 39D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 39A ;
- FIG. 40A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 40B is a cross-sectional view along line X-X′ in FIG. 40A ;
- FIG. 40C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 40A ;
- FIG. 40D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 40A ;
- FIG. 41A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 41B is a cross-sectional view along line X-X′ in FIG. 41A ;
- FIG. 41C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 41A ;
- FIG. 41D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 41A ;
- FIG. 42A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 42B is a cross-sectional view along line X-X′ in FIG. 42A ;
- FIG. 42C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 42A ;
- FIG. 42D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 42A ;
- FIG. 43A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 43B is a cross-sectional view along line X-X′ in FIG. 43A ;
- FIG. 43C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 43A ;
- FIG. 43D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 43A ;
- FIG. 44A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 44B is a cross-sectional view along line X-X′ in FIG. 44A ;
- FIG. 44C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 44A ;
- FIG. 44D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 44A ;
- FIG. 45A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 45B is a cross-sectional view along line X-X′ in FIG. 45A ;
- FIG. 45C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 45A ;
- FIG. 45D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 45A ;
- FIG. 46A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 46B is a cross-sectional view along line X-X′ in FIG. 46A ;
- FIG. 46C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 46A ;
- FIG. 46D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 46A ;
- FIG. 47A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 47B is a cross-sectional view along line X-X′ in FIG. 47A ;
- FIG. 47C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 47A ;
- FIG. 47D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 47A ;
- FIG. 48A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 48B is a cross-sectional view along line X-X′ in FIG. 48A ;
- FIG. 48C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 48A ;
- FIG. 48D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 48A ;
- FIG. 49A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 49B is a cross-sectional view along line X-X′ in FIG. 49A ;
- FIG. 49C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 49A ;
- FIG. 49D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 49A ;
- FIG. 50A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 50B is a cross-sectional view along line X-X′ in FIG. 50A ;
- FIG. 50C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 50A ;
- FIG. 50D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 50A ;
- FIG. 51A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 51B is a cross-sectional view along line X-X′ in FIG. 51A ;
- FIG. 51C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 51A ;
- FIG. 51D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 51A ;
- FIG. 52A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 52B is a cross-sectional view along line X-X′ in FIG. 52A ;
- FIG. 52C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 52A ;
- FIG. 52D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 52A ;
- FIG. 53A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 53B is a cross-sectional view along line X-X′ in FIG. 53A ;
- FIG. 53C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 53A ;
- FIG. 53D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 53A ;
- FIG. 54A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 54B is a cross-sectional view along line X-X′ in FIG. 54A ;
- FIG. 54C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 54A ;
- FIG. 54D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 54A ;
- FIG. 55A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 55B is a cross-sectional view along line X-X′ in FIG. 55A ;
- FIG. 55C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 55A ;
- FIG. 55D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 55A ;
- FIG. 56A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 56B is a cross-sectional view along line X-X′ in FIG. 56A ;
- FIG. 56C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 56A ;
- FIG. 56D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 56A ;
- FIG. 57A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 57B is a cross-sectional view along line X-X′ in FIG. 57A ;
- FIG. 57C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 57A ;
- FIG. 57D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 57A ;
- FIG. 58A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 58B is a cross-sectional view along line X-X′ in FIG. 58A ;
- FIG. 58C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 58A ;
- FIG. 58D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 58A ;
- FIG. 59A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 59B is a cross-sectional view along line X-X′ in FIG. 59A ;
- FIG. 59C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 59A ;
- FIG. 59D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 59A ;
- FIG. 60A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 60B is a cross-sectional view along line X-X′ in FIG. 60A ;
- FIG. 60C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 60A ;
- FIG. 60D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 60A ;
- FIG. 61A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 61B is a cross-sectional view along line X-X′ in FIG. 61A ;
- FIG. 61C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 61A ;
- FIG. 61D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 61A ;
- FIG. 62A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 62B is a cross-sectional view along line X-X′ in FIG. 62A ;
- FIG. 62C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 62A ;
- FIG. 62D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 62A ;
- FIG. 63A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 63B is a cross-sectional view along line X-X′ in FIG. 63A ;
- FIG. 63C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 63A ;
- FIG. 63D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 63A ;
- FIG. 64A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 64B is a cross-sectional view along line X-X′ in FIG. 64A ;
- FIG. 64C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 64A ;
- FIG. 64D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 64A ;
- FIG. 65A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 65B is a cross-sectional view along line X-X′ in FIG. 65A ;
- FIG. 65C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 65A ;
- FIG. 65D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 65A ;
- FIG. 66A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 66B is a cross-sectional view along line X-X′ in FIG. 66A ;
- FIG. 66C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 66A ;
- FIG. 66D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 66A ;
- FIG. 67A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 67B is a cross-sectional view along line X-X′ in FIG. 67A ;
- FIG. 67C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 67A ;
- FIG. 67D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 67A ;
- FIG. 68A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 68B is a cross-sectional view along line X-X′ in FIG. 68A ;
- FIG. 68C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 68A ;
- FIG. 68D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 68A ;
- FIG. 69A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 69B is a cross-sectional view along line X-X′ in FIG. 69A ;
- FIG. 69C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 69A ;
- FIG. 69D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 69A ;
- FIG. 70A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 70B is a cross-sectional view along line X-X′ in FIG. 70A ;
- FIG. 70C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 70A ;
- FIG. 70D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 70A ;
- FIG. 71A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 71B is a cross-sectional view along line X-X′ in FIG. 71A ;
- FIG. 71C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 71A ;
- FIG. 71D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 71A ;
- FIG. 72A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 72B is a cross-sectional view along line X-X′ in FIG. 72A ;
- FIG. 72C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 72A ;
- FIG. 72D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 72A ;
- FIG. 73A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 73B is a cross-sectional view along line X-X′ in FIG. 73A ;
- FIG. 73C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 73A ;
- FIG. 73D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 73A ;
- FIG. 74A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 74B is a cross-sectional view along line X-X′ in FIG. 74A ;
- FIG. 74C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 74A ;
- FIG. 74D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 74A ;
- FIG. 75A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 75B is a cross-sectional view along line X-X′ in FIG. 75A ;
- FIG. 75C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 75A ;
- FIG. 75D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 75A ;
- FIG. 76A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 76B is a cross-sectional view along line X-X′ in FIG. 76A ;
- FIG. 76C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 76A ;
- FIG. 76D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 76A ;
- FIG. 77A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 77B is a cross-sectional view along line X-X′ in FIG. 77A ;
- FIG. 77C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 77A ;
- FIG. 77D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 77A ;
- FIG. 78A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 78B is a cross-sectional view along line X-X′ in FIG. 78A ;
- FIG. 78C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 78A ;
- FIG. 78D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 78A ;
- FIG. 79A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 79B is a cross-sectional view along line X-X′ in FIG. 79A ;
- FIG. 79C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 79A ;
- FIG. 79D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 79A ;
- FIG. 80A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 80B is a cross-sectional view along line X-X′ in FIG. 80A ;
- FIG. 80C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 80A ;
- FIG. 80D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 80A ;
- FIG. 81A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 81B is a cross-sectional view along line X-X′ in FIG. 81A ;
- FIG. 81C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 81A ;
- FIG. 81D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 81A ;
- FIG. 82A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 82B is a cross-sectional view along line X-X′ in FIG. 82A ;
- FIG. 82C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 82A ;
- FIG. 82D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 82A ;
- FIG. 83A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 83B is a cross-sectional view along line X-X′ in FIG. 83A ;
- FIG. 83C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 83A ;
- FIG. 83D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 83A ;
- FIG. 84A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention
- FIG. 84B is a cross-sectional view along line X-X′ in FIG. 84A ;
- FIG. 84C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 84A ;
- FIG. 84D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 84A ;
- FIG. 85A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 85B is a cross-sectional view along line X-X′ in FIG. 85A ;
- FIG. 85C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 85A ;
- FIG. 85D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 85A ;
- FIG. 86A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 86B is a cross-sectional view along line X-X′ in FIG. 86A ;
- FIG. 86C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 86A ;
- FIG. 86D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 86A ;
- FIG. 87A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 87B is a cross-sectional view along line X-X′ in FIG. 87A ;
- FIG. 87C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 87A ;
- FIG. 87D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 87A ;
- FIG. 88A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention.
- FIG. 88B is a cross-sectional view along line X-X′ in FIG. 88A ;
- FIG. 88C is a cross-sectional view along line Y 1 -Y 1 ′ in FIG. 88A ;
- FIG. 88D is a cross-sectional view along line Y 2 -Y 2 ′ in FIG. 88A ;
- FIG. 1C shows an SGT 220 according to a first embodiment of the present invention.
- This SGT 220 is an nMOS SGT and is provided with a first planar silicon layer 234 and a first columnar silicon layer 232 formed on top of the first planar silicon layer 234 .
- a first n+ type silicon layer 113 is formed on the lower region of the first columnar silicon layer 232 and the region of the first planar silicon layer 234 positioned below the first columnar silicon layer 232 , and a second n+ type silicon layer 157 is formed on the upper region of the first columnar silicon layer 232 .
- the first n+ type silicon layer 113 functions as a source scattering layer and the second n+ type silicon layer 157 functions as a drain scattering layer.
- the area between the source scattering layer and the drawing scattering layer functions as a channel region.
- the first columnar silicon layer 232 between the first n+ type silicon layer 113 and the second n+ type silicon layer 157 functioning as this channel region is called a first silicon layer 114 .
- a gate insulating film 140 is formed surrounding the first columnar silicon layer 232 functioning as the channel region.
- the gate insulating film 140 may be, for example, an oxide film, a nitride film or a high-k film.
- a first metal film 138 is formed surrounding this gate insulating film 140 .
- the first metal film 138 may be, for example, titanium, titanium nitride, tantalum or tantalum nitride.
- First polysilicon films 136 and 152 are formed surrounding this first metal film 138 .
- the first metal film 138 and the first polysilicon films 136 and 152 constitute a first gate electrode 236 .
- a channel is formed in the first silicon layer 114 by impressing a voltage on the first gate electrode 236 during operation.
- a first metal-silicon compound 172 , a third metal-silicon compound 170 and a second metal-silicon compound 171 are formed on the first n+ type silicon layer 113 , the gate electrode 236 and the second n+ type silicon layer 157 , respectively.
- the metal comprising the metal-silicon compounds Ni or Co may be used, for example.
- the first n+ type silicon layer 113 , the gate electrode 236 and the second n+ type silicon layer 157 are connected to below-described contacts. Through this, the resistances of the gate, source and drain are lowered.
- the first n+ type silicon layer 113 is connected to a contact 230 via the first metal-silicon compound 172 .
- the contact 230 is formed from a barrier metal layer 189 and metal layers 194 and 199 .
- the contact 230 is further connected to a power source wire 225 .
- the power source wire 225 is composed of a barrier metal layer 216 , a metal layer 217 and a barrier metal layer 218 .
- the second n+ type silicon layer 157 is connected to a contact 229 via the second metal-silicon compound 171 .
- the contact 229 is composed of a barrier metal layer 188 and metal layers 193 and 198 .
- the contact 229 is further connected to an output wire 223 .
- the output wire 223 is composed of a barrier metal layer 213 , a metal 214 and a barrier metal layer 215 .
- a first insulating film 129 is formed between the first gate electrode 236 and the first planar silicon layer 234 , a second insulating film 162 is formed in a sidewall shape on the upper sidewall of the first columnar silicon layer 232 and above the first gate electrode 236 , and a third insulating film 164 is formed in a sidewall shape on the sidewall of the first gate electrode 236 and the first insulating film 129 .
- the first insulating film 129 is preferably a low-k insulating film such as SiOF, SiOH or the like, for example.
- the second insulating film 162 and the third insulating film 164 are oxide films, nitride films or high-k films, for example.
- the parasitic capacitance between the gate electrode and the planar silicon layer is reduced by the first insulating film 129 .
- the thickness of the second insulating film 162 is preferably thicker than the sum of the thickness of the first gate insulating film 140 and the thickness of the first metal film 138 .
- the first gate insulating film 140 and the first metal film 138 are covered by the first columnar silicon layer 232 , the first polysilicon films 136 and 152 , the first insulating film 129 and the second insulating film 162 .
- the entirety of the first metal film 138 is protected, so this film is not etched by a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture when forming the metal-silicon compound.
- the length from the center of the first columnar silicon layer 232 to the end of the first planar silicon layer 234 in the nMOS SGT according to the present embodiment is preferably larger than the sum of the length from the center to the sidewall of the first columnar silicon layer 232 , the thickness of the first gate insulating film 140 , the thickness of the first gate electrode 236 formed by the first metal film 138 and the first polysilicon films 136 and 152 and the thickness of the third insulating film 164 .
- an example was shown of a single columnar semiconductor layer, but in the second embodiment, an example is shown of a circuit composed of multiple columnar semiconductor layers.
- An inverter according to the second embodiment is provided with a pMOS SGT and an nMOS SGT.
- the nMOS SGT 220 is provided with a first planar silicon layer 234 and a first columnar silicon layer 232 formed on top of the first planar silicon layer 234 .
- a first n+ type silicon layer 113 is formed on the lower region of the first columnar silicon layer 232 and the region of the first planar silicon layer 234 positioned below the first columnar silicon layer 232 , and a second n+ type silicon layer 157 is formed on the upper region of the first columnar silicon layer 232 .
- the first n+ type silicon layer 113 functions as a source scattering layer and the second n+ type silicon layer 157 functions as a drain scattering layer.
- the area between the source scattering layer and the drawing scattering layer functions as a channel region.
- the first columnar silicon layer 232 between the first n+ type silicon layer 113 and the second n+type silicon layer 157 functioning as this channel region is called a first silicon layer 114 .
- a first gate insulating film 140 is formed surrounding the first columnar silicon layer 232 functioning as the channel region.
- the gate insulating film 140 may be, for example, an oxide film, a nitride film or a high-k film.
- a first metal film 138 is formed surrounding this first gate insulating film 140 .
- the first metal film 138 may be, for example, titanium, titanium nitride, tantalum or tantalum nitride.
- First polysilicon films 136 and 152 are formed surrounding this first metal film 138 .
- the first metal film 138 and the first polysilicon films 136 and 152 constitute a first gate electrode 236 .
- a channel is formed in the first silicon layer 114 by impressing a voltage on the first gate electrode 236 during operation.
- a first metal-silicon compound 172 , a third metal-silicon compound 170 and a second metal-silicon compound 171 are formed on the first n+ type silicon layer 113 , the first gate electrode 236 and the second n+ type silicon layer 157 , respectively.
- the metal comprising the metal-silicon compounds may be Ni or Co, for example.
- the first n+ type silicon layer 113 , the gate electrode 236 and the second n+ type silicon layer 157 are connected to below-described contacts. Through this, the resistances of the gate, source and drain are lowered.
- a first insulating film 129 is formed between the first gate electrode 236 and the first planar silicon layer 234 , a second insulating film 162 is formed in a sidewall shape on the upper sidewall of the first columnar silicon layer 232 and above the first gate electrode 236 , and a third insulating film 164 is formed in a sidewall shape on the sidewall of the first gate electrode 236 and the first insulating film 129 .
- the first insulating film 129 is preferably a low-k insulating film such as SiOF, SiOH or the like, for example.
- the second insulating film 162 and the third insulating film 164 are oxide films, nitride films or high-k films, for example.
- the parasitic capacitance between the gate electrode and the planar silicon layer is reduced by the first insulating film 129 .
- the pMOS SGT 219 and is provided with a second planar silicon layer 233 and a second columnar silicon layer 231 formed on top of the second planar silicon layer 233 .
- a first p+ type silicon layer 119 is formed on the lower region of the second columnar silicon layer 231 and the region of the second planar silicon layer 233 positioned below the second columnar silicon layer 231 , and a second p+ type silicon layer 159 is formed on the upper region of the second columnar silicon layer 231 .
- the first p+ type silicon layer 119 for example, functions as a source scattering layer and the second p+ type silicon layer 159 functions as a drain scattering layer.
- the area between the source scattering layer and the drawing scattering layer functions as a channel region.
- the second columnar silicon layer 231 between the first p+ type silicon layer 119 and the second p+ type silicon layer 159 functioning as this channel region is called a second silicon layer 120 .
- a second gate insulating film 139 is formed surrounding the second columnar silicon layer 231 functioning as the channel region.
- the second gate insulating film 139 may be, for example, an oxide film, a nitride film or a high-k film.
- a second metal film 137 is formed surrounding this second gate insulating film 139 .
- the second metal film 137 may be, for example, titanium, titanium nitride, tantalum or tantalum nitride.
- Second polysilicon films 135 and 151 are formed surrounding this second metal film 137 .
- the second metal film 137 and the second polysilicon films 135 and 151 constitute a second gate electrode 235 .
- a channel is formed in the second silicon layer 120 by impressing a voltage on the second gate electrode 235 during operation.
- a fourth metal-silicon compound 168 , a fifth metal-silicon compound 170 and a sixth metal-silicon compound 169 are respectively formed on the first p+ type silicon layer 119 , the second gate electrode 235 and the second p+type silicon layer 159 .
- the metal comprising the metal-silicon compounds Ni or Co may be used, for example.
- the first p+ type silicon layer 119 , the second gate electrode 235 and the second p+ type silicon layer 159 are connected to below-described contacts. Through this, the resistances of the gate, source and drain are lowered.
- a fourth insulating film 129 is formed between the second gate electrode 235 and the second planar silicon layer 233 , a fifth insulating film 161 is formed in a sidewall shape on the upper sidewall of the second columnar silicon layer 231 and above the second gate electrode 235 , and a sixth insulating film 164 is formed in a sidewall shape on the sidewall of the second gate electrode 235 and the fourth insulating film 129 .
- the fourth insulating film 129 is preferably a low-k insulating film such as SiOF, SiOH or the like, for example.
- the parasitic capacitance between the gate electrode and the planar silicon layer is reduced by the fourth insulating film 129 .
- the first n+ type silicon layer 113 is connected to a contact 230 via the first metal-silicon compound 172 .
- the contact 230 is formed from a barrier metal layer 189 and metal layers 194 and 199 .
- the contact 230 is further connected to a power source wire 225 .
- the power source wire 225 is composed of a barrier metal layer 216 , a metal layer 217 and a barrier metal layer 218 .
- the second n+ type silicon layer 157 is connected to a contact 229 via the second metal-silicon compound 171 .
- the contact 229 is composed of a barrier metal layer 188 and metal layers 193 and 198 .
- the contact 229 is further connected to an output wire 223 .
- the output wire 223 is composed of a barrier metal layer 213 , a metal layer 214 and a barrier metal layer 215 .
- the first gate electrode 236 is connected to a contact 228 via the third metal-silicon compound 170 and the second gate electrode 235 is connected to the contact 228 via the fifth metal-silicon compound 170 .
- the contact 228 is composed of a barrier metal layer 187 and metal layers 192 and 197 .
- the contact 228 is further connected to an input wire 224 .
- the input wire 224 is composed of a barrier metal layer 213 , a metal layer 214 and a barrier metal layer 215 .
- the first p+ type silicon layer 119 is connected to a contact 226 via the fourth metal-silicon compound 168 .
- the contact 226 is formed from a barrier metal layer 185 and metal layers 190 and 195 .
- the contact 226 is further connected to a power source wire 222 .
- the power source wire 222 is composed of a barrier metal layer 207 , a metal layer 208 and a barrier metal layer 209 .
- the second p+ type silicon layer 159 is connected to a contact 227 via the sixth metal-silicon compound 169 .
- the contact 227 is composed of a barrier metal layer 186 and metal layers 191 and 196 .
- the contact 227 is further connected to an output wire 223 .
- the output wire 223 is composed of a barrier metal layer 213 , a metal layer 214 and a barrier metal layer 215 .
- an inverter circuit is composed from the pMOS SGT 219 and the nMOS SGT 220 .
- the first gate insulating film 140 and the first metal film 138 are preferably materials that make the nMOS SGT 220 enhancement-type
- the second gate insulating film 139 and the second metal film 137 are preferably materials that make the pMOS SGT 219 enhancement-type.
- the penetrating current that flows during operation of this inverter composed of the nMOS SGT 220 and the pMOS SGT 219 can thus be reduced.
- the thickness of the second insulating film 162 is preferably thicker than the sum of the thickness of the first gate insulating film 140 and the thickness of the first metal film 138 .
- the first gate insulating film 140 and the first metal film 138 are covered by the first columnar silicon layer 232 , the first polysilicon films 136 and 152 , the first insulating film 129 and the second insulating film 162 .
- the first metal film 138 is protected in its entirety and thus is not etched by a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture when the metal-semiconductor compound is formed.
- the thickness of the second insulating film 161 is preferably thicker than the sum of the thickness of the second gate insulating film 139 and the thickness of the second metal film 137 .
- the second gate insulating film 139 and the second metal film 137 are covered by the second columnar silicon layer 231 , the second polysilicon films 135 and 151 , the fourth insulating film 129 and the fifth insulating film 161 .
- the second metal film 137 is protected in its entirety and thus is not etched by a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture when the metal-semiconductor compound is formed.
- the length from the center of the first columnar silicon layer 232 to the end of the first planar silicon layer 234 is preferably larger than the sum of the length from the center to the sidewall of the first columnar silicon layer 232 , the thickness of the first gate insulating film 140 , the thickness of the first gate electrode 236 and the thickness of the third insulating film 164 .
- the first metal-silicon compound 172 can be formed on the n+ type silicon layer 113 without adding any special manufacturing processes.
- the length from the center of the second columnar silicon layer 231 to the end of the second planar silicon layer 233 is preferably larger than the sum of the length from the center to the sidewall of the second columnar silicon layer 231 , the thickness of the second gate insulating film 139 , the thickness of the first gate electrode 235 and the thickness of the sixth insulating film 164 .
- the fourth metal-silicon compound 168 can be formed on the p+ type silicon layer 119 without adding any special manufacturing processes.
- FIGS. 2A through 88D the same constituent elements are labeled with the same reference numbers.
- FIGS. 2A through 88D show an example of producing an SGT according to the present invention.
- part A shows a planar view
- part B shows a cross-sectional view along line X-X′
- part C shows a cross-sectional view along line Y 1 -Y 1 ′
- part D shows a cross-sectional view along line Y 2 -Y 2 ′.
- a nitride film 103 is formed on a substrate composed of a silicon oxide film 101 and a silicon layer 102 .
- the substrate may also be composed of silicon.
- an oxide film may be formed on the silicon layer and another silicon layer may be formed on the oxide film.
- an i-type silicon layer is used as the silicon layer 102 .
- dopants are introduced into the part that becomes the channel of the SGT.
- a thin n-type silicon layer or a thin p-type silicon layer may be used in place of the i-type silicon layer.
- resists 104 and 105 for forming a hard mask for a columnar silicon layer are formed on the nitride film 103 , as shown in FIGS. 3A to 3D .
- the nitride film 103 is etched and hard masks 106 and 107 are formed, as shown in FIGS. 4A to 4D .
- the silicon layer 102 is etched and columnar silicon layers 231 and 232 are formed, as shown in FIGS. 5A to 5D .
- the surface of the silicon layer 102 is oxidized and a sacrificial oxide film 108 is formed, as shown in FIGS. 7A to 7D .
- a sacrificial oxide film 108 is formed, as shown in FIGS. 7A to 7D .
- the sacrificial oxide film 108 is removed through etching to form the shape shown in FIGS. 8A to 8D .
- An oxide film 109 is formed on the surface of the silicon layer 102 and the hard masks 106 and 107 , as shown in FIGS. 9A to 9D .
- the oxide film 109 is etched and left in sidewall shape on the sidewall of the columnar silicon layers 231 and 232 to form sidewalls 110 and 111 , as shown in FIGS. 10A to 10D .
- these sidewalls 110 and 111 prevent dopants from entering the channel, making it possible to control fluctuations in the threshold voltage of the SGT.
- a resist 112 for injecting dopants into the bottom of the columnar silicon layer 232 is formed surrounding the columnar silicon layer 231 , as shown in FIGS. 11A to 11D .
- arsenic for example, is injected into the silicon layer 102 in the region where the nMOS SGT is to be formed, thereby forming an n+ type silicon layer 113 surrounding the bottom of the columnar silicon layer 232 .
- the part of the silicon layer 102 covered by the hard mask 107 and the sidewall 111 does not become the n+ type silicon layer, comprising instead a first silicon layer 114 region in the columnar silicon layer 232 .
- the resist 112 is removed. Conditions on the substrate following removal are shown in FIGS. 13A to 13D .
- the sidewalls 110 and 111 are removed through etching. Conditions on the substrate following etching are shown in FIGS. 14A to 14D .
- Annealing is accomplished and the injected dopants, here arsenic, are activated. Through this, the injected dopants are scattered to the bottom of the columnar silicon layer 232 , as shown in FIGS. 15A to 15D . Through this, even the bottom of the columnar silicon layer 231 becomes an n+ type silicon layer and forms a portion of the n+ type silicon layer 113 .
- An oxide film 115 is formed on the silicon layer 102 , the hard masks 106 and 107 and the n+ type silicon layer 113 , as shown in FIGS. 16A to 16D .
- the oxide film 115 is etched, leaving behind a sidewall shape in the sidewall of the columnar silicon layers 231 and 232 to form sidewalls 116 and 117 , as shown in FIGS. 17A to 17D .
- these sidewalls prevent dopants from entering the channel, making it possible to control fluctuations in the threshold voltage of the SGT.
- a resist 118 is formed surrounding the columnar silicon layer 231 in order to inject dopants into the bottom of the columnar silicon layer 232 , as shown in FIGS. 18A to 18D .
- boron for example, is injected into the silicon layer 102 in the region where the pMOS SGT is to be formed, thereby forming a p+ type silicon layer 119 surrounding the bottom of the columnar silicon layer 231 .
- the part of the silicon layer 102 covered by the hard mask 106 and the sidewall 116 does not become the p+ type silicon layer, comprising instead a second silicon layer 120 region in the columnar silicon layer 231 .
- the resist 118 is removed. Conditions on the substrate following removal are shown in FIGS. 20A to 20D .
- the sidewalls 116 and 117 are removed through etching. Conditions on the substrate following etching are shown in FIGS. 21A to 21D .
- Annealing is accomplished and the injected dopant, here boron, is activated. Through this, the injected dopant is scattered to the bottom of the columnar silicon layer 231 , as shown in FIGS. 22A to 22D . Through this, even the bottom of the columnar silicon layer 231 becomes a p+ type silicon layer and forms a portion of the p+ type silicon layer 119 .
- An oxide film 121 is formed on the surface of the hard masks 106 and 107 , the n+ type silicon layer 113 and the p+ type silicon layer 119 , as shown in FIGS. 23A to 23D .
- This oxide film 121 protects the first silicon layer 114 and the second silicon layer 120 from resist for forming a planar silicon layer later.
- Resists 122 and 123 for forming a planar silicon layer are formed.
- the resists 122 and 123 are formed so as to cover the second silicon layer 120 and the area surrounding the bottom thereof, and the first silicon layer 114 and the area surrounding the bottom thereof, respectively, as shown in FIGS. 24A to 24D .
- the oxide film 121 is etched and partitioned into oxide films 124 and 125 , as shown in FIGS. 25A to 25D .
- planar silicon layers 233 and 234 are etched to form planar silicon layers 233 and 234 , as shown in FIGS. 26A and 26D .
- the planar silicon layer 233 is the planar portion of the p+ type silicon layer 119 arranged surrounding the area immediately below the second silicon layer 120 .
- the planar silicon layer 234 is the planar portion of the n+ type silicon layer 113 arranged surrounding the area immediately below the first silicon layer 114 .
- the resists 122 and 123 are removed. Conditions on the substrate following removal are shown in FIGS. 27A to 27D .
- An oxide film 123 is formed on the surface of the resists 122 and 123 and the planar silicon layers 233 and 244 , as shown in FIGS. 28A to 28D .
- CMP Chemical Mechanical Polishing
- the oxide films 126 , 124 and 125 are etched to form an oxide film 126 buried between the planar silicon layers 119 and 133 , as shown in FIGS. 30A to 30D .
- An oxide film 128 is formed on the result of the above processes. At this time, the oxide film 128 is formed thickly on the n+ type silicon layer 113 , the p+ type silicon layer 119 , the oxide film 126 and the hard masks 106 and 107 , and the oxide film 128 is formed thinly on the sidewalls of the columnar silicon layers 231 and 232 , as shown in FIGS. 31A to 31D .
- the oxide film 128 formed on the sidewalls of the columnar silicon layers 231 and 232 is removed through etching.
- the etching is preferably isotropic etching.
- the oxide film 128 is formed thickly on the n+ type silicon layer 113 , the p+ type silicon layer 119 , the oxide film 126 and the hard masks 106 and 107 and the oxide film 128 is formed thinly on the sidewalls of the columnar silicon layers 213 and 232 , and consequently, the oxide film 128 remains on the n+ type silicon layer 113 , the p+ type silicon layer 119 and the oxide film 126 , forming an insulating film 129 , as shown in FIGS. 32A to 32D .
- oxide films 130 and 131 remain on the hard masks 106 and 107 as well.
- the insulating film 129 By means of the insulating film 129 , it is possible to reduce the parasitic capacitance between the gate electrode and the planar silicon layer.
- a gate insulating film 132 is formed so as to cover at least the first silicon layer 114 and the surface of the surroundings of the bottom thereof and the second silicon layer 120 and the surface of the surroundings of the bottom thereof, as shown in FIGS. 33A to 33D .
- the gate insulating film 132 is a film containing at least one out of an oxide film, a nitride film and a high-k film.
- hydrogen atmosphere annealing or epitaxial growth may be accomplished on the columnar silicon layers 231 and 232 .
- a metal film 133 is formed on the surface of the gate insulating film 132 , as shown in FIGS. 34A to 34D .
- the metal film is preferably a film containing titanium, titanium nitride, tantalum or tantalum nitride.
- a polysilicon film 134 is formed on the surface of the metal film 133 , as shown in FIGS. 35A to 35D .
- the polysilicon film 134 is etched to form polysilicon films 135 and 136 remaining in sidewall shape, as shown in FIGS. 36A to 36D .
- the metal film 133 is etched.
- the metal film on the sidewalls of the columnar silicon layers 231 and 232 is protected by the polysilicon films 135 and 136 and thus is not etched, and becomes the metal films 137 and 138 remaining in sidewall shape, as shown in FIGS. 37A to 37D .
- the gate insulating film 132 is etched.
- the gate insulating film on the sidewalls of the columnar silicon layers 231 and 232 is protected by the polysilicon films 135 and 136 and thus is not etched, and becomes the gate insulating film 140 remaining in sidewall shape, as shown in FIGS. 38A to 38D .
- a polysilicon film 141 is formed on the surface where circuits are formed, as shown in FIGS. 39A to 39D .
- the polysilicon film 141 is preferably formed using normal-pressure CVD.
- this high-k film can be the source of metal contamination.
- the gate insulating film 139 and the metal film 137 are covered by the columnar silicon layer 231 , the polysilicon films 135 and 141 , the insulating film 129 and the hard mask 106 .
- the gate insulating film 140 and the metal film 138 are covered by the columnar silicon layer 232 , the polysilicon films 136 and 141 , the insulating film 129 and the hard mask 107 .
- the gate insulating films 139 and 140 and the metal films 137 and 138 which are all sources of contamination, are covered by the columnar silicon layers 231 and 232 , the polysilicon layers 135 , 136 and 141 , the insulating film 129 and the hard masks 106 and 107 , so it is possible to control metal contamination by metal contained in the gate insulating films 139 and 140 and the metal films 137 and 138 .
- etching is accomplished to leave a sidewall shape and the gate insulating film is etched, following which a polysilicon film is formed and the gate insulating film and the metal film are covered by the columnar silicon layer, the polysilicon layer, the insulating film and the hard mask.
- a polysilicon film 142 is formed on the surface where the circuits are formed, as shown in FIGS. 40A to 40D .
- the polysilicon film is preferably formed using low-pressure CVD.
- the gate insulating film and the metal film that are the source of contamination are covered by the columnar silicon layers 231 and 232 , the polysilicon layers 135 , 136 and 141 , the insulating film 129 and the hard masks 106 and 107 , so it is possible to use low-pressure CVD.
- CMP chemical mechanical polishing
- the oxide films 130 and 131 are removed through etching. Conditions on the substrate following etching are shown in FIGS. 42A to 42D
- the polysilicon film 142 is etched and the polysilicon film 142 is removed to the top edge of the region where the gate electrode and the gate insulating films 139 and 140 are to be formed, as shown in FIGS. 43A to 43D . Through this etching, the gate length of the SGT is determined.
- the metal films 137 and 138 on the upper sidewalls of the columnar silicon layers 231 and 232 are removed through etching. Conditions on the substrate following etching are shown in FIGS. 44A to 44D .
- the gate insulating films 139 and 140 on the upper sidewalls of the columnar silicon layers 231 and 232 are removed through etching. Conditions on the substrate following etching are shown in FIGS. 45A to 45D
- An oxide film 144 is formed on the surface where the circuits are formed, as shown in FIGS. 46A to 46D . Because the gate electrode top surface is protected by this oxide film 144 from the wet treatment or dry treatment accomplished in later processes, it is possible to control fluctuations in gate length, that is to say variance in gate length, and damage to the gate insulating films 139 and 140 and the metal films 137 and 138 from the gate electrode top surface.
- a nitride film 145 is formed on the surface of the oxide film 144 , as shown in FIGS. 47A to 47D .
- the nitride film 145 and the oxide film 144 are etched to form the oxide films 148 and 149 and the nitride films 146 and 147 remaining in a sidewall shape, as shown in FIGS. 48A to 48D .
- the sum of the film thicknesses of the oxide film 148 and the nitride film 146 remaining in sidewall shape is the film thickness of the gate electrode 235 later, and the film thickness of the oxide film 149 and the nitride film 147 remaining in sidewall shape is the film thickness of the gate electrode 236 later, so by adjusting the film formation thicknesses and etching conditions of the oxide film 144 and the nitride film 145 , it is possible to form a gate electrode of the desired film thickness.
- the sum of the radius of the columnar silicon layer 231 and the sum of the film thicknesses of the oxide film 148 and the nitride film 146 remaining in sidewall shape is greater than the radius of the outer circumference of the cylinder composed by the gate insulating film 139 and the metal film 137 , and for the sum of the radius of the columnar silicon layer 232 and the sum of the film thicknesses of the oxide film 149 and the nitride film 147 remaining in sidewall shape to be larger than the diameter of the outer circumference of the cylinder composed by the gate insulating film 140 and the metal film 138 .
- the metal films 137 and 138 are covered by the polysilicon film after gate etching, it is possible to control metal contamination.
- a resist 150 for forming a gate wire 221 is formed on the polysilicon layer 142 at least between the first silicon layer 114 and the second silicon layer 120 , as shown in FIGS. 49A to 49D .
- the polysilicon films 142 , 141 , 135 and 136 are etched to form gate electrodes 235 and 236 and the gate wire 221 , as shown in FIGS. 50A to 50D .
- the gate electrode 235 is composed of the metal film 137 and the polysilicon films 135 and 151
- the gate electrode 236 is composed of the metal film 138 and the polysilicon films 136 and 152 .
- the gate wire 221 connecting the gate electrodes 235 and 236 is composed of the polysilicon films 135 , 151 , 142 , 152 and 136 .
- the insulating film 129 is etched and the surfaces of the p+ type silicon layer 119 and the n+ type silicon layer 113 are exposed, as shown in FIGS. 51A to 51D .
- the resist 150 is removed. Conditions on the substrate following removal are shown in FIGS. 52A to 52D .
- Oxidation is accomplished to form oxide films 153 , 154 and 155 , as shown in FIGS. 53A to 53D .
- the p+ type silicon layer 159 , the n+ type silicon layer 157 , the gate electrodes 235 and 236 and the gate wire 221 are protected by these nitride films from etching through wet treatment or dry treatment during etching of the hard masks 106 and 107 and the nitride films 146 and 147 performed later.
- the hard masks 106 and 107 and the nitride films 146 and 147 are removed by etching through a wet treatment or dry treatment. Conditions on the substrate following etching are shown in FIGS. 54A to 54D . Because the top surface of the gate electrodes is protected from the wet treatment or dry treatment by the oxide films 148 and 149 , it is possible to control fluctuations in gate length, that is to say variances in gate length, and to control damage to the gate insulating films 139 and 140 and the metal films 137 and 138 from the top surface of the gate electrode.
- the gate insulating films 139 and 140 and metal films 137 and 138 are covered by the polysilicon 135 , 136 , 151 and 152 , the nitride films 148 and 149 , the columnar silicon layers 231 and 232 and the insulating film 129 , so metal contamination of the nitride film wet etching device is controlled.
- the oxide films 148 , 149 , 153 , 154 and 155 are removed by etching. Conditions on the substrate following etching are shown in FIGS. 55A to 55D .
- a resist 156 for forming an n+ type silicon layer on the columnar silicon layer 232 through dopant injection is formed surrounding the columnar silicon layer 231 , as shown in FIGS. 56A to 56D .
- a thin oxide film may be formed as a through (?) oxide film for dopant injection.
- arsenic for example, is injected into the top of the columnar silicon layer 232 to form an n+ type silicon layer 157 .
- the angle of injecting the arsenic is preferably 10 degrees to 60 degrees, and more preferably the large angle of 60 degrees, where a line orthogonal to the substrate is taken as 0 degrees.
- the resist 156 is removed. Conditions on the substrate following removal are shown in FIGS. 58A to 58D .
- Heat treatment is accomplished and the arsenic is activated. Conditions on the substrate following activation is shown in FIGS. 59A to 59D .
- a resist 158 for forming a p+ type silicon layer on the upper part of the columnar silicon layer 231 through dopant injection is formed surrounding the columnar silicon layer 232 , as shown by FIGS. 60A to 60D .
- boron for example, is injected into the upper part of the columnar silicon layer 231 to form a p+ type silicon layer 159 .
- the angle of injecting the boron is preferably 10 degrees to 60 degrees, and more preferably the large angle of 60 degrees, where a line orthogonal to the substrate is taken as 0 degrees.
- the resist 158 is removed. Conditions on the substrate following removal are shown in FIGS. 62A to 62D .
- Heat treatment is accomplished and the boron is activated. Conditions on the substrate following activation is shown in FIGS. 63A to 63D .
- a nitride film 160 is formed on the surface where the circuits are formed, as shown in FIGS. 64A to 64D .
- the nitride film 160 is etched to form an insulating film 161 composed of nitride film formed in a sidewall shape on the upper sidewall of the columnar silicon layer 231 and the upper part of the gate electrode 235 , an insulating film 162 composed of a nitride film formed in a sidewall shape on the upper sidewall of the columnar silicon layer 232 and the upper part of the gate electrode 236 , an insulating film 164 composed of a nitride film formed in a sidewall shape on the sidewalls of the insulating film 129 and the gate electrodes 235 and 236 , an insulating film 163 composed of a nitride film formed in a sidewall shape on the sidewall of the p+ type silicon layer 119 and an insulating film 165 composed of a nitride film formed in a sidewall shape on the sidewall of the n+ type silicon layer 113 , as shown in FIGS. 65A to 65D .
- the gate insulating film 140 and the metal film 138 are covered by the columnar silicon layer 232 , the polysilicon layers 136 and 152 , the insulating film 129 and the insulating film 162 , and in addition, the gate insulating film 129 and the metal film 137 are covered by the columnar silicon layer 231 , the polysilicon layers 135 and 151 , the insulating film 129 and the insulating film 161 .
- a resist 166 for forming a deep n+ type silicon layer in the direction orthogonal to the substrate on the upper part of the columnar silicon layer 232 through dopant injection is formed surrounding the columnar silicon layer 231 , as shown in FIGS. 66A to 66D .
- By making this an n+ type silicon layer deep in the direction orthogonal to the substrate it is possible to form a metal-silicon compound later on the n+ type silicon layer. If this were an n+ type silicon layer shallow in the direction orthogonal to the substrate, the metal-silicon compound formed later would be formed on the n+ type silicon layer and the first silicon layer and would become a source of leak current.
- arsenic for example, is injected into the upper part of the columnar silicon layer 232 and the n+ type silicon layer 157 is made deep in the direction orthogonal to the substrate.
- the angle of injecting the arsenic is preferably a low angle of 0 degrees to 7 degrees, where the line orthogonal to the substrate is taken to be 0 degrees.
- the resist 166 is removed. Conditions on the substrate following removal are shown in FIGS. 68A to 68D .
- a resist 167 for forming a deep p+ type silicon layer in the direction orthogonal to the substrate on the upper part of the columnar silicon layer 231 through dopant injection is formed surrounding the columnar silicon layer 232 , as shown in FIGS. 69A to 69D .
- This a p+ type silicon layer deep in the direction orthogonal to the substrate, it is possible to form a metal-silicon compound later on the p+ type silicon layer. If this were a p+ type silicon layer shallow in the direction orthogonal to the substrate, the metal-silicon compound formed later would be formed on the p+ type silicon layer and the second silicon layer and would become a source of leak current.
- boron for example, is injected into the upper part of the columnar silicon layer 231 and the p+ type silicon layer 159 is made deep in the direction orthogonal to the substrate.
- the angle of injecting the boron is preferably a low angle of 0 degrees to 7 degrees, where the line orthogonal to the substrate is taken to be 0 degrees.
- the resist 167 is removed. Conditions on the substrate following removal are shown in FIGS. 71A to 71D .
- Heat treatment is accomplished in order to activate the dopant. Conditions following activation are shown in FIGS. 72A to 72D .
- a metal-silicon compound is formed on the surface of the p+ type silicon layer 119 , the p+ type silicon layer 159 , the gate electrode 235 , the n+ type silicon layer 113 , the n+ type silicon layer 157 and the gate electrode 236 , and by removing the unreacted metal film using a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture, a metal-silicon compound 168 is formed on the surface of the p+ type silicon layer 119 , a metal-silicon compound 169 is formed on the surface of the p+ type silicon layer 159 , a metal-silicon compound 170 is formed on the surface of the gate electrode 235 , the gate wire 221 and the gate electrode 236 , a metal-silicon compound 172 is formed on the surface of the n+ type silicon layer 113 , and a metal-silicon compound 171 is formed on the surface of the n+ type
- the gate insulating film 140 and the metal film 138 are covered by the columnar silicon layer 232 , the polysilicon films 136 and 152 , the insulating film 129 and the insulating film 162 , and in addition, the gate insulating film 139 and the metal film 137 are covered by the columnar silicon layer 231 , the polysilicon films 135 and 151 , the insulating film 129 and the insulating film 161 , so the metal films 137 and 138 are not etched by the sulfuric acid hydrogen peroxide mixture or ammonia hydrogen peroxide mixture.
- the structure of the present invention it is possible to use metal in the gate electrode, it is possible to control depletion of the channel region, it is possible to lower the resistance of the gate electrode and it is possible to lower the resistance of the gate, source and drain through a metal-silicon compound.
- the natural oxide film on the surface of the silicon layer is removed by hydrofluoric acid as a pre-treatment prior to sputtering the metal such as Ni or Co.
- the insulating film 129 composed of an oxide film is protected from the hydrofluoric acid by the insulating film 164 composed of a nitride film formed in a sidewall shape on the sidewall.
- a contact stopper 173 of nitride film is formed, an interlayer insulating film 174 is deposited and planarization is undertaken, as shown in FIGS. 74A to 74D .
- a resist 175 for forming contact holes is formed above the columnar silicon layers 231 and 232 , as shown in FIGS. 75A to 75D .
- the interlayer insulating film 174 is etched to form contact holes 176 and 177 above the columnar silicon layer 232 , as shown in FIGS. 76A to 76D .
- the resist 175 is removed. Conditions on the substrate following removal are shown in FIGS. 77A to 77D .
- a resist 178 for forming contact holes above the planar silicon layers 233 and 234 and above the gate wire 221 is formed, as shown in FIGS. 78A to 78D .
- the interlayer insulating film 174 is etched to form contact holes 179 , 180 and 181 above the planar silicon layers 233 and 234 and above the gate wire 221 , respectively, as shown in FIGS. 79A to 79D .
- the etching conditions for forming the contact holes 176 and 177 above the columnar silicon 231 and 232 and the etching conditions for forming the contact holes 179 , 180 and 181 above the planar silicon layers 233 and 234 and above the gate wire 221 can each be optimized.
- the resist 178 is removed. Conditions on the substrate following removal are shown in FIGS. 80A to 80D .
- a contact stopper 173 is etched below the contact holes 179 , 176 , 180 , 177 and 181 . Conditions on the substrate following etching are shown in FIGS. 81A to 81D .
- a metal 183 is deposited on the top thereof, as shown in FIGS. 82A to 82D .
- a metal 184 is deposited to bury the gap, as shown in FIGS. 83A to 83D .
- the metals 184 and 183 and the barrier metal layer 182 are planarized and etched to form contacts 226 , 227 , 228 , 229 and 230 , as shown in FIGS. 84A to 84D .
- the contact 226 is composed of a barrier metal layer 185 and metal layers 190 and 195 .
- the contact 227 is composed of a barrier metal layer 186 and metal layers 191 and 196 .
- the contact 228 is composed of a barrier metal layer 187 and metal layers 192 and 197 .
- the contact 229 is composed of a barrier metal layer 188 and metal layers 193 and 198 .
- the contact 230 is composed of a barrier metal layer 189 and metal layers 194 and 199 .
- a barrier metal layer 200 , a metal layer 201 and a barrier metal layer 202 are deposited in this order on the planarized surface, as shown in FIGS. 85A to 85D .
- Resists 203 , 204 , 205 and 206 for forming a power source wire, an input wire and an output wire are formed, as shown in FIGS. 86A to 86D .
- the barrier metal layer 202 , the metal 201 and the barrier metal layer 200 are etched to form power source wires 222 and 225 , an input wire 224 and an output wire 223 , as shown in FIGS. 87A to 87D .
- the power source wire 222 is composed of a barrier metal layer 207 , a metal layer 208 and a barrier metal layer 209 .
- the power source wire 225 is composed of a barrier metal layer 216 , a metal layer 217 and a barrier metal layer 218 .
- the input wire 224 is composed of a barrier metal layer 213 , a metal layer 214 and a barrier metal layer 215 .
- the output wire 223 is composed of a barrier metal layer 210 , a metal layer 211 and a barrier metal layer 212 .
- the resists 203 , 204 , 205 and 206 are removed. Conditions on the substrate following removal are shown in FIGS. 88A to 88D .
Abstract
Description
- This application is a divisional patent application of U.S. patent application Ser. No. 14/831,303, filed Aug. 20, 2015, which is a continuation application of U.S. patent application Ser. No. 13/116,506, filed May 26, 2011, now U.S. Pat. No. 9,153,697, which claims the benefit of U.S. Provisional Patent Appl. Ser. No. 61/354,866, filed Jun. 15, 2010 and claims priority under 35 U.S.C. §119(a) to JP2010-136470 filed Jun. 15, 2010. The entire contents of these applications are hereby incorporated by reference.
- 1. Field of the Invention
- This application relates generally to a semiconductor device and a method of producing such.
- 2. Description of the Related Art
- Semiconductor devices, particularly integrated circuits using MOS transistors, are increasingly being highly integrated. MOS transistors in integrated circuits have been downsized to nano sizes as the integration level is increased. As MOS transistors are downsized, problems arise such as difficulty in leaking current control. For that reason, further downsizing is difficult. In order to resolve these problems, a surrounding gate transistor (SGT) structure has been proposed in which the source, gate and drain are provided on a substrate in the vertical direction and the gate surrounds an island-shaped semiconductor layer.
- In order to reduce power consumption in SGTs, it is preferable for resistance to be reduced in the source, gate and drain. In particular, in reducing the resistance of the gate electrode, it is desirable to use metal in the gate electrode. However, contamination of manufacturing equipment by metal and contamination of semiconductor devices produced by that manufacturing equipment is not desirable. Accordingly, processes subsequent to the forming of the metal gate electrode need to be special processes such as those that constantly control such metal contamination.
-
Patent Literature 1 discloses a method for producing an SGT satisfying to a certain extent the various conditions stated above. [Patent Literature 1] International Laid-Open Patent Publication 2009/110049 - However, in
Patent Literature 1 the protection of semiconductor manufacturing equipment and semiconductor devices from metal contamination is imperfect. For example, inPatent Literature 1 the gate electrode is formed by planarizing the gate metal using CMP (Chemical Mechanical Polishing) and then etching this material. At this time, the gate metal is not covered by other materials and is exposed. In addition, the gate metal is similarly exposed during the process of wet etching the nitride film hard mask and nitride film sidewall. Consequently, there is a concern that the CMP device, the gate etching device and the nitride film wet etching device could be contaminated by metal in the course of producing the SGT. Hence, there is a possibility that a semiconductor device produced through such a metal device could be contaminated by metal. - In addition, when forming a metal-semiconductor compound through etching in
Patent Literature 1, the gate metal is exposed. Consequently, perPatent Literature 1, the gate metal needs to be tantalum or some other material that is not etched by the chemicals used when forming the metal-semiconductor compound. - In addition, another problem is that similar to MOS transistors, as SGTs are downsized parasitic capacitance occurs in the multi-layered wiring and through this the operating speed of the SGT declines.
- In consideration of the foregoing, it is an objective of the present invention to provide a semiconductor device having a structure that controls metal contamination of semiconductor manufacturing equipment and semiconductor devices in semiconductor manufacturing processes while having good characteristics, and a method of producing such a device.
- The semiconductor device according one aspect includes a first planar layer comprising a first planar semiconductor layer, a second planar semiconductor layer, and a planar insulating layer separating the first and second planar semiconductor layers;
- a first columnar semiconductor layer on the first planar semiconductor layer;
- a first gate insulating film surrounding the first columnar semiconductor layer;
- a first gate electrode surrounding the first gate insulating film;
- a first insulating film overlying the planar insulating layer and between the first gate electrode and the first planar semiconductor layer, the first insulating film comprising an insulating material different from the first gate insulating film.
- The semiconductor device according to another aspect of the present invention is a semiconductor device provided with:
- a first planar semiconductor layer;
- a first columnar semiconductor layer formed on the first planar semiconductor layer;
- a first high concentration semiconductor layer formed on the first planar semiconductor layer and the lower region of the first columnar semiconductor layer;
- a second high concentration semiconductor layer of the same conductive type as the first high concentration semiconductor layer, formed on the upper region of the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;
- a first semiconductor film formed on the first metal film so as to surround the first metal film;
- a first gate electrode composed of the first metal film and the first semiconductor film;
- a first insulating film formed between the first gate electrode and the first planar semiconductor layer;
- a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround the upper region of the first columnar semiconductor layer;
- a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film;
- a first contact formed above the first columnar semiconductor layer;
- a second contact formed above the first planar semiconductor layer; and
- a third contact formed above the first gate electrode;
- wherein the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film.
- It is preferable for the thickness of the second insulating film to be thicker than the sum of the thickness of the first gate insulating film and the thickness of the first metal film.
- It is preferable for the semiconductor device to further have a first metal-semiconductor compound formed on the upper surface of the first high concentration semiconductor layer.
- It is preferable for the length from the center of the first columnar semiconductor layer to the edge of the first planar semiconductor layer to be larger than the sum of the length from the center to the sidewall of the first columnar semiconductor layer, the thickness of the first gate insulating film, the thickness of the first gate electrode and the thickness of the third insulating film.
- It is also possible for the semiconductor device to further have a third metal-semiconductor compound formed on the top surface of the first gate electrode.
- It is also possible for the semiconductor device to further have a second metal-semiconductor compound formed on the top surface of the second high concentration semiconductor layer.
- The semiconductor device according to a yet another aspect of the present invention is provided with a first transistor and a second transistor, wherein:
- the first transistor has:
- a first planar semiconductor layer;
- a first columnar semiconductor layer formed on the first planar semiconductor layer;
- a first high concentration semiconductor layer of second conductive type formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a second high concentration semiconductor layer of second conductive type formed on the upper region of the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;
- a first semiconductor film formed on the first metal film so as to surround the first metal film;
- a first gate electrode composed of the first metal film and the first semiconductor film;
- a first insulating film formed between the first gate electrode and the first planar semiconductor layer;
- a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround upper region of the first columnar semiconductor layer;
- a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film;
- a first metal-semiconductor compound formed on the top surface of the portion of the first high concentration semiconductor layer formed in the region below the first columnar semiconductor layer;
- a third metal-semiconductor compound formed on the top surface of the first gate electrode; and,
- a second metal-semiconductor compound formed on the top surface of the second high concentration semiconductor layer;
- and the second transistor has:
- a second planar semiconductor layer;
- a second columnar semiconductor layer formed on the second planar semiconductor layer;
- a third high concentration semiconductor layer of first conductive type formed on the lower region of the second columnar semiconductor layer and on the region of the second planar semiconductor layer below the second columnar semiconductor layer;
- a fourth high concentration semiconductor layer of first conductive type formed on the upper region of the second columnar semiconductor layer;
- a second gate insulating film formed on the sidewall of the second columnar semiconductor layer between the third high concentration semiconductor layer and the fourth high concentration semiconductor layer, so as to surround the second columnar semiconductor layer;
- a second metal film formed on the second gate insulating film so as to surround the second gate insulating film;
- a second semiconductor film formed on the second metal film so as to surround the second metal film;
- a second gate electrode composed of the second metal film and the second semiconductor film;
- a fourth insulating film formed between the second gate electrode and the second planar semiconductor layer;
- a fifth insulating film formed in sidewall shape contacting the upper sidewall of the second columnar semiconductor layer and the top surface of the second gate electrode so as to surround the top region of the second columnar semiconductor layer;
- a sixth insulating film formed in a sidewall shape contacting the sidewall of the fourth insulating film and the second gate electrode so as to surround the second gate electrode and the fourth insulating film;
- a fourth metal-semiconductor compound formed on the top surface of the portion of the third high concentration semiconductor layer formed in the region below the second columnar semiconductor layer;
- a fifth metal-semiconductor compound formed on the top surface of the second gate electrode; and,
- a sixth metal-semiconductor compound formed on the top surface of the fourth high concentration semiconductor layer;
- wherein the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, and
- the second gate insulating film and the second metal film are covered by the second columnar semiconductor layer, the second semiconductor film, the fourth insulating film and the fifth insulating film.
- It is preferable for the first gate insulating film and the first metal film to be formed from materials that make the first transistor enhancement-type, and
- the second gate insulating film and the second metal film to be formed from materials that make the second transistor enhancement-type.
- It is preferable for the thickness of the second insulating film to be thicker than the sum of the thickness of the first gate insulating film and the thickness of the first metal film.
- It is also possible for the semiconductor device to be such that the length from the center of the first columnar semiconductor layer to the edge of the first planar semiconductor layer is larger than the sum of the length from the center to the sidewall of the first columnar semiconductor layer, the thickness of the first gate insulating film, the thickness of the first gate electrode and the thickness of the third insulating film.
- It is also possible for the semiconductor device to be such that:
- the first conductive type is n+ type,
- the second conductive type is p+ type, and
- the first and second columnar semiconductor layers and the first and second planar semiconductor layers are made of silicon
- The method of producing a semiconductor device according to an aspect of the present invention is a method of producing the semiconductor device according to the present invention and includes:
- a process for preparing a first structure having:
- a first planar semiconductor layer;
- a first columnar semiconductor layer formed on the first planar semiconductor layer and a hard mask formed on the top surface of the first columnar semiconductor;
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer; and
- a first insulating film formed on the first planar semiconductor layer;
- a process for forming a seventh insulating film, a third metal film and a third semiconductor film, in that order, on the first structure;
- a process for etching the third semiconductor film and leaving a sidewall shape on the sidewall on the first columnar semiconductor layer;
- a process for etching the third metal film and leaving a sidewall shape on the sidewall of the first columnar semiconductor layer;
- a seventh insulating film etching process for etching the seventh insulating film and leaving a sidewall shape on the sidewall of the first columnar semiconductor layer; and
- a fourth semiconductor film formation process for forming a fourth semiconductor film on the result of the seventh insulating film etching process.
- It is also possible for the semiconductor device production method according to the present invention to include:
- a process for planarizing the fourth semiconductor film and the third semiconductor film in the result of the fourth semiconductor film formation process and exposing the upper region of the first metal film;
- a first metal film and first gate insulating film formation process for etching the third metal film and the seventh insulating film so that the upper sidewall of the first columnar semiconductor layer is exposed to form the first metal film and the first gate insulating film; and,
- a process for forming a first oxide film on the result of the first metal film and first gate insulating film formation process.
- The method of producing a semiconductor device according to another aspect of the present invention is a method of producing the semiconductor device according to the present invention and includes:
- a process for preparing a second structure having:
- a first planar semiconductor layer;
- a first columnar semiconductor layer formed on the first planar semiconductor layer;
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall in the middle region of the first columnar semiconductor layer so as to surround the first columnar semiconductor layer;
- a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;
- a first semiconductor film formed on the first metal film so as to surround the first metal film;
- a first gate electrode composed of the first metal film and the first semiconductor film; and
- a first insulating film formed between the first gate electrode and the first planar semiconductor layer; and
- a process for forming a second high concentration semiconductor layer of the same conductive type as the first high concentration semiconductor layer on the upper region of the first columnar semiconductor layer on the second structure by injecting a dopant at an angle of 10 degrees to 60 degrees, with a line orthogonal to the substrate being 0 degrees.
- The method of producing a semiconductor device according to a yet another aspect of the present invention is a method of producing the semiconductor device according to the present invention and includes:
- a process for preparing a third structure having:
- a first planar semiconductor layer;
- a first columnar semiconductor layer formed on the first planar semiconductor layer;
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a second high concentration semiconductor layer of the same conductive type as the first semiconductor layer, formed on the upper region of the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;
- a first semiconductor film formed on the first metal film so as to surround the first metal film;
- a first gate electrode composed of the first metal film and the first semiconductor film; and
- a first insulating film formed between the first gate electrode and the first planar semiconductor layer;
- a process for forming an eighth insulating film on the third structure; and
- a process for forming a second insulating film by etching the eighth insulating film in a sidewall shape so the eighth insulating film remains on the top surface of the first gate electrode and the upper sidewall of the first columnar semiconductor layer.
- The method of producing a semiconductor device according to a further aspect of the present invention is a method of producing the semiconductor device according to the present invention and includes:
- a process for preparing a fourth structure having:
- a first planar semiconductor layer;
- a first columnar semiconductor layer formed on the first planar semiconductor layer;
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a second high concentration semiconductor layer of the same conductive type as the first semiconductor layer, formed on the upper region of the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;
- a first semiconductor film formed on the first metal film so as to surround the first metal film;
- a first gate electrode composed of the first metal film and the first semiconductor film;
- a first insulating film formed between the first gate electrode and the first planar semiconductor layer;
- a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround the top region of the first columnar semiconductor layer;
- a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film; and
- a first gate wire connected to the first gate electrode;
- a contact stopper formation process for forming a contact stopper on the fourth structure;
- a process for forming an interlayer insulating film so as to bury the result of the contact stopper formation process;
- a process for forming a first resist on the interlayer insulating film, excluding on top of the first columnar semiconductor layer;
- a process for etching the interlayer insulating film and forming a first contact hole on the interlayer insulating film;
- a first resist removal process for removing the first resist;
- a process for forming a second resist on the result of the first resist removal process, excluding on the first planar semiconductor layer and on the first gate wire;
- a process for etching the interlayer insulating film and forming a second contact hole on top of the first planar semiconductor layer and forming a third contact hole on top of the first gate wire, on the interlayer insulating film;
- a process for removing the second resist; and
- a process for forming a first contact positioned above the first columnar semiconductor layer, a second contact positioned above the first planar semiconductor layer and a third contact positioned above the first gate wire on the first contact hole, the second contact hole and the third contact hole, respectively.
- In an aspect of the disclosure, the semiconductor device is provided with:
- a first planar semiconductor layer;
- a first columnar semiconductor layer formed on the first planar semiconductor layer;
- a first high concentration semiconductor layer formed on the first planar semiconductor layer and the lower region of the first columnar semiconductor layer;
- a second high concentration semiconductor layer of the same conductive type as the first high concentration semiconductor layer, formed on the upper region of the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;
- a first semiconductor film formed on the first metal film so as to surround the first metal film;
- a first gate electrode composed of the first metal film and the first semiconductor film;
- a first insulating film formed between the first gate electrode and the first planar semiconductor layer;
- a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround the upper region of the first columnar semiconductor layer;
- a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film;
- a first contact formed above the first columnar semiconductor layer;
- a second contact formed above the first planar semiconductor layer; and
- a third contact formed above the first gate electrode;
- and the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film.
- Through this, an SGT structure is provided that uses metal in the gate electrode while controlling metal contamination, lowers the resistance of the gate, source and drain, and reduces parasitic capacitance.
- The first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film.
- If the metal film is exposed when the metal-semiconductor compound is formed, the metal film is etched by a mixture, such as, a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture when the metal-semiconductor compound is formed. However, in the structure of the present invention, the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, so the first metal film is not etched by the sulfuric acid hydrogen peroxide mixture or the ammonia hydrogen peroxide mixture when the compound of metal and semiconductor is formed. Through this, it is possible to form a metal-semiconductor compound on the first high concentration semiconductor layer, the first gate electrode and the second high concentration semiconductor layer, it is possible to control depletion of the channel region by using metal in the gate electrode, to reduce gate electrode resistance and to reduce the resistance of the gate, source and drain through a compound of metal and silicon. In addition, it is possible to reduce parasitic capacitance between the gate electrode and the planar semiconductor layer by means of the first insulating film.
- In addition, the first gate insulating film and the first metal film are formed only surrounding the first columnar semiconductor layer, and the first metal film is covered by a semiconductor film such as polysilicon, so when the semiconductor film is planarized using a CMP device during gate formation, it is possible to prevent metal contamination of the CMP device.
- In addition, the first gate insulating film and the first metal film are formed only surrounding the first columnar semiconductor layer, and the first metal film is covered by a semiconductor film such as polysilicon, so when the semiconductor film is etched during gate etching, it is possible to prevent metal contamination of the gate etching device.
- In addition, the first gate insulating film and the first metal film are formed only surrounding the first columnar semiconductor layer, and the first metal film is covered by a semiconductor film such as polysilicon, so when the nitride film hard mask and the nitride film sidewalls are wet etched, it is possible to prevent metal contamination of the nitride film wet etching device.
- In addition, with the present invention the thickness of the second insulating film is thicker than the sum of the thickness of the first gate insulating film and the thickness of the first metal film.
- Through this, the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, so the first metal film is not etched by the sulfuric acid hydrogen peroxide mixture or the ammonia hydrogen peroxide mixture when the compound of metal and semiconductor is formed. Through this, it is possible to form a metal-semiconductor compound on the first high concentration semiconductor layer, the first gate electrode and the second high concentration semiconductor layer without any special additional processes.
- By having a first metal-semiconductor compound formed on the upper surface of the first high concentration semiconductor layer, it is possible to lower the resistance of the first high concentration semiconductor layer.
- Here, the length from the center of the first columnar semiconductor layer to the edge of the first planar semiconductor layer is larger than the sum of the length from the center to the sidewall of the first columnar semiconductor layer, the thickness of the first gate insulating film, the thickness of the first gate electrode and the thickness of the third insulating film.
- Through this, it is possible to form the first metal-semiconductor compound on the first high concentration semiconductor layer formed on the first planar semiconductor layer, and to lower the resistance of the first high concentration semiconductor layer.
- Here, by having a third metal-semiconductor compound formed on the top surface of the first gate electrode, it is possible to lower the resistance of the first gate electrode.
- Here, by having a second metal-semiconductor compound formed on the top surface of the second high concentration semiconductor layer, it is possible to lower the resistance of the second high concentration semiconductor layer.
- The semiconductor device according to a second aspect of the present invention is provided with a first transistor and a second transistor, wherein:
- the first transistor has:
- a first planar semiconductor layer;
- a first columnar semiconductor layer formed on the first planar semiconductor layer;
- a first high concentration semiconductor layer of second conductive type formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a second high concentration semiconductor layer of second conductive type formed on the upper region of the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;
- a first semiconductor film formed on the first metal film so as to surround the first metal film;
- a first gate electrode composed of the first metal film and the first semiconductor film;
- a first insulating film formed between the first gate electrode and the first planar semiconductor layer;
- a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround upper region of the first columnar semiconductor layer;
- a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film;
- a first metal-semiconductor compound formed on the top surface of the portion of the first high concentration semiconductor layer formed in the region below the first columnar semiconductor layer;
- a third metal-semiconductor compound formed on the top surface of the first gate electrode; and,
- a second metal-semiconductor compound formed on the top surface of the second high concentration semiconductor layer;
- and the second transistor has:
- a second planar semiconductor layer;
- a second columnar semiconductor layer formed on the second planar semiconductor layer;
- a third high concentration semiconductor layer of first conductive type formed on the lower region of the second columnar semiconductor layer and on the region of the second planar semiconductor layer below the second columnar semiconductor layer;
- a fourth high concentration semiconductor layer of first conductive type formed on the upper region of the second columnar semiconductor layer;
- a second gate insulating film formed on the sidewall of the second columnar semiconductor layer between the third high concentration semiconductor layer and the fourth high concentration semiconductor layer, so as to surround the second columnar semiconductor layer;
- a second metal film formed on the second gate insulating film so as to surround the second gate insulating film;
- a second semiconductor film formed on the second metal film so as to surround the second metal film;
- a second gate electrode composed of the second metal film and the second semiconductor film;
- a fourth insulating film formed between the second gate electrode and the second planar semiconductor layer;
- a fifth insulating film formed in sidewall shape contacting the upper sidewall of the second columnar semiconductor layer and the top surface of the second gate electrode so as to surround the top region of the second columnar semiconductor layer;
- a sixth insulating film formed in a sidewall shape contacting the sidewall of the fourth insulating film and the second gate electrode so as to surround the second gate electrode and the fourth insulating film;
- a fourth metal-semiconductor compound formed on the top surface of the portion of the third high concentration semiconductor layer formed in the region below the second columnar semiconductor layer;
- a fifth metal-semiconductor compound formed on the top surface of the second gate electrode; and,
- a sixth metal-semiconductor compound formed on the top surface of the fourth high concentration semiconductor layer;
- wherein the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, and
- the second gate insulating film and the second metal film are covered by the second columnar semiconductor layer, the second semiconductor film, the fourth insulating film and the fifth insulating film.
- Through this, an SGT structure is provided that uses metal in the gate electrode while controlling metal contamination, lowers the resistance of the gate, source and drain, and reduces parasitic capacitance.
- The first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film.
- If the metal film is exposed when the metal-semiconductor compound is formed, the metal film is etched by a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture when the metal-semiconductor compound is formed. However, in the structure of the present invention, the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, so the first metal film is not etched by the sulfuric acid hydrogen peroxide mixture or the ammonia hydrogen peroxide mixture when the compound of metal and semiconductor is formed. Through this, it is possible to form a metal-semiconductor compound on the first high concentration semiconductor layer, the first gate electrode and the second high concentration semiconductor layer, and it is possible to control depletion of the channel region by using metal in the first gate electrode to reduce the resistance of the first gate electrode and to reduce the resistance of the gate, source and drain through a compound of metal and silicon. In addition, it is possible to reduce parasitic capacitance between the first gate electrode and the first planar semiconductor layer by means of the first insulating film.
- In addition, the second gate insulating film and the second metal film are covered by the second columnar semiconductor layer, the second semiconductor film, the fourth insulating film and the fifth insulating film. If the metal film is exposed when the metal-semiconductor compound is formed, the metal film is etched by a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture when the metal-semiconductor compound is formed. However, in the structure of the present invention, the second gate insulating film and the second metal film are covered by the second columnar semiconductor layer, the second semiconductor film, the fourth insulating film and the fifth insulating film, so the second metal film is not etched by the sulfuric acid hydrogen peroxide mixture or the ammonia hydrogen peroxide mixture when the metal-semiconductor compound is formed. Through this, it is possible to form a metal-semiconductor compound on the third high concentration semiconductor layer, the second gate electrode and the fourth high concentration semiconductor layer, to control depletion of the channel region by using metal in the second gate electrode, to reduce the resistance of the second gate electrode and to reduce the resistance of the gate, source and drain through a compound of metal and silicon. In addition, it is possible to reduce parasitic capacitance between the second gate electrode and the second planar semiconductor layer by means of the fourth insulating film.
- Here, the first gate insulating film and the first metal film are formed from materials that make the first transistor enhancement-type, and
- the second gate insulating film and the second metal film are formed from materials that make the second transistor enhancement-type.
- Through this, it is possible to reduce penetrating current that flows during operation of a semiconductor device composed of a first transistor and a second transistor.
- Here, by having the thickness of the second insulating film be thicker than the sum of the thickness of the first gate insulating film and the thickness of the first metal film, the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, so the first metal film is not etched by the sulfuric acid hydrogen peroxide mixture or the ammonia hydrogen peroxide mixture when the compound of metal and semiconductor is formed.
- Through this, it is possible to form a metal-semiconductor compound on the third high concentration semiconductor layer, the first gate electrode and the fourth high concentration semiconductor layer.
- Here, by having the length from the center of the first columnar semiconductor layer to the edge of the first planar semiconductor layer be larger than the sum of the length from the center to the sidewall of the first columnar semiconductor layer, the thickness of the first gate insulating film, the thickness of the first gate electrode and the thickness of the third insulating film, it is possible to form the first metal-semiconductor compound on the third high concentration semiconductor layer formed on the first planar semiconductor layer, and to lower the resistance of the third high concentration semiconductor layer.
- It is also possible for the semiconductor device to be such that:
- the first conductive type is n+ type,
- the second conductive type is p+ type, and
- the first and second columnar semiconductor layers and the first and second planar semiconductor layers are made of silicon.
- Through this, it is possible to form an inverter with the first transistor being an nMOS SGT and the second transistor being a pMOS SGT.
- The method of producing a semiconductor device according to the present invention includes:
- a process for preparing a first structure having:
- a first planar semiconductor layer;
- a first columnar semiconductor layer formed on the first planar semiconductor layer and a hard mask formed on the top surface of the first columnar semiconductor;
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer; and
- a first insulating film formed on the first planar semiconductor layer;
- a process for forming a seventh insulating film, a third metal film and a third semiconductor film, in that order, on the first structure;
- a process for etching the third semiconductor film and leaving a sidewall shape on the sidewall on the first columnar semiconductor layer;
- a process for etching the third metal film and leaving a sidewall shape on the sidewall of the first columnar semiconductor layer;
- a seventh insulating film etching process for etching the seventh insulating film and leaving a sidewall shape on the sidewall of the first columnar semiconductor layer; and
- a fourth semiconductor film formation process for forming a fourth semiconductor film on the result of the seventh insulating film etching process.
- Through this, the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the hard mask. When a high-k film is used for the first gate insulating film, the high-k film is a source of metal contamination, so it is possible to control metal contamination by the first gate insulating film and the first metal film, which are sources of contamination, being covered by the first columnar semiconductor layer, the fourth semiconductor film, the first insulating film and the hard mask.
- In addition, the semiconductor device production method according to the present invention may include:
- a process for planarizing the fourth semiconductor film and the third semiconductor film in the result of the fourth semiconductor film formation process and exposing the upper region of the first metal film;
- a first metal film and first gate insulating film formation process for etching the third metal film and the seventh insulating film so that the upper sidewall of the first columnar semiconductor layer is exposed to form the first metal film and the first gate insulating film; and,
- a process for forming a first oxide film on the result of the first metal film and first gate insulating film formation process.
- Through this, it is possible to control metal contamination of the CMP device used in the planarization process because metal is not exposed during the process of planarizing the fourth semiconductor film and the third semiconductor film, it is possible to determine the gate length of the SGT through etching of the semiconductor film, and it is possible to control fluctuations in gate length, that is to say variances in gate length, and damage to the first gate insulating film and the first metal film from the gate electrode top surface because the gate electrode top surface is protected by the deposited first oxide film from wet processes and dry processes performed in later procedures.
- In addition, the first gate insulating film and the first metal film are formed only around the first columnar silicon layer and the first metal film is covered by polysilicon, so it is possible to reduce metal contamination of the gate etching device by etching the polysilicon during gate etching.
- In addition, the first gate insulating film and the first metal film are formed only around the columnar semiconductor layer and the first metal film is covered by the first columnar semiconductor layer and the third and fourth semiconductor films, so it is possible to reduce metal contamination of the nitride film wet etching device when wet etching the nitride film hard mask and the nitride film sidewall.
- In addition, the method of producing a semiconductor device according to the present invention includes:
- a process for preparing a second structure having:
- a first planar semiconductor layer;
- a first columnar semiconductor layer formed on the first planar semiconductor layer;
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall in the middle region of the first columnar semiconductor layer so as to surround the first columnar semiconductor layer;
- a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;
- a first semiconductor film formed on the first metal film so as to surround the first metal film;
- a first gate electrode composed of the first metal film and the first semiconductor film; and
- a first insulating film formed between the first gate electrode and the first planar semiconductor layer; and
- a process for forming a second high concentration semiconductor layer of the same conductive type as the first high concentration semiconductor layer on the upper region of the first columnar semiconductor layer on the second structure by injecting a dopant at an angle of 10 degrees to 60 degrees, with a line orthogonal to the substrate being 0 degrees.
- Through this, it is possible to cover the first gate insulating film and the first metal film with the first columnar semiconductor layer, the first semiconductor layer, the first insulating film and the second insulating film.
- In addition, the method of producing a semiconductor device according to the present invention includes:
- a process for preparing a third structure having:
- a first planar semiconductor layer;
- a first columnar semiconductor layer formed on the first planar semiconductor layer;
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a second high concentration semiconductor layer of the same conductive type as the first high concentration semiconductor layer, formed on the upper region of the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;
- a first semiconductor film formed on the first metal film so as to surround the first metal film;
- a first gate electrode composed of the first metal film and the first semiconductor film; and
- a first insulating film formed between the first gate electrode and the first planar semiconductor layer;
- a process for forming an eighth insulating film on the third structure; and
- a process for forming a second insulating film by etching the eighth insulating film in a sidewall shape so the eighth insulating film remains on the top surface of the first gate electrode and the upper sidewall of the first columnar semiconductor layer.
- Through this, it is possible for the second high concentration silicon layer and the first gate electrode to be separated from the first gate insulating film, to have an overlap and to minimize that overlap.
- In addition, the method of producing a semiconductor device according to the present invention includes:
- a process for preparing a fourth structure having:
- a first planar semiconductor layer;
- a first columnar semiconductor layer formed on the first planar semiconductor layer;
- a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;
- a second high concentration semiconductor layer of the same conductive type as the first high concentration semiconductor layer, formed on the upper region of the first columnar semiconductor layer;
- a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;
- a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;
- a first semiconductor film formed on the first metal film so as to surround the first metal film;
- a first gate electrode composed of the first metal film and the first semiconductor film;
- a first insulating film formed between the first gate electrode and the first planar semiconductor layer;
- a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround the top region of the first columnar semiconductor layer;
- a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film; and
- a first gate wire connected to the first gate electrode;
- a contact stopper formation process for forming a contact stopper on the fourth structure;
- a process for forming an interlayer insulating film so as to bury the result of the contact stopper formation process;
- a process for forming a first resist on the interlayer insulating film, excluding on top of the first columnar semiconductor layer;
- a process for etching the interlayer insulating film and forming a first contact hole on the interlayer insulating film;
- a first resist removal process for removing the first resist;
- a process for forming a second resist on the result of the first resist removal process, excluding on the first planar semiconductor layer and on the first gate wire;
- a process for etching the interlayer insulating film and forming a second contact hole on top of the first planar semiconductor layer and forming a third contact hole on top of the first gate wire, on the interlayer insulating film;
- a process for removing the second resist; and
- a process for forming a first contact positioned above the first columnar semiconductor layer, a second contact positioned above the first planar semiconductor layer and a third contact positioned above the first gate wire on the first contact hole, the second contact hole and the third contact hole, respectively.
- Through this, the contact holes on the first planar semiconductor layer and the first gate wiring are formed through different processes, so it is possible to optimize etching conditions for forming the first contact hole on the first columnar semiconductor layer and etching conditions for forming the second contact hole on the first planar semiconductor layer and the third contact hole on the first gate wiring.
- A more complete understanding of this application can be obtained when the following detailed description is considered in conjunction with the following drawings, in which:
-
FIG. 1A is a planar view of the semiconductor device according to an embodiment of the present invention; -
FIG. 1B is a cross-sectional view along line X-X′ inFIG. 1A ; -
FIG. 1C is a cross-sectional view along line Y1-Y1′ inFIG. 1A ; -
FIG. 1D is a cross-sectional view along line Y2-Y2′ inFIG. 1A ; -
FIG. 2A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 2B is a cross-sectional view along line X-X′ inFIG. 2A ; -
FIG. 2C is a cross-sectional view along line Y1-Y1′ inFIG. 2A ; -
FIG. 2D is a cross-sectional view along line Y2-Y2′ inFIG. 2A ; -
FIG. 3A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 3B is a cross-sectional view along line X-X′ inFIG. 3A ; -
FIG. 3C is a cross-sectional view along line Y1-Y1′ inFIG. 3A ; -
FIG. 3D is a cross-sectional view along line Y2-Y2′ inFIG. 3A ; -
FIG. 4A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 4B is a cross-sectional view along line X-X′ inFIG. 4A ; -
FIG. 4C is a cross-sectional view along line Y1-Y1′ inFIG. 4A ; -
FIG. 4D is a cross-sectional view along line Y2-Y2′ inFIG. 4A ; -
FIG. 5A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 5B is a cross-sectional view along line X-X′ inFIG. 5A ; -
FIG. 5C is a cross-sectional view along line Y1-Y1′ inFIG. 5A ; -
FIG. 5D is a cross-sectional view along line Y2-Y2′ inFIG. 5A ; -
FIG. 6A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 6B is a cross-sectional view along line X-X′ inFIG. 6A ; -
FIG. 6C is a cross-sectional view along line Y1-Y1′ inFIG. 6A ; -
FIG. 6D is a cross-sectional view along line Y2-Y2′ inFIG. 6A ; -
FIG. 7A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 7B is a cross-sectional view along line X-X′ inFIG. 7A ; -
FIG. 7C is a cross-sectional view along line Y1-Y1′ inFIG. 7A ; -
FIG. 7D is a cross-sectional view along line Y2-Y2′ inFIG. 7A ; -
FIG. 8A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 8B is a cross-sectional view along line X-X′ inFIG. 8A ; -
FIG. 8C is a cross-sectional view along line Y1-Y1′ inFIG. 8A ; -
FIG. 8D is a cross-sectional view along line Y2-Y2′ inFIG. 8A ; -
FIG. 9A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 9B is a cross-sectional view along line X-X′ inFIG. 9A ; -
FIG. 9C is a cross-sectional view along line Y1-Y1′ inFIG. 9A ; -
FIG. 9D is a cross-sectional view along line Y2-Y2′ inFIG. 9A ; -
FIG. 10A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 10B is a cross-sectional view along line X-X′ inFIG. 10A ; -
FIG. 10C is a cross-sectional view along line Y1-Y1′ inFIG. 10A ; -
FIG. 10D is a cross-sectional view along line Y2-Y2′ inFIG. 10A ; -
FIG. 11A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 11B is a cross-sectional view along line X-X′ inFIG. 11A ; -
FIG. 11C is a cross-sectional view along line Y1-Y1′ inFIG. 11A ; -
FIG. 11D is a cross-sectional view along line Y2-Y2′ inFIG. 11A ; -
FIG. 12A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 12B is a cross-sectional view along line X-X′ inFIG. 12A ; -
FIG. 12C is a cross-sectional view along line Y1-Y1′ inFIG. 12A ; -
FIG. 12D is a cross-sectional view along line Y2-Y2′ inFIG. 12A ; -
FIG. 13A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 13B is a cross-sectional view along line X-X′ inFIG. 13A ; -
FIG. 13C is a cross-sectional view along line Y1-Y1′ inFIG. 13A ; -
FIG. 13D is a cross-sectional view along line Y2-Y2′ inFIG. 13A ; -
FIG. 14A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 14B is a cross-sectional view along line X-X′ inFIG. 14A ; -
FIG. 14C is a cross-sectional view along line Y1-Y1′ inFIG. 14A ; -
FIG. 14D is a cross-sectional view along line Y2-Y2′ inFIG. 14A ; -
FIG. 15A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 15B is a cross-sectional view along line X-X′ inFIG. 15A ; -
FIG. 15C is a cross-sectional view along line Y1-Y1′ inFIG. 15A ; -
FIG. 15D is a cross-sectional view along line Y2-Y2′ inFIG. 15A ; -
FIG. 16A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 16B is a cross-sectional view along line X-X′ inFIG. 16A ; -
FIG. 16C is a cross-sectional view along line Y1-Y1′ inFIG. 16A ; -
FIG. 16D is a cross-sectional view along line Y2-Y2′ inFIG. 16A ; -
FIG. 17A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 17B is a cross-sectional view along line X-X′ inFIG. 17A ; -
FIG. 17C is a cross-sectional view along line Y1-Y1′ inFIG. 17A ; -
FIG. 17D is a cross-sectional view along line Y2-Y2′ inFIG. 17A ; -
FIG. 18A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 18B is a cross-sectional view along line X-X′ inFIG. 18A ; -
FIG. 18C is a cross-sectional view along line Y1-Y1′ inFIG. 18A ; -
FIG. 18D is a cross-sectional view along line Y2-Y2′ inFIG. 18A ; -
FIG. 19A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 19B is a cross-sectional view along line X-X′ inFIG. 19A ; -
FIG. 19C is a cross-sectional view along line Y1-Y1′ inFIG. 19A ; -
FIG. 19D is a cross-sectional view along line Y2-Y2′ inFIG. 19A ; -
FIG. 20A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 20B is a cross-sectional view along line X-X′ inFIG. 20A ; -
FIG. 20C is a cross-sectional view along line Y1-Y1′ inFIG. 20A ; -
FIG. 20D is a cross-sectional view along line Y2-Y2′ inFIG. 20A ; -
FIG. 21A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 21B is a cross-sectional view along line X-X′ inFIG. 21A ; -
FIG. 21C is a cross-sectional view along line Y1-Y1′ inFIG. 21A ; -
FIG. 21D is a cross-sectional view along line Y2-Y2′ inFIG. 21A ; -
FIG. 22A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 22B is a cross-sectional view along line X-X′ inFIG. 22A ; -
FIG. 22C is a cross-sectional view along line Y1-Y1′ inFIG. 22A ; -
FIG. 22D is a cross-sectional view along line Y2-Y2′ inFIG. 22A ; -
FIG. 23A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 23B is a cross-sectional view along line X-X′ inFIG. 23A ; -
FIG. 23C is a cross-sectional view along line Y1-Y1′ inFIG. 23A ; -
FIG. 23D is a cross-sectional view along line Y2-Y2′ inFIG. 23A ; -
FIG. 24A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 24B is a cross-sectional view along line X-X′ inFIG. 24A ; -
FIG. 24C is a cross-sectional view along line Y1-Y1′ inFIG. 24A ; -
FIG. 24D is a cross-sectional view along line Y2-Y2′ inFIG. 24A ; -
FIG. 25A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 25B is a cross-sectional view along line X-X′ inFIG. 25A ; -
FIG. 25C is a cross-sectional view along line Y1-Y1′ inFIG. 25A ; -
FIG. 25D is a cross-sectional view along line Y2-Y2′ inFIG. 25A ; -
FIG. 26A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 26B is a cross-sectional view along line X-X′ inFIG. 26A ; -
FIG. 26C is a cross-sectional view along line Y1-Y1′ inFIG. 26A ; -
FIG. 26D is a cross-sectional view along line Y2-Y2′ inFIG. 26A ; -
FIG. 27A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 27B is a cross-sectional view along line X-X′ inFIG. 27A ; -
FIG. 27C is a cross-sectional view along line Y1-Y1′ inFIG. 27A ; -
FIG. 27D is a cross-sectional view along line Y2-Y2′ inFIG. 27A ; -
FIG. 28A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 28B is a cross-sectional view along line X-X′ inFIG. 28A ; -
FIG. 28C is a cross-sectional view along line Y1-Y1′ inFIG. 28A ; -
FIG. 28D is a cross-sectional view along line Y2-Y2′ inFIG. 28A ; -
FIG. 29A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 29B is a cross-sectional view along line X-X′ inFIG. 29A ; -
FIG. 29C is a cross-sectional view along line Y1-Y1′ inFIG. 29A ; -
FIG. 29D is a cross-sectional view along line Y2-Y2′ inFIG. 29A ; -
FIG. 30A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 30B is a cross-sectional view along line X-X′ inFIG. 30A ; -
FIG. 30C is a cross-sectional view along line Y1-Y1′ inFIG. 30A ; -
FIG. 30D is a cross-sectional view along line Y2-Y2′ inFIG. 30A ; -
FIG. 31A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 31B is a cross-sectional view along line X-X′ inFIG. 31A ; -
FIG. 31C is a cross-sectional view along line Y1-Y1′ inFIG. 31A ; -
FIG. 31D is a cross-sectional view along line Y2-Y2′ inFIG. 31A ; -
FIG. 32A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 32B is a cross-sectional view along line X-X′ inFIG. 32A ; -
FIG. 32C is a cross-sectional view along line Y1-Y1′ inFIG. 32A ; -
FIG. 32D is a cross-sectional view along line Y2-Y2′ inFIG. 32A ; -
FIG. 33A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 33B is a cross-sectional view along line X-X′ inFIG. 33A ; -
FIG. 33C is a cross-sectional view along line Y1-Y1′ inFIG. 33A ; -
FIG. 33D is a cross-sectional view along line Y2-Y2′ inFIG. 33A ; -
FIG. 34A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 34B is a cross-sectional view along line X-X′ inFIG. 34A ; -
FIG. 34C is a cross-sectional view along line Y1-Y1′ inFIG. 34A ; -
FIG. 34D is a cross-sectional view along line Y2-Y2′ inFIG. 34A ; -
FIG. 35A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 35B is a cross-sectional view along line X-X′ inFIG. 35A ; -
FIG. 35C is a cross-sectional view along line Y1-Y1′ inFIG. 35A ; -
FIG. 35D is a cross-sectional view along line Y2-Y2′ inFIG. 35A ; -
FIG. 36A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 36B is a cross-sectional view along line X-X′ inFIG. 36A ; -
FIG. 36C is a cross-sectional view along line Y1-Y1′ inFIG. 36A ; -
FIG. 36D is a cross-sectional view along line Y2-Y2′ inFIG. 36A ; -
FIG. 37A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 37B is a cross-sectional view along line X-X′ inFIG. 37A ; -
FIG. 37C is a cross-sectional view along line Y1-Y1′ inFIG. 37A ; -
FIG. 37D is a cross-sectional view along line Y2-Y2′ inFIG. 37A ; -
FIG. 38A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 38B is a cross-sectional view along line X-X′ inFIG. 38A ; -
FIG. 38C is a cross-sectional view along line Y1-Y1′ inFIG. 38A ; -
FIG. 38D is a cross-sectional view along line Y2-Y2′ inFIG. 38A ; -
FIG. 39A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 39B is a cross-sectional view along line X-X′ inFIG. 39A ; -
FIG. 39C is a cross-sectional view along line Y1-Y1′ inFIG. 39A ; -
FIG. 39D is a cross-sectional view along line Y2-Y2′ inFIG. 39A ; -
FIG. 40A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 40B is a cross-sectional view along line X-X′ inFIG. 40A ; -
FIG. 40C is a cross-sectional view along line Y1-Y1′ inFIG. 40A ; -
FIG. 40D is a cross-sectional view along line Y2-Y2′ inFIG. 40A ; -
FIG. 41A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 41B is a cross-sectional view along line X-X′ inFIG. 41A ; -
FIG. 41C is a cross-sectional view along line Y1-Y1′ inFIG. 41A ; -
FIG. 41D is a cross-sectional view along line Y2-Y2′ inFIG. 41A ; -
FIG. 42A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 42B is a cross-sectional view along line X-X′ inFIG. 42A ; -
FIG. 42C is a cross-sectional view along line Y1-Y1′ inFIG. 42A ; -
FIG. 42D is a cross-sectional view along line Y2-Y2′ inFIG. 42A ; -
FIG. 43A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 43B is a cross-sectional view along line X-X′ inFIG. 43A ; -
FIG. 43C is a cross-sectional view along line Y1-Y1′ inFIG. 43A ; -
FIG. 43D is a cross-sectional view along line Y2-Y2′ inFIG. 43A ; -
FIG. 44A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 44B is a cross-sectional view along line X-X′ inFIG. 44A ; -
FIG. 44C is a cross-sectional view along line Y1-Y1′ inFIG. 44A ; -
FIG. 44D is a cross-sectional view along line Y2-Y2′ inFIG. 44A ; -
FIG. 45A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 45B is a cross-sectional view along line X-X′ inFIG. 45A ; -
FIG. 45C is a cross-sectional view along line Y1-Y1′ inFIG. 45A ; -
FIG. 45D is a cross-sectional view along line Y2-Y2′ inFIG. 45A ; -
FIG. 46A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 46B is a cross-sectional view along line X-X′ inFIG. 46A ; -
FIG. 46C is a cross-sectional view along line Y1-Y1′ inFIG. 46A ; -
FIG. 46D is a cross-sectional view along line Y2-Y2′ inFIG. 46A ; -
FIG. 47A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 47B is a cross-sectional view along line X-X′ inFIG. 47A ; -
FIG. 47C is a cross-sectional view along line Y1-Y1′ inFIG. 47A ; -
FIG. 47D is a cross-sectional view along line Y2-Y2′ inFIG. 47A ; -
FIG. 48A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 48B is a cross-sectional view along line X-X′ inFIG. 48A ; -
FIG. 48C is a cross-sectional view along line Y1-Y1′ inFIG. 48A ; -
FIG. 48D is a cross-sectional view along line Y2-Y2′ inFIG. 48A ; -
FIG. 49A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 49B is a cross-sectional view along line X-X′ inFIG. 49A ; -
FIG. 49C is a cross-sectional view along line Y1-Y1′ inFIG. 49A ; -
FIG. 49D is a cross-sectional view along line Y2-Y2′ inFIG. 49A ; -
FIG. 50A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 50B is a cross-sectional view along line X-X′ inFIG. 50A ; -
FIG. 50C is a cross-sectional view along line Y1-Y1′ inFIG. 50A ; -
FIG. 50D is a cross-sectional view along line Y2-Y2′ inFIG. 50A ; -
FIG. 51A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 51B is a cross-sectional view along line X-X′ inFIG. 51A ; -
FIG. 51C is a cross-sectional view along line Y1-Y1′ inFIG. 51A ; -
FIG. 51D is a cross-sectional view along line Y2-Y2′ inFIG. 51A ; -
FIG. 52A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 52B is a cross-sectional view along line X-X′ inFIG. 52A ; -
FIG. 52C is a cross-sectional view along line Y1-Y1′ inFIG. 52A ; -
FIG. 52D is a cross-sectional view along line Y2-Y2′ inFIG. 52A ; -
FIG. 53A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 53B is a cross-sectional view along line X-X′ inFIG. 53A ; -
FIG. 53C is a cross-sectional view along line Y1-Y1′ inFIG. 53A ; -
FIG. 53D is a cross-sectional view along line Y2-Y2′ inFIG. 53A ; -
FIG. 54A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 54B is a cross-sectional view along line X-X′ inFIG. 54A ; -
FIG. 54C is a cross-sectional view along line Y1-Y1′ inFIG. 54A ; -
FIG. 54D is a cross-sectional view along line Y2-Y2′ inFIG. 54A ; -
FIG. 55A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 55B is a cross-sectional view along line X-X′ inFIG. 55A ; -
FIG. 55C is a cross-sectional view along line Y1-Y1′ inFIG. 55A ; -
FIG. 55D is a cross-sectional view along line Y2-Y2′ inFIG. 55A ; -
FIG. 56A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 56B is a cross-sectional view along line X-X′ inFIG. 56A ; -
FIG. 56C is a cross-sectional view along line Y1-Y1′ inFIG. 56A ; -
FIG. 56D is a cross-sectional view along line Y2-Y2′ inFIG. 56A ; -
FIG. 57A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 57B is a cross-sectional view along line X-X′ inFIG. 57A ; -
FIG. 57C is a cross-sectional view along line Y1-Y1′ inFIG. 57A ; -
FIG. 57D is a cross-sectional view along line Y2-Y2′ inFIG. 57A ; -
FIG. 58A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 58B is a cross-sectional view along line X-X′ inFIG. 58A ; -
FIG. 58C is a cross-sectional view along line Y1-Y1′ inFIG. 58A ; -
FIG. 58D is a cross-sectional view along line Y2-Y2′ inFIG. 58A ; -
FIG. 59A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 59B is a cross-sectional view along line X-X′ inFIG. 59A ; -
FIG. 59C is a cross-sectional view along line Y1-Y1′ inFIG. 59A ; -
FIG. 59D is a cross-sectional view along line Y2-Y2′ inFIG. 59A ; -
FIG. 60A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 60B is a cross-sectional view along line X-X′ inFIG. 60A ; -
FIG. 60C is a cross-sectional view along line Y1-Y1′ inFIG. 60A ; -
FIG. 60D is a cross-sectional view along line Y2-Y2′ inFIG. 60A ; -
FIG. 61A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 61B is a cross-sectional view along line X-X′ inFIG. 61A ; -
FIG. 61C is a cross-sectional view along line Y1-Y1′ inFIG. 61A ; -
FIG. 61D is a cross-sectional view along line Y2-Y2′ inFIG. 61A ; -
FIG. 62A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 62B is a cross-sectional view along line X-X′ inFIG. 62A ; -
FIG. 62C is a cross-sectional view along line Y1-Y1′ inFIG. 62A ; -
FIG. 62D is a cross-sectional view along line Y2-Y2′ inFIG. 62A ; -
FIG. 63A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 63B is a cross-sectional view along line X-X′ inFIG. 63A ; -
FIG. 63C is a cross-sectional view along line Y1-Y1′ inFIG. 63A ; -
FIG. 63D is a cross-sectional view along line Y2-Y2′ inFIG. 63A ; -
FIG. 64A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 64B is a cross-sectional view along line X-X′ inFIG. 64A ; -
FIG. 64C is a cross-sectional view along line Y1-Y1′ inFIG. 64A ; -
FIG. 64D is a cross-sectional view along line Y2-Y2′ inFIG. 64A ; -
FIG. 65A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 65B is a cross-sectional view along line X-X′ inFIG. 65A ; -
FIG. 65C is a cross-sectional view along line Y1-Y1′ inFIG. 65A ; -
FIG. 65D is a cross-sectional view along line Y2-Y2′ inFIG. 65A ; -
FIG. 66A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 66B is a cross-sectional view along line X-X′ inFIG. 66A ; -
FIG. 66C is a cross-sectional view along line Y1-Y1′ inFIG. 66A ; -
FIG. 66D is a cross-sectional view along line Y2-Y2′ inFIG. 66A ; -
FIG. 67A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 67B is a cross-sectional view along line X-X′ inFIG. 67A ; -
FIG. 67C is a cross-sectional view along line Y1-Y1′ inFIG. 67A ; -
FIG. 67D is a cross-sectional view along line Y2-Y2′ inFIG. 67A ; -
FIG. 68A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 68B is a cross-sectional view along line X-X′ inFIG. 68A ; -
FIG. 68C is a cross-sectional view along line Y1-Y1′ inFIG. 68A ; -
FIG. 68D is a cross-sectional view along line Y2-Y2′ inFIG. 68A ; -
FIG. 69A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 69B is a cross-sectional view along line X-X′ inFIG. 69A ; -
FIG. 69C is a cross-sectional view along line Y1-Y1′ inFIG. 69A ; -
FIG. 69D is a cross-sectional view along line Y2-Y2′ inFIG. 69A ; -
FIG. 70A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 70B is a cross-sectional view along line X-X′ inFIG. 70A ; -
FIG. 70C is a cross-sectional view along line Y1-Y1′ inFIG. 70A ; -
FIG. 70D is a cross-sectional view along line Y2-Y2′ inFIG. 70A ; -
FIG. 71A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 71B is a cross-sectional view along line X-X′ inFIG. 71A ; -
FIG. 71C is a cross-sectional view along line Y1-Y1′ inFIG. 71A ; -
FIG. 71D is a cross-sectional view along line Y2-Y2′ inFIG. 71A ; -
FIG. 72A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 72B is a cross-sectional view along line X-X′ inFIG. 72A ; -
FIG. 72C is a cross-sectional view along line Y1-Y1′ inFIG. 72A ; -
FIG. 72D is a cross-sectional view along line Y2-Y2′ inFIG. 72A ; -
FIG. 73A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 73B is a cross-sectional view along line X-X′ inFIG. 73A ; -
FIG. 73C is a cross-sectional view along line Y1-Y1′ inFIG. 73A ; -
FIG. 73D is a cross-sectional view along line Y2-Y2′ inFIG. 73A ; -
FIG. 74A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 74B is a cross-sectional view along line X-X′ inFIG. 74A ; -
FIG. 74C is a cross-sectional view along line Y1-Y1′ inFIG. 74A ; -
FIG. 74D is a cross-sectional view along line Y2-Y2′ inFIG. 74A ; -
FIG. 75A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 75B is a cross-sectional view along line X-X′ inFIG. 75A ; -
FIG. 75C is a cross-sectional view along line Y1-Y1′ inFIG. 75A ; -
FIG. 75D is a cross-sectional view along line Y2-Y2′ inFIG. 75A ; -
FIG. 76A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 76B is a cross-sectional view along line X-X′ inFIG. 76A ; -
FIG. 76C is a cross-sectional view along line Y1-Y1′ inFIG. 76A ; -
FIG. 76D is a cross-sectional view along line Y2-Y2′ inFIG. 76A ; -
FIG. 77A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 77B is a cross-sectional view along line X-X′ inFIG. 77A ; -
FIG. 77C is a cross-sectional view along line Y1-Y1′ inFIG. 77A ; -
FIG. 77D is a cross-sectional view along line Y2-Y2′ inFIG. 77A ; -
FIG. 78A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 78B is a cross-sectional view along line X-X′ inFIG. 78A ; -
FIG. 78C is a cross-sectional view along line Y1-Y1′ inFIG. 78A ; -
FIG. 78D is a cross-sectional view along line Y2-Y2′ inFIG. 78A ; -
FIG. 79A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 79B is a cross-sectional view along line X-X′ inFIG. 79A ; -
FIG. 79C is a cross-sectional view along line Y1-Y1′ inFIG. 79A ; -
FIG. 79D is a cross-sectional view along line Y2-Y2′ inFIG. 79A ; -
FIG. 80A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 80B is a cross-sectional view along line X-X′ inFIG. 80A ; -
FIG. 80C is a cross-sectional view along line Y1-Y1′ inFIG. 80A ; -
FIG. 80D is a cross-sectional view along line Y2-Y2′ inFIG. 80A ; -
FIG. 81A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 81B is a cross-sectional view along line X-X′ inFIG. 81A ; -
FIG. 81C is a cross-sectional view along line Y1-Y1′ inFIG. 81A ; -
FIG. 81D is a cross-sectional view along line Y2-Y2′ inFIG. 81A ; -
FIG. 82A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 82B is a cross-sectional view along line X-X′ inFIG. 82A ; -
FIG. 82C is a cross-sectional view along line Y1-Y1′ inFIG. 82A ; -
FIG. 82D is a cross-sectional view along line Y2-Y2′ inFIG. 82A ; -
FIG. 83A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 83B is a cross-sectional view along line X-X′ inFIG. 83A ; -
FIG. 83C is a cross-sectional view along line Y1-Y1′ inFIG. 83A ; -
FIG. 83D is a cross-sectional view along line Y2-Y2′ inFIG. 83A ; -
FIG. 84A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 84B is a cross-sectional view along line X-X′ inFIG. 84A ; -
FIG. 84C is a cross-sectional view along line Y1-Y1′ inFIG. 84A ; -
FIG. 84D is a cross-sectional view along line Y2-Y2′ inFIG. 84A ; -
FIG. 85A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 85B is a cross-sectional view along line X-X′ inFIG. 85A ; -
FIG. 85C is a cross-sectional view along line Y1-Y1′ inFIG. 85A ; -
FIG. 85D is a cross-sectional view along line Y2-Y2′ inFIG. 85A ; -
FIG. 86A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 86B is a cross-sectional view along line X-X′ inFIG. 86A ; -
FIG. 86C is a cross-sectional view along line Y1-Y1′ inFIG. 86A ; -
FIG. 86D is a cross-sectional view along line Y2-Y2′ inFIG. 86A ; -
FIG. 87A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 87B is a cross-sectional view along line X-X′ inFIG. 87A ; -
FIG. 87C is a cross-sectional view along line Y1-Y1′ inFIG. 87A ; -
FIG. 87D is a cross-sectional view along line Y2-Y2′ inFIG. 87A ; -
FIG. 88A is a planar view of the semiconductor device during production, showing the method of producing the semiconductor device according to an embodiment of the present invention; -
FIG. 88B is a cross-sectional view along line X-X′ inFIG. 88A ; -
FIG. 88C is a cross-sectional view along line Y1-Y1′ inFIG. 88A ; and -
FIG. 88D is a cross-sectional view along line Y2-Y2′ inFIG. 88A ; - The embodiments of the present invention are described below with reference to
FIGS. 1A to 88D . -
FIG. 1C shows anSGT 220 according to a first embodiment of the present invention. - This
SGT 220 is an nMOS SGT and is provided with a firstplanar silicon layer 234 and a firstcolumnar silicon layer 232 formed on top of the firstplanar silicon layer 234. - A first n+
type silicon layer 113 is formed on the lower region of the firstcolumnar silicon layer 232 and the region of the firstplanar silicon layer 234 positioned below the firstcolumnar silicon layer 232, and a second n+type silicon layer 157 is formed on the upper region of the firstcolumnar silicon layer 232. In this embodiment, the first n+type silicon layer 113, for example, functions as a source scattering layer and the second n+type silicon layer 157 functions as a drain scattering layer. In addition, the area between the source scattering layer and the drawing scattering layer functions as a channel region. The firstcolumnar silicon layer 232 between the first n+type silicon layer 113 and the second n+type silicon layer 157 functioning as this channel region is called afirst silicon layer 114. - A
gate insulating film 140 is formed surrounding the firstcolumnar silicon layer 232 functioning as the channel region. Thegate insulating film 140 may be, for example, an oxide film, a nitride film or a high-k film. Furthermore, afirst metal film 138 is formed surrounding thisgate insulating film 140. Thefirst metal film 138 may be, for example, titanium, titanium nitride, tantalum or tantalum nitride.First polysilicon films first metal film 138. Thefirst metal film 138 and thefirst polysilicon films first gate electrode 236. Thus, by using metal as the gate electrode, it is possible to control depletion of the channel region while also lowering the resistance of the gate electrode. - In the present embodiment, a channel is formed in the
first silicon layer 114 by impressing a voltage on thefirst gate electrode 236 during operation. - In addition, a first metal-
silicon compound 172, a third metal-silicon compound 170 and a second metal-silicon compound 171 are formed on the first n+type silicon layer 113, thegate electrode 236 and the second n+type silicon layer 157, respectively. As the metal comprising the metal-silicon compounds, Ni or Co may be used, for example. Through these metal-silicon compounds, the first n+type silicon layer 113, thegate electrode 236 and the second n+type silicon layer 157 are connected to below-described contacts. Through this, the resistances of the gate, source and drain are lowered. - The first n+
type silicon layer 113 is connected to acontact 230 via the first metal-silicon compound 172. Thecontact 230 is formed from abarrier metal layer 189 andmetal layers contact 230 is further connected to apower source wire 225. Thepower source wire 225 is composed of abarrier metal layer 216, ametal layer 217 and abarrier metal layer 218. - The second n+
type silicon layer 157 is connected to acontact 229 via the second metal-silicon compound 171. Thecontact 229 is composed of abarrier metal layer 188 andmetal layers contact 229 is further connected to anoutput wire 223. Theoutput wire 223 is composed of abarrier metal layer 213, ametal 214 and abarrier metal layer 215. - Furthermore, a first
insulating film 129 is formed between thefirst gate electrode 236 and the firstplanar silicon layer 234, a secondinsulating film 162 is formed in a sidewall shape on the upper sidewall of the firstcolumnar silicon layer 232 and above thefirst gate electrode 236, and a thirdinsulating film 164 is formed in a sidewall shape on the sidewall of thefirst gate electrode 236 and the first insulatingfilm 129. The firstinsulating film 129 is preferably a low-k insulating film such as SiOF, SiOH or the like, for example. The secondinsulating film 162 and the thirdinsulating film 164 are oxide films, nitride films or high-k films, for example. - The parasitic capacitance between the gate electrode and the planar silicon layer is reduced by the first insulating
film 129. - With the above composition, downsizing and lowering of resistance in the semiconductor device are realized in the nMOS SGT according to the present embodiment, and in addition parasitic capacitance between multi-layer wiring is reduced. Through this, it is possible to avoid lowering of operation speeds accompanying downsizing of the SGT.
- In the nMOS SGT according to this embodiment, the thickness of the second
insulating film 162 is preferably thicker than the sum of the thickness of the firstgate insulating film 140 and the thickness of thefirst metal film 138. In this case, the firstgate insulating film 140 and thefirst metal film 138 are covered by the firstcolumnar silicon layer 232, thefirst polysilicon films film 129 and the secondinsulating film 162. - By using the above-described composition, the entirety of the
first metal film 138 is protected, so this film is not etched by a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture when forming the metal-silicon compound. - In addition, the length from the center of the first
columnar silicon layer 232 to the end of the firstplanar silicon layer 234 in the nMOS SGT according to the present embodiment is preferably larger than the sum of the length from the center to the sidewall of the firstcolumnar silicon layer 232, the thickness of the firstgate insulating film 140, the thickness of thefirst gate electrode 236 formed by thefirst metal film 138 and thefirst polysilicon films insulating film 164. - When the above-described composition is used, it is possible to form the first metal-
silicon compound 172 on the first n+type silicon layer 113 without the special addition of manufacturing processes. - In the first embodiment, an example was shown of a single columnar semiconductor layer, but in the second embodiment, an example is shown of a circuit composed of multiple columnar semiconductor layers.
- An inverter according to the second embodiment is provided with a pMOS SGT and an nMOS SGT.
- The
nMOS SGT 220 is provided with a firstplanar silicon layer 234 and a firstcolumnar silicon layer 232 formed on top of the firstplanar silicon layer 234. - A first n+
type silicon layer 113 is formed on the lower region of the firstcolumnar silicon layer 232 and the region of the firstplanar silicon layer 234 positioned below the firstcolumnar silicon layer 232, and a second n+type silicon layer 157 is formed on the upper region of the firstcolumnar silicon layer 232. In this embodiment, the first n+type silicon layer 113, for example, functions as a source scattering layer and the second n+type silicon layer 157 functions as a drain scattering layer. In addition, the area between the source scattering layer and the drawing scattering layer functions as a channel region. The firstcolumnar silicon layer 232 between the first n+type silicon layer 113 and the second n+type silicon layer 157 functioning as this channel region is called afirst silicon layer 114. - A first
gate insulating film 140 is formed surrounding the firstcolumnar silicon layer 232 functioning as the channel region. Thegate insulating film 140 may be, for example, an oxide film, a nitride film or a high-k film. Furthermore, afirst metal film 138 is formed surrounding this firstgate insulating film 140. Thefirst metal film 138 may be, for example, titanium, titanium nitride, tantalum or tantalum nitride.First polysilicon films first metal film 138. Thefirst metal film 138 and thefirst polysilicon films first gate electrode 236. Thus, by using metal as the gate electrode, it is possible to control depletion of the channel region while also lowering the resistance of the gate electrode. - In the present embodiment, a channel is formed in the
first silicon layer 114 by impressing a voltage on thefirst gate electrode 236 during operation. - In addition, a first metal-
silicon compound 172, a third metal-silicon compound 170 and a second metal-silicon compound 171 are formed on the first n+type silicon layer 113, thefirst gate electrode 236 and the second n+type silicon layer 157, respectively. The metal comprising the metal-silicon compounds may be Ni or Co, for example. Through these metal-silicon compounds, the first n+type silicon layer 113, thegate electrode 236 and the second n+type silicon layer 157 are connected to below-described contacts. Through this, the resistances of the gate, source and drain are lowered. - Furthermore, a first
insulating film 129 is formed between thefirst gate electrode 236 and the firstplanar silicon layer 234, a secondinsulating film 162 is formed in a sidewall shape on the upper sidewall of the firstcolumnar silicon layer 232 and above thefirst gate electrode 236, and a thirdinsulating film 164 is formed in a sidewall shape on the sidewall of thefirst gate electrode 236 and the first insulatingfilm 129. The firstinsulating film 129 is preferably a low-k insulating film such as SiOF, SiOH or the like, for example. The secondinsulating film 162 and the thirdinsulating film 164 are oxide films, nitride films or high-k films, for example. - The parasitic capacitance between the gate electrode and the planar silicon layer is reduced by the first insulating
film 129. - The
pMOS SGT 219 and is provided with a secondplanar silicon layer 233 and a secondcolumnar silicon layer 231 formed on top of the secondplanar silicon layer 233. - A first p+
type silicon layer 119 is formed on the lower region of the secondcolumnar silicon layer 231 and the region of the secondplanar silicon layer 233 positioned below the secondcolumnar silicon layer 231, and a second p+type silicon layer 159 is formed on the upper region of the secondcolumnar silicon layer 231. In this embodiment, the first p+type silicon layer 119, for example, functions as a source scattering layer and the second p+type silicon layer 159 functions as a drain scattering layer. In addition, the area between the source scattering layer and the drawing scattering layer functions as a channel region. The secondcolumnar silicon layer 231 between the first p+type silicon layer 119 and the second p+type silicon layer 159 functioning as this channel region is called asecond silicon layer 120. - A second
gate insulating film 139 is formed surrounding the secondcolumnar silicon layer 231 functioning as the channel region. The secondgate insulating film 139 may be, for example, an oxide film, a nitride film or a high-k film. Furthermore, asecond metal film 137 is formed surrounding this secondgate insulating film 139. Thesecond metal film 137 may be, for example, titanium, titanium nitride, tantalum or tantalum nitride.Second polysilicon films second metal film 137. Thesecond metal film 137 and thesecond polysilicon films second gate electrode 235. Thus, by using metal as the gate electrode, it is possible to control depletion of the channel region while also lowering the resistance of the gate electrode. - In the present embodiment, a channel is formed in the
second silicon layer 120 by impressing a voltage on thesecond gate electrode 235 during operation. - In addition, a fourth metal-
silicon compound 168, a fifth metal-silicon compound 170 and a sixth metal-silicon compound 169 are respectively formed on the first p+type silicon layer 119, thesecond gate electrode 235 and the second p+type silicon layer 159. As the metal comprising the metal-silicon compounds, Ni or Co may be used, for example. Through these metal-silicon compounds, the first p+type silicon layer 119, thesecond gate electrode 235 and the second p+type silicon layer 159 are connected to below-described contacts. Through this, the resistances of the gate, source and drain are lowered. - Furthermore, a fourth
insulating film 129 is formed between thesecond gate electrode 235 and the secondplanar silicon layer 233, a fifthinsulating film 161 is formed in a sidewall shape on the upper sidewall of the secondcolumnar silicon layer 231 and above thesecond gate electrode 235, and a sixthinsulating film 164 is formed in a sidewall shape on the sidewall of thesecond gate electrode 235 and the fourth insulatingfilm 129. The fourthinsulating film 129 is preferably a low-k insulating film such as SiOF, SiOH or the like, for example. - The parasitic capacitance between the gate electrode and the planar silicon layer is reduced by the fourth insulating
film 129. - The first n+
type silicon layer 113 is connected to acontact 230 via the first metal-silicon compound 172. Thecontact 230 is formed from abarrier metal layer 189 andmetal layers contact 230 is further connected to apower source wire 225. Thepower source wire 225 is composed of abarrier metal layer 216, ametal layer 217 and abarrier metal layer 218. - The second n+
type silicon layer 157 is connected to acontact 229 via the second metal-silicon compound 171. Thecontact 229 is composed of abarrier metal layer 188 andmetal layers contact 229 is further connected to anoutput wire 223. Theoutput wire 223 is composed of abarrier metal layer 213, ametal layer 214 and abarrier metal layer 215. - The
first gate electrode 236 is connected to acontact 228 via the third metal-silicon compound 170 and thesecond gate electrode 235 is connected to thecontact 228 via the fifth metal-silicon compound 170. Thecontact 228 is composed of abarrier metal layer 187 andmetal layers contact 228 is further connected to aninput wire 224. Theinput wire 224 is composed of abarrier metal layer 213, ametal layer 214 and abarrier metal layer 215. - The first p+
type silicon layer 119 is connected to acontact 226 via the fourth metal-silicon compound 168. Thecontact 226 is formed from abarrier metal layer 185 andmetal layers contact 226 is further connected to apower source wire 222. Thepower source wire 222 is composed of abarrier metal layer 207, ametal layer 208 and abarrier metal layer 209. - The second p+
type silicon layer 159 is connected to acontact 227 via the sixth metal-silicon compound 169. Thecontact 227 is composed of abarrier metal layer 186 andmetal layers contact 227 is further connected to anoutput wire 223. Theoutput wire 223 is composed of abarrier metal layer 213, ametal layer 214 and abarrier metal layer 215. - Through the above, an inverter circuit is composed from the
pMOS SGT 219 and thenMOS SGT 220. - Through this composition, lower resistance and downsizing of the semiconductor device are realized in the inverter circuit according to the present embodiment, and in addition, the parasitic capacitance between interlayer wires is reduced. Through this, it is possible to avoid slowing of operating speeds accompanying SGT downsizing.
- Through this composition, lower resistance and downsizing of the semiconductor device are realized in the inverter circuit according to the present embodiment, and in addition, the parasitic capacitance between interlayer wires is reduced. Through this, it is possible to avoid slowing of operating speeds accompanying SGT downsizing.
- In this embodiment, the first
gate insulating film 140 and thefirst metal film 138 are preferably materials that make thenMOS SGT 220 enhancement-type, and the secondgate insulating film 139 and thesecond metal film 137 are preferably materials that make thepMOS SGT 219 enhancement-type. The penetrating current that flows during operation of this inverter composed of thenMOS SGT 220 and thepMOS SGT 219 can thus be reduced. - In addition, in the nMOS SGT according to this embodiment, the thickness of the second
insulating film 162 is preferably thicker than the sum of the thickness of the firstgate insulating film 140 and the thickness of thefirst metal film 138. In this case, the firstgate insulating film 140 and thefirst metal film 138 are covered by the firstcolumnar silicon layer 232, thefirst polysilicon films film 129 and the secondinsulating film 162. - When the above-described composition is employed, the
first metal film 138 is protected in its entirety and thus is not etched by a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture when the metal-semiconductor compound is formed. - In addition, in the pMOS SGT according to this embodiment, the thickness of the second
insulating film 161 is preferably thicker than the sum of the thickness of the secondgate insulating film 139 and the thickness of thesecond metal film 137. In this case, the secondgate insulating film 139 and thesecond metal film 137 are covered by the secondcolumnar silicon layer 231, thesecond polysilicon films film 129 and the fifth insulatingfilm 161. - When the above-described composition is employed, the
second metal film 137 is protected in its entirety and thus is not etched by a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture when the metal-semiconductor compound is formed. - In addition, in the nMOS SGT according to this embodiment, the length from the center of the first
columnar silicon layer 232 to the end of the firstplanar silicon layer 234 is preferably larger than the sum of the length from the center to the sidewall of the firstcolumnar silicon layer 232, the thickness of the firstgate insulating film 140, the thickness of thefirst gate electrode 236 and the thickness of the thirdinsulating film 164. - When the above-described composition is employed, the first metal-
silicon compound 172 can be formed on the n+type silicon layer 113 without adding any special manufacturing processes. - In addition, in the pMOS SGT according to this embodiment, the length from the center of the second
columnar silicon layer 231 to the end of the secondplanar silicon layer 233 is preferably larger than the sum of the length from the center to the sidewall of the secondcolumnar silicon layer 231, the thickness of the secondgate insulating film 139, the thickness of thefirst gate electrode 235 and the thickness of the sixthinsulating film 164. - When the above-described composition is employed, the fourth metal-
silicon compound 168 can be formed on the p+type silicon layer 119 without adding any special manufacturing processes. - Next, one example of the manufacturing method for forming an inverter provided with SGTs according to the embodiments of the present invention will be described with reference to
FIGS. 2A through 88D . In these drawings, the same constituent elements are labeled with the same reference numbers. -
FIGS. 2A through 88D show an example of producing an SGT according to the present invention. In each drawing, part A shows a planar view, part B shows a cross-sectional view along line X-X′, part C shows a cross-sectional view along line Y1-Y1′ and part D shows a cross-sectional view along line Y2-Y2′. - First, as shown in
FIGS. 2A to 2D , anitride film 103 is formed on a substrate composed of asilicon oxide film 101 and asilicon layer 102. Here, the substrate may also be composed of silicon. In addition, an oxide film may be formed on the silicon layer and another silicon layer may be formed on the oxide film. In the present embodiment, an i-type silicon layer is used as thesilicon layer 102. When a p-type silicon layer and an n-type silicon layer are used in place of the i-type silicon layer, dopants are introduced into the part that becomes the channel of the SGT. In addition, a thin n-type silicon layer or a thin p-type silicon layer may be used in place of the i-type silicon layer. - Next, resists 104 and 105 for forming a hard mask for a columnar silicon layer are formed on the
nitride film 103, as shown inFIGS. 3A to 3D . - Next, the
nitride film 103 is etched andhard masks FIGS. 4A to 4D . - Next, the
silicon layer 102 is etched and columnar silicon layers 231 and 232 are formed, as shown inFIGS. 5A to 5D . - Next, the resists 104 and 105 are removed. Conditions on the substrate following removal are shown in
FIGS. 6A to 6D . - The surface of the
silicon layer 102 is oxidized and asacrificial oxide film 108 is formed, as shown inFIGS. 7A to 7D . By making this sacrificial oxide film, the surface of the silicon, such as carbon thrown in during silicon etching, is removed. - The
sacrificial oxide film 108 is removed through etching to form the shape shown inFIGS. 8A to 8D . - An
oxide film 109 is formed on the surface of thesilicon layer 102 and thehard masks FIGS. 9A to 9D . - The
oxide film 109 is etched and left in sidewall shape on the sidewall of the columnar silicon layers 231 and 232 to formsidewalls FIGS. 10A to 10D . When forming an n+ type silicon layer by injecting dopants surrounding the bottom of thecolumnar silicon layer 231, thesesidewalls - A resist 112 for injecting dopants into the bottom of the
columnar silicon layer 232 is formed surrounding thecolumnar silicon layer 231, as shown inFIGS. 11A to 11D . - As indicated by the arrows in
FIGS. 12B and 12C , arsenic, for example, is injected into thesilicon layer 102 in the region where the nMOS SGT is to be formed, thereby forming an n+type silicon layer 113 surrounding the bottom of thecolumnar silicon layer 232. At this time, the part of thesilicon layer 102 covered by thehard mask 107 and thesidewall 111 does not become the n+ type silicon layer, comprising instead afirst silicon layer 114 region in thecolumnar silicon layer 232. - The resist 112 is removed. Conditions on the substrate following removal are shown in
FIGS. 13A to 13D . - The
sidewalls FIGS. 14A to 14D . - Annealing is accomplished and the injected dopants, here arsenic, are activated. Through this, the injected dopants are scattered to the bottom of the
columnar silicon layer 232, as shown inFIGS. 15A to 15D . Through this, even the bottom of thecolumnar silicon layer 231 becomes an n+ type silicon layer and forms a portion of the n+type silicon layer 113. - An
oxide film 115 is formed on thesilicon layer 102, thehard masks type silicon layer 113, as shown inFIGS. 16A to 16D . - The
oxide film 115 is etched, leaving behind a sidewall shape in the sidewall of the columnar silicon layers 231 and 232 to formsidewalls FIGS. 17A to 17D . When forming a p+ type silicon layer by injecting dopants surrounding the bottom of thecolumnar silicon layer 231, these sidewalls prevent dopants from entering the channel, making it possible to control fluctuations in the threshold voltage of the SGT. - A resist 118 is formed surrounding the
columnar silicon layer 231 in order to inject dopants into the bottom of thecolumnar silicon layer 232, as shown inFIGS. 18A to 18D . - As indicated by the arrows in
FIGS. 19B and 19D , boron, for example, is injected into thesilicon layer 102 in the region where the pMOS SGT is to be formed, thereby forming a p+type silicon layer 119 surrounding the bottom of thecolumnar silicon layer 231. At this time, the part of thesilicon layer 102 covered by thehard mask 106 and thesidewall 116 does not become the p+ type silicon layer, comprising instead asecond silicon layer 120 region in thecolumnar silicon layer 231. - The resist 118 is removed. Conditions on the substrate following removal are shown in
FIGS. 20A to 20D . - The
sidewalls FIGS. 21A to 21D . - Annealing is accomplished and the injected dopant, here boron, is activated. Through this, the injected dopant is scattered to the bottom of the
columnar silicon layer 231, as shown inFIGS. 22A to 22D . Through this, even the bottom of thecolumnar silicon layer 231 becomes a p+ type silicon layer and forms a portion of the p+type silicon layer 119. - An
oxide film 121 is formed on the surface of thehard masks type silicon layer 113 and the p+type silicon layer 119, as shown inFIGS. 23A to 23D . Thisoxide film 121 protects thefirst silicon layer 114 and thesecond silicon layer 120 from resist for forming a planar silicon layer later. - Resists 122 and 123 for forming a planar silicon layer are formed. The resists 122 and 123 are formed so as to cover the
second silicon layer 120 and the area surrounding the bottom thereof, and thefirst silicon layer 114 and the area surrounding the bottom thereof, respectively, as shown inFIGS. 24A to 24D . - The
oxide film 121 is etched and partitioned intooxide films FIGS. 25A to 25D . - Portions of the p+
type silicon layer 119 and of the n+type silicon layer 113 are etched to form planar silicon layers 233 and 234, as shown inFIGS. 26A and 26D . Theplanar silicon layer 233 is the planar portion of the p+type silicon layer 119 arranged surrounding the area immediately below thesecond silicon layer 120. In addition, theplanar silicon layer 234 is the planar portion of the n+type silicon layer 113 arranged surrounding the area immediately below thefirst silicon layer 114. - The resists 122 and 123 are removed. Conditions on the substrate following removal are shown in
FIGS. 27A to 27D . - An
oxide film 123 is formed on the surface of the resists 122 and 123 and the planar silicon layers 233 and 244, as shown inFIGS. 28A to 28D . - CMP (Chemical Mechanical Polishing) is accomplished, the
oxide film 126 is planarized and thehard masks FIGS. 29A to 29D . - The
oxide films oxide film 126 buried between the planar silicon layers 119 and 133, as shown inFIGS. 30A to 30D . - An
oxide film 128 is formed on the result of the above processes. At this time, theoxide film 128 is formed thickly on the n+type silicon layer 113, the p+type silicon layer 119, theoxide film 126 and thehard masks oxide film 128 is formed thinly on the sidewalls of the columnar silicon layers 231 and 232, as shown inFIGS. 31A to 31D . - The
oxide film 128 formed on the sidewalls of the columnar silicon layers 231 and 232 is removed through etching. The etching is preferably isotropic etching. Theoxide film 128 is formed thickly on the n+type silicon layer 113, the p+type silicon layer 119, theoxide film 126 and thehard masks oxide film 128 is formed thinly on the sidewalls of the columnar silicon layers 213 and 232, and consequently, theoxide film 128 remains on the n+type silicon layer 113, the p+type silicon layer 119 and theoxide film 126, forming an insulatingfilm 129, as shown inFIGS. 32A to 32D . In addition, in thiscase oxide films hard masks - By means of the insulating
film 129, it is possible to reduce the parasitic capacitance between the gate electrode and the planar silicon layer. - A
gate insulating film 132 is formed so as to cover at least thefirst silicon layer 114 and the surface of the surroundings of the bottom thereof and thesecond silicon layer 120 and the surface of the surroundings of the bottom thereof, as shown inFIGS. 33A to 33D . Thegate insulating film 132 is a film containing at least one out of an oxide film, a nitride film and a high-k film. In addition, prior to forming the gate insulating film, hydrogen atmosphere annealing or epitaxial growth may be accomplished on the columnar silicon layers 231 and 232. - A
metal film 133 is formed on the surface of thegate insulating film 132, as shown inFIGS. 34A to 34D . The metal film is preferably a film containing titanium, titanium nitride, tantalum or tantalum nitride. By using the metal film, it is possible to control depletion of the channel region and it is also possible to lower the resistance of the gate electrode. It is necessary to use a manufacturing process for later processes so as to control metal contamination by the metal gate electrode. - A
polysilicon film 134 is formed on the surface of themetal film 133, as shown inFIGS. 35A to 35D . In order to control metal contamination, it is preferable to form thepolysilicon film 134 using normal-pressure CVD. - The
polysilicon film 134 is etched to formpolysilicon films FIGS. 36A to 36D . - The
metal film 133 is etched. The metal film on the sidewalls of the columnar silicon layers 231 and 232 is protected by thepolysilicon films metal films FIGS. 37A to 37D . - The
gate insulating film 132 is etched. The gate insulating film on the sidewalls of the columnar silicon layers 231 and 232 is protected by thepolysilicon films gate insulating film 140 remaining in sidewall shape, as shown inFIGS. 38A to 38D . - A
polysilicon film 141 is formed on the surface where circuits are formed, as shown inFIGS. 39A to 39D . In order to control metal contamination, thepolysilicon film 141 is preferably formed using normal-pressure CVD. - When a high-k film is used in the
gate insulating films - Through this
polysilicon film 141, thegate insulating film 139 and themetal film 137 are covered by thecolumnar silicon layer 231, thepolysilicon films film 129 and thehard mask 106. - In addition, the
gate insulating film 140 and themetal film 138 are covered by thecolumnar silicon layer 232, thepolysilicon films film 129 and thehard mask 107. - That is to say, the
gate insulating films metal films film 129 and thehard masks gate insulating films metal films - In order to achieve the aforementioned objectives, it would be fine to form a structure in which the metal film is thickly formed, etching is accomplished to leave a sidewall shape and the gate insulating film is etched, following which a polysilicon film is formed and the gate insulating film and the metal film are covered by the columnar silicon layer, the polysilicon layer, the insulating film and the hard mask.
- A
polysilicon film 142 is formed on the surface where the circuits are formed, as shown inFIGS. 40A to 40D . In order to bury thecolumnar silicon film 129 and thehard masks - CMP (chemical mechanical polishing) is accomplished with the
oxide films FIGS. 41A to 41D , and thepolysilicon film 142 is planarized, as shown inFIGS. 41A to 41D . Because the polysilicon film is planarized, it is possible to control metal contamination of the CMP device. - The
oxide films FIGS. 42A to 42D - The
polysilicon film 142 is etched and thepolysilicon film 142 is removed to the top edge of the region where the gate electrode and thegate insulating films FIGS. 43A to 43D . Through this etching, the gate length of the SGT is determined. - The
metal films FIGS. 44A to 44D . - The
gate insulating films FIGS. 45A to 45D - An
oxide film 144 is formed on the surface where the circuits are formed, as shown inFIGS. 46A to 46D . Because the gate electrode top surface is protected by thisoxide film 144 from the wet treatment or dry treatment accomplished in later processes, it is possible to control fluctuations in gate length, that is to say variance in gate length, and damage to thegate insulating films metal films - A
nitride film 145 is formed on the surface of theoxide film 144, as shown inFIGS. 47A to 47D . - The
nitride film 145 and theoxide film 144 are etched to form theoxide films nitride films FIGS. 48A to 48D . - The sum of the film thicknesses of the
oxide film 148 and thenitride film 146 remaining in sidewall shape is the film thickness of thegate electrode 235 later, and the film thickness of theoxide film 149 and thenitride film 147 remaining in sidewall shape is the film thickness of thegate electrode 236 later, so by adjusting the film formation thicknesses and etching conditions of theoxide film 144 and thenitride film 145, it is possible to form a gate electrode of the desired film thickness. - In addition, it is preferable for the sum of the radius of the
columnar silicon layer 231 and the sum of the film thicknesses of theoxide film 148 and thenitride film 146 remaining in sidewall shape to be greater than the radius of the outer circumference of the cylinder composed by thegate insulating film 139 and themetal film 137, and for the sum of the radius of thecolumnar silicon layer 232 and the sum of the film thicknesses of theoxide film 149 and thenitride film 147 remaining in sidewall shape to be larger than the diameter of the outer circumference of the cylinder composed by thegate insulating film 140 and themetal film 138. At this time, because themetal films - A resist 150 for forming a
gate wire 221 is formed on thepolysilicon layer 142 at least between thefirst silicon layer 114 and thesecond silicon layer 120, as shown inFIGS. 49A to 49D . - The
polysilicon films gate electrodes gate wire 221, as shown inFIGS. 50A to 50D . - The
gate electrode 235 is composed of themetal film 137 and thepolysilicon films gate electrode 236 is composed of themetal film 138 and thepolysilicon films - The
gate wire 221 connecting thegate electrodes polysilicon films - The insulating
film 129 is etched and the surfaces of the p+type silicon layer 119 and the n+type silicon layer 113 are exposed, as shown inFIGS. 51A to 51D . - The resist 150 is removed. Conditions on the substrate following removal are shown in
FIGS. 52A to 52D . - Oxidation is accomplished to form
oxide films FIGS. 53A to 53D . The p+type silicon layer 159, the n+type silicon layer 157, thegate electrodes gate wire 221 are protected by these nitride films from etching through wet treatment or dry treatment during etching of thehard masks nitride films - The
hard masks nitride films FIGS. 54A to 54D . Because the top surface of the gate electrodes is protected from the wet treatment or dry treatment by theoxide films gate insulating films metal films gate insulating films metal films polysilicon nitride films film 129, so metal contamination of the nitride film wet etching device is controlled. - The
oxide films FIGS. 55A to 55D . - A resist 156 for forming an n+ type silicon layer on the
columnar silicon layer 232 through dopant injection is formed surrounding thecolumnar silicon layer 231, as shown inFIGS. 56A to 56D . In advance of this process, a thin oxide film may be formed as a through (?) oxide film for dopant injection. - As indicated by the arrows in
FIGS. 57B and 57C , arsenic, for example, is injected into the top of thecolumnar silicon layer 232 to form an n+type silicon layer 157. The angle of injecting the arsenic is preferably 10 degrees to 60 degrees, and more preferably the large angle of 60 degrees, where a line orthogonal to the substrate is taken as 0 degrees. By injecting the arsenic at a large angle, the n+ type silicon layers 157 and thegate electrode 236 are given an overlap and it is possible to minimize this overlap. - The resist 156 is removed. Conditions on the substrate following removal are shown in
FIGS. 58A to 58D . - Heat treatment is accomplished and the arsenic is activated. Conditions on the substrate following activation is shown in
FIGS. 59A to 59D . - A resist 158 for forming a p+ type silicon layer on the upper part of the
columnar silicon layer 231 through dopant injection is formed surrounding thecolumnar silicon layer 232, as shown byFIGS. 60A to 60D . - As indicated by
FIGS. 61B and 61D , boron, for example, is injected into the upper part of thecolumnar silicon layer 231 to form a p+type silicon layer 159. The angle of injecting the boron is preferably 10 degrees to 60 degrees, and more preferably the large angle of 60 degrees, where a line orthogonal to the substrate is taken as 0 degrees. By injecting the boron at a large angle, the p+ type silicon layers 159 and thegate electrode 235 are given an overlap and it is possible to minimize this overlap. - The resist 158 is removed. Conditions on the substrate following removal are shown in
FIGS. 62A to 62D . - Heat treatment is accomplished and the boron is activated. Conditions on the substrate following activation is shown in
FIGS. 63A to 63D . By separately undertaking heat treatment of the n+type silicon layer 157 and heat treatment of the p+type silicon layer 159, it is possible to easily optimize heat treatment conditions for each, so it is possible to control the short channel effect and to control leak current. - A
nitride film 160 is formed on the surface where the circuits are formed, as shown inFIGS. 64A to 64D . - The
nitride film 160 is etched to form an insulatingfilm 161 composed of nitride film formed in a sidewall shape on the upper sidewall of thecolumnar silicon layer 231 and the upper part of thegate electrode 235, an insulatingfilm 162 composed of a nitride film formed in a sidewall shape on the upper sidewall of thecolumnar silicon layer 232 and the upper part of thegate electrode 236, an insulatingfilm 164 composed of a nitride film formed in a sidewall shape on the sidewalls of the insulatingfilm 129 and thegate electrodes film 163 composed of a nitride film formed in a sidewall shape on the sidewall of the p+type silicon layer 119 and an insulatingfilm 165 composed of a nitride film formed in a sidewall shape on the sidewall of the n+type silicon layer 113, as shown inFIGS. 65A to 65D . - By making the thicknesses of the insulating
films gate insulating films metal films gate insulating film 140 and themetal film 138 are covered by thecolumnar silicon layer 232, the polysilicon layers 136 and 152, the insulatingfilm 129 and the insulatingfilm 162, and in addition, thegate insulating film 129 and themetal film 137 are covered by thecolumnar silicon layer 231, the polysilicon layers 135 and 151, the insulatingfilm 129 and the insulatingfilm 161. - A resist 166 for forming a deep n+ type silicon layer in the direction orthogonal to the substrate on the upper part of the
columnar silicon layer 232 through dopant injection is formed surrounding thecolumnar silicon layer 231, as shown inFIGS. 66A to 66D . By making this an n+ type silicon layer deep in the direction orthogonal to the substrate, it is possible to form a metal-silicon compound later on the n+ type silicon layer. If this were an n+ type silicon layer shallow in the direction orthogonal to the substrate, the metal-silicon compound formed later would be formed on the n+ type silicon layer and the first silicon layer and would become a source of leak current. - As shown in
FIGS. 67B and 67C , arsenic, for example, is injected into the upper part of thecolumnar silicon layer 232 and the n+type silicon layer 157 is made deep in the direction orthogonal to the substrate. The angle of injecting the arsenic is preferably a low angle of 0 degrees to 7 degrees, where the line orthogonal to the substrate is taken to be 0 degrees. By injecting the arsenic at a low angle, it is possible to form an n+ type silicon layer deep in the direction orthogonal to the substrate on the upper part of the columnar silicon layer of the nMOS SGT. - The resist 166 is removed. Conditions on the substrate following removal are shown in
FIGS. 68A to 68D . - A resist 167 for forming a deep p+ type silicon layer in the direction orthogonal to the substrate on the upper part of the
columnar silicon layer 231 through dopant injection is formed surrounding thecolumnar silicon layer 232, as shown inFIGS. 69A to 69D . By making this a p+ type silicon layer deep in the direction orthogonal to the substrate, it is possible to form a metal-silicon compound later on the p+ type silicon layer. If this were a p+ type silicon layer shallow in the direction orthogonal to the substrate, the metal-silicon compound formed later would be formed on the p+ type silicon layer and the second silicon layer and would become a source of leak current. - As shown in
FIGS. 70B and 70D , boron, for example, is injected into the upper part of thecolumnar silicon layer 231 and the p+type silicon layer 159 is made deep in the direction orthogonal to the substrate. The angle of injecting the boron is preferably a low angle of 0 degrees to 7 degrees, where the line orthogonal to the substrate is taken to be 0 degrees. By injecting the boron at a low angle, it is possible to form a p+ type silicon layer deep in the direction orthogonal to the substrate on the upper part of the columnar silicon layer of the pMOS SGT. - The resist 167 is removed. Conditions on the substrate following removal are shown in
FIGS. 71A to 71D . - Heat treatment is accomplished in order to activate the dopant. Conditions following activation are shown in
FIGS. 72A to 72D . - By sputtering a metal such as Ni or Co and adding heat treatment, a metal-silicon compound is formed on the surface of the p+
type silicon layer 119, the p+type silicon layer 159, thegate electrode 235, the n+type silicon layer 113, the n+type silicon layer 157 and thegate electrode 236, and by removing the unreacted metal film using a sulfuric acid hydrogen peroxide mixture or an ammonia hydrogen peroxide mixture, a metal-silicon compound 168 is formed on the surface of the p+type silicon layer 119, a metal-silicon compound 169 is formed on the surface of the p+type silicon layer 159, a metal-silicon compound 170 is formed on the surface of thegate electrode 235, thegate wire 221 and thegate electrode 236, a metal-silicon compound 172 is formed on the surface of the n+type silicon layer 113, and a metal-silicon compound 171 is formed on the surface of the n+type silicon layer 157. - The
gate insulating film 140 and themetal film 138 are covered by thecolumnar silicon layer 232, thepolysilicon films film 129 and the insulatingfilm 162, and in addition, thegate insulating film 139 and themetal film 137 are covered by thecolumnar silicon layer 231, thepolysilicon films film 129 and the insulatingfilm 161, so themetal films - In other words, by using the structure of the present invention, it is possible to use metal in the gate electrode, it is possible to control depletion of the channel region, it is possible to lower the resistance of the gate electrode and it is possible to lower the resistance of the gate, source and drain through a metal-silicon compound.
- Normally, the natural oxide film on the surface of the silicon layer is removed by hydrofluoric acid as a pre-treatment prior to sputtering the metal such as Ni or Co. At this time, the insulating
film 129 composed of an oxide film is protected from the hydrofluoric acid by the insulatingfilm 164 composed of a nitride film formed in a sidewall shape on the sidewall. - A
contact stopper 173 of nitride film is formed, aninterlayer insulating film 174 is deposited and planarization is undertaken, as shown inFIGS. 74A to 74D . - A resist 175 for forming contact holes is formed above the columnar silicon layers 231 and 232, as shown in
FIGS. 75A to 75D . - The
interlayer insulating film 174 is etched to form contact holes 176 and 177 above thecolumnar silicon layer 232, as shown inFIGS. 76A to 76D . - The resist 175 is removed. Conditions on the substrate following removal are shown in
FIGS. 77A to 77D . - A resist 178 for forming contact holes above the planar silicon layers 233 and 234 and above the
gate wire 221 is formed, as shown inFIGS. 78A to 78D . - The
interlayer insulating film 174 is etched to form contact holes 179, 180 and 181 above the planar silicon layers 233 and 234 and above thegate wire 221, respectively, as shown inFIGS. 79A to 79D . - Because the contact holes 176 and 177 above the
columnar silicon gate wire 221 are formed through different processes, the etching conditions for forming the contact holes 176 and 177 above thecolumnar silicon gate wire 221 can each be optimized. - The resist 178 is removed. Conditions on the substrate following removal are shown in
FIGS. 80A to 80D . - A
contact stopper 173 is etched below the contact holes 179, 176, 180, 177 and 181. Conditions on the substrate following etching are shown inFIGS. 81A to 81D . - After a
barrier metal layer 182 is deposited on the surface where the circuits are formed, ametal 183 is deposited on the top thereof, as shown inFIGS. 82A to 82D . - A
metal 184 is deposited to bury the gap, as shown inFIGS. 83A to 83D . - The
metals barrier metal layer 182 are planarized and etched to formcontacts FIGS. 84A to 84D . Thecontact 226 is composed of abarrier metal layer 185 andmetal layers contact 227 is composed of abarrier metal layer 186 andmetal layers contact 228 is composed of abarrier metal layer 187 andmetal layers contact 229 is composed of abarrier metal layer 188 andmetal layers contact 230 is composed of abarrier metal layer 189 andmetal layers - A
barrier metal layer 200, ametal layer 201 and abarrier metal layer 202 are deposited in this order on the planarized surface, as shown inFIGS. 85A to 85D . - Resists 203, 204, 205 and 206 for forming a power source wire, an input wire and an output wire are formed, as shown in
FIGS. 86A to 86D . - The
barrier metal layer 202, themetal 201 and thebarrier metal layer 200 are etched to formpower source wires input wire 224 and anoutput wire 223, as shown inFIGS. 87A to 87D . Thepower source wire 222 is composed of abarrier metal layer 207, ametal layer 208 and abarrier metal layer 209. Thepower source wire 225 is composed of abarrier metal layer 216, ametal layer 217 and abarrier metal layer 218. Theinput wire 224 is composed of abarrier metal layer 213, ametal layer 214 and abarrier metal layer 215. Theoutput wire 223 is composed of abarrier metal layer 210, ametal layer 211 and abarrier metal layer 212. - The resists 203, 204, 205 and 206 are removed. Conditions on the substrate following removal are shown in
FIGS. 88A to 88D . - With the above production method, it is possible to produce a semiconductor device with a small parasitic capacitance between the gate electrode and the planar silicon layers because of the first and fourth insulating films.
- Having described and illustrated the principles of this application by reference to one (or more) preferred embodiment(s), it should be apparent that the preferred embodiment(s) may be modified in arrangement and detail without departing from the principles disclosed herein and that it is intended that the application be construed as including all such modifications and variations insofar as they come within the spirit and scope of the subject matter disclosed herein.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/191,853 US20160308013A1 (en) | 2010-06-15 | 2016-06-24 | Semiconductor device and production method |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US35486610P | 2010-06-15 | 2010-06-15 | |
JP2010136470A JP5087655B2 (en) | 2010-06-15 | 2010-06-15 | Semiconductor device and manufacturing method thereof |
JP2010136470 | 2010-06-15 | ||
US13/116,506 US9153697B2 (en) | 2010-06-15 | 2011-05-26 | Surrounding gate transistor (SGT) structure |
US14/831,303 US20150357428A1 (en) | 2010-06-15 | 2015-08-20 | Surrounding gate transistor (sgt) structure |
US15/191,853 US20160308013A1 (en) | 2010-06-15 | 2016-06-24 | Semiconductor device and production method |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/831,303 Division US20150357428A1 (en) | 2010-06-15 | 2015-08-20 | Surrounding gate transistor (sgt) structure |
Publications (1)
Publication Number | Publication Date |
---|---|
US20160308013A1 true US20160308013A1 (en) | 2016-10-20 |
Family
ID=45095538
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/116,506 Active 2032-11-02 US9153697B2 (en) | 2010-06-15 | 2011-05-26 | Surrounding gate transistor (SGT) structure |
US14/831,303 Abandoned US20150357428A1 (en) | 2010-06-15 | 2015-08-20 | Surrounding gate transistor (sgt) structure |
US15/191,853 Abandoned US20160308013A1 (en) | 2010-06-15 | 2016-06-24 | Semiconductor device and production method |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/116,506 Active 2032-11-02 US9153697B2 (en) | 2010-06-15 | 2011-05-26 | Surrounding gate transistor (SGT) structure |
US14/831,303 Abandoned US20150357428A1 (en) | 2010-06-15 | 2015-08-20 | Surrounding gate transistor (sgt) structure |
Country Status (6)
Country | Link |
---|---|
US (3) | US9153697B2 (en) |
JP (1) | JP5087655B2 (en) |
KR (1) | KR101253419B1 (en) |
CN (1) | CN102290441B (en) |
SG (1) | SG177062A1 (en) |
TW (1) | TW201145516A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11742400B2 (en) * | 2018-08-14 | 2023-08-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field effect transistor (FinFET) device structure with deep contact structure |
Families Citing this family (74)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8183628B2 (en) | 2007-10-29 | 2012-05-22 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor structure and method of fabricating the semiconductor structure |
US8188537B2 (en) | 2008-01-29 | 2012-05-29 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor device and production method therefor |
JP5317343B2 (en) | 2009-04-28 | 2013-10-16 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and manufacturing method thereof |
US8598650B2 (en) * | 2008-01-29 | 2013-12-03 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor device and production method therefor |
JP4577592B2 (en) | 2009-04-20 | 2010-11-10 | 日本ユニサンティスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP4530098B1 (en) | 2009-05-29 | 2010-08-25 | 日本ユニサンティスエレクトロニクス株式会社 | Semiconductor device |
JP5356970B2 (en) | 2009-10-01 | 2013-12-04 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device |
JP4912513B2 (en) * | 2010-03-08 | 2012-04-11 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Solid-state imaging device |
US8487357B2 (en) | 2010-03-12 | 2013-07-16 | Unisantis Electronics Singapore Pte Ltd. | Solid state imaging device having high sensitivity and high pixel density |
JP5066590B2 (en) | 2010-06-09 | 2012-11-07 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and manufacturing method thereof |
JP5087655B2 (en) | 2010-06-15 | 2012-12-05 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and manufacturing method thereof |
US8564034B2 (en) | 2011-09-08 | 2013-10-22 | Unisantis Electronics Singapore Pte. Ltd. | Solid-state imaging device |
US8669601B2 (en) | 2011-09-15 | 2014-03-11 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing semiconductor device and semiconductor device having pillar-shaped semiconductor |
US8759178B2 (en) | 2011-11-09 | 2014-06-24 | Unisantis Electronics Singapore Pte. Ltd. | Method for manufacturing semiconductor device and semiconductor device |
US10438836B2 (en) | 2011-11-09 | 2019-10-08 | Unisantis Electronics Singapore Pte. Ltd. | Method for manufacturing a semiconductor device |
US8772175B2 (en) | 2011-12-19 | 2014-07-08 | Unisantis Electronics Singapore Pte. Ltd. | Method for manufacturing semiconductor device and semiconductor device |
US8916478B2 (en) * | 2011-12-19 | 2014-12-23 | Unisantis Electronics Singapore Pte. Ltd. | Method for manufacturing semiconductor device and semiconductor device |
US8748938B2 (en) | 2012-02-20 | 2014-06-10 | Unisantis Electronics Singapore Pte. Ltd. | Solid-state imaging device |
US8829601B2 (en) | 2012-05-17 | 2014-09-09 | Unisantis Electronics Singapore Pte. Ltd. | Semiconductor device |
JP5752810B2 (en) * | 2012-05-17 | 2015-07-22 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device |
US9166043B2 (en) | 2012-05-17 | 2015-10-20 | Unisantis Electronics Singapore Pte. Ltd. | Semiconductor device |
US9012981B2 (en) | 2012-05-17 | 2015-04-21 | Unisantis Electronics Singapore Pte. Ltd. | Semiconductor device |
US8877578B2 (en) | 2012-05-18 | 2014-11-04 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing semiconductor device and semiconductor device |
US8697511B2 (en) | 2012-05-18 | 2014-04-15 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing semiconductor device and semiconductor device |
US8836051B2 (en) | 2012-06-08 | 2014-09-16 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing semiconductor device and semiconductor device |
JP5749818B2 (en) * | 2012-06-08 | 2015-07-15 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device manufacturing method and semiconductor device |
US8742492B2 (en) | 2012-08-07 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device with a vertical gate structure |
SG11201500829PA (en) * | 2012-09-28 | 2015-03-30 | Unisantis Elect Singapore Pte | Semiconductor device manufacturing method and semiconductor device |
US9082838B2 (en) | 2012-09-28 | 2015-07-14 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing a semiconductor device and semiconductor device |
US8829619B2 (en) | 2012-10-09 | 2014-09-09 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing semiconductor device and semiconductor device |
US9000513B2 (en) | 2012-11-12 | 2015-04-07 | Unisantis Electronics Singapore Pte. Ltd. | Method for manufacturing a semiconductor device and semiconductor device with surrounding gate transistor |
US20150357336A1 (en) * | 2013-01-09 | 2015-12-10 | Ps5 Luxco S.A.R.L. | Semiconductor device and method of manufacturing the same |
US9029940B2 (en) * | 2013-01-18 | 2015-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical tunneling field-effect transistor cell |
US9536977B2 (en) * | 2013-01-18 | 2017-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical tunneling field-effect transistor cell and fabricating the same |
US9190484B2 (en) * | 2013-01-18 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical tunneling field-effect transistor cell and fabricating the same |
US9041095B2 (en) | 2013-01-24 | 2015-05-26 | Unisantis Electronics Singapore Pte. Ltd. | Vertical transistor with surrounding gate and work-function metal around upper sidewall, and method for manufacturing the same |
US20140264557A1 (en) * | 2013-03-15 | 2014-09-18 | International Business Machines Corporation | Self-aligned approach for drain diffusion in field effect transistors |
SG11201504337QA (en) * | 2013-04-19 | 2015-07-30 | Unisantis Elect Singapore Pte | Method for producing semiconductor device, and semiconductor device |
KR20140142887A (en) * | 2013-06-05 | 2014-12-15 | 에스케이하이닉스 주식회사 | 3 Dimension Semiconductor Device And Method of Manufacturing The same |
WO2014199481A1 (en) | 2013-06-13 | 2014-12-18 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device having sgt and manufacturing method therefor |
US9640645B2 (en) | 2013-09-05 | 2017-05-02 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device with silicide |
JP5639317B1 (en) * | 2013-11-06 | 2014-12-10 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device having SGT and manufacturing method thereof |
US10026658B2 (en) * | 2014-04-14 | 2018-07-17 | Taiwan Semiconductor Manufacturing Company Limited | Methods for fabricating vertical-gate-all-around transistor structures |
US10418271B2 (en) * | 2014-06-13 | 2019-09-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming isolation layer |
US9755033B2 (en) * | 2014-06-13 | 2017-09-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of forming vertical structure |
US9614091B2 (en) * | 2014-06-20 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structure and method for fabricating the same |
US9318447B2 (en) | 2014-07-18 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method of forming vertical structure |
US9893159B2 (en) * | 2014-08-15 | 2018-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor, integrated circuit and method of fabricating the same |
US9985026B2 (en) | 2014-08-15 | 2018-05-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor, integrated circuit and method of fabricating the same |
JP5903139B2 (en) * | 2014-08-22 | 2016-04-13 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device manufacturing method and semiconductor device |
US9735245B2 (en) * | 2014-08-25 | 2017-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Recessed salicide structure to integrate a flash memory device with a high κ, metal gate logic device |
US9911848B2 (en) * | 2014-08-29 | 2018-03-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical transistor and method of manufacturing the same |
US9871111B2 (en) * | 2014-09-18 | 2018-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
JP5928566B2 (en) * | 2014-12-10 | 2016-06-01 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device manufacturing method and semiconductor device |
US9412817B2 (en) | 2014-12-19 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide regions in vertical gate all around (VGAA) devices and methods of forming same |
US10950722B2 (en) * | 2014-12-31 | 2021-03-16 | Stmicroelectronics, Inc. | Vertical gate all-around transistor |
US9349859B1 (en) * | 2015-01-29 | 2016-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Top metal pads as local interconnectors of vertical transistors |
US9564493B2 (en) | 2015-03-13 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same |
US10134863B2 (en) * | 2015-06-15 | 2018-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical semiconductor device structure and method of forming |
US10410932B2 (en) | 2015-10-09 | 2019-09-10 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing pillar-shaped semiconductor device |
US10229916B2 (en) * | 2015-10-09 | 2019-03-12 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing pillar-shaped semiconductor device |
US9805935B2 (en) * | 2015-12-31 | 2017-10-31 | International Business Machines Corporation | Bottom source/drain silicidation for vertical field-effect transistor (FET) |
US9722048B1 (en) * | 2016-03-28 | 2017-08-01 | International Business Machines Corporation | Vertical transistors with reduced bottom electrode series resistance |
US9711511B1 (en) * | 2016-06-27 | 2017-07-18 | Globalfoundries Inc. | Vertical channel transistor-based semiconductor memory structure |
US20170373071A1 (en) * | 2016-06-27 | 2017-12-28 | Globalfoundries Inc. | Vertical channel transistor-based semiconductor structure |
US11088033B2 (en) * | 2016-09-08 | 2021-08-10 | International Business Machines Corporation | Low resistance source-drain contacts using high temperature silicides |
US10840354B2 (en) * | 2017-02-06 | 2020-11-17 | International Business Machines Corporation | Approach to bottom dielectric isolation for vertical transport fin field effect transistors |
CN108110059B (en) * | 2017-12-27 | 2023-03-14 | 中国科学院微电子研究所 | Semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
US10297668B1 (en) * | 2018-01-22 | 2019-05-21 | International Business Machines Corporation | Vertical transport fin field effect transistor with asymmetric channel profile |
CN109768087B (en) * | 2018-12-20 | 2021-04-27 | 中国科学院微电子研究所 | Semiconductor device, method of manufacturing the same, integrated circuit, and electronic apparatus |
CN110120424B (en) * | 2019-05-08 | 2022-03-22 | 中国科学院微电子研究所 | Semiconductor device, method of manufacturing the same, integrated circuit, and electronic apparatus |
KR20210099841A (en) * | 2020-02-05 | 2021-08-13 | 삼성전자주식회사 | Image Sensor Including a Transistor Having a Protruding Channel Electrode |
CN113363211B (en) * | 2020-03-05 | 2023-10-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
US11908907B2 (en) * | 2020-12-11 | 2024-02-20 | International Business Machines Corporation | VFET contact formation |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100207201A1 (en) * | 2008-01-29 | 2010-08-19 | Fujio Masuoka | Semiconductor device and production method therefor |
US20100219464A1 (en) * | 2008-02-15 | 2010-09-02 | Fujio Masuoka | Production method for semiconductor device |
Family Cites Families (163)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5864779U (en) | 1981-10-26 | 1983-05-02 | 日産ディーゼル工業株式会社 | Automobile emergency door opening device |
JPS6070757A (en) | 1983-09-28 | 1985-04-22 | Hitachi Ltd | Semiconductor integrated circuit |
US5017977A (en) | 1985-03-26 | 1991-05-21 | Texas Instruments Incorporated | Dual EPROM cells on trench walls with virtual ground buried bit lines |
JPS6245058A (en) | 1985-08-22 | 1987-02-27 | Nec Corp | Semiconductor device and its manufacture |
JPS62190751A (en) | 1986-02-17 | 1987-08-20 | Nec Corp | Semiconductor device |
JPS6337633A (en) | 1986-07-31 | 1988-02-18 | Nec Corp | Semiconductor integrated circuit device |
JPH0722182B2 (en) | 1986-12-23 | 1995-03-08 | 松下電子工業株式会社 | Complementary semiconductor device |
JPS6489560A (en) | 1987-09-30 | 1989-04-04 | Sony Corp | Semiconductor memory |
JPH01175775A (en) | 1987-12-29 | 1989-07-12 | Sharp Corp | Photo-driven mos semiconductor device |
JPH0266969A (en) | 1988-08-31 | 1990-03-07 | Nec Corp | Semiconductor integrated circuit device |
JP2703970B2 (en) | 1989-01-17 | 1998-01-26 | 株式会社東芝 | MOS type semiconductor device |
JP3057661B2 (en) | 1988-09-06 | 2000-07-04 | 株式会社東芝 | Semiconductor device |
US5258635A (en) | 1988-09-06 | 1993-11-02 | Kabushiki Kaisha Toshiba | MOS-type semiconductor integrated circuit device |
JPH0289368A (en) | 1988-09-27 | 1990-03-29 | Sony Corp | Solid-state image sensing device |
JP2804539B2 (en) | 1989-09-28 | 1998-09-30 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
JP2950558B2 (en) | 1989-11-01 | 1999-09-20 | 株式会社東芝 | Semiconductor device |
JPH03187272A (en) | 1989-12-15 | 1991-08-15 | Mitsubishi Electric Corp | Mos type field effect transistor and manufacture thereof |
JPH03225873A (en) | 1990-01-30 | 1991-10-04 | Mitsubishi Electric Corp | Semiconductor device |
JPH04234166A (en) | 1990-12-28 | 1992-08-21 | Texas Instr Japan Ltd | Semiconductor integrated circuit device |
US5466961A (en) | 1991-04-23 | 1995-11-14 | Canon Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
JP3325072B2 (en) | 1992-03-02 | 2002-09-17 | モトローラ・インコーポレイテッド | Semiconductor memory device |
US5308782A (en) | 1992-03-02 | 1994-05-03 | Motorola | Semiconductor memory device and method of formation |
JPH05276442A (en) | 1992-03-30 | 1993-10-22 | Hamamatsu Photonics Kk | Afterimage integration solid-state image pickup device |
JP2748072B2 (en) | 1992-07-03 | 1998-05-06 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
GB2286723B (en) | 1992-12-11 | 1997-01-08 | Intel Corp | A mos transistor having a composite gate electrode and method of fabrication |
JPH06237003A (en) | 1993-02-10 | 1994-08-23 | Hitachi Ltd | Semiconductor memory device and manufacture thereof |
JPH06268173A (en) | 1993-03-15 | 1994-09-22 | Toshiba Corp | Semiconductor memory device |
JP3403231B2 (en) | 1993-05-12 | 2003-05-06 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
JP3745392B2 (en) | 1994-05-26 | 2006-02-15 | 株式会社ルネサステクノロジ | Semiconductor device |
JPH0878533A (en) | 1994-08-31 | 1996-03-22 | Nec Corp | Semiconductor device and fabrication thereof |
JP2797984B2 (en) | 1994-10-27 | 1998-09-17 | 日本電気株式会社 | Solid-state imaging device and method of manufacturing the same |
JP3318814B2 (en) | 1995-03-15 | 2002-08-26 | ソニー株式会社 | Solid-state imaging device and driving method thereof |
KR0165398B1 (en) | 1995-05-26 | 1998-12-15 | 윤종용 | Vertical transistor manufacturing method |
JPH098290A (en) | 1995-06-20 | 1997-01-10 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
JP3957774B2 (en) | 1995-06-23 | 2007-08-15 | 株式会社東芝 | Semiconductor device |
US5767549A (en) | 1996-07-03 | 1998-06-16 | International Business Machines Corporation | SOI CMOS structure |
JPH1079482A (en) | 1996-08-09 | 1998-03-24 | Rai Hai | Ultrahigh-density integrated circuit |
US7052941B2 (en) | 2003-06-24 | 2006-05-30 | Sang-Yun Lee | Method for making a three-dimensional integrated circuit structure |
JP3036588B2 (en) | 1997-02-03 | 2000-04-24 | 日本電気株式会社 | Semiconductor storage device |
JP4014708B2 (en) | 1997-08-21 | 2007-11-28 | 株式会社ルネサステクノロジ | Method for designing semiconductor integrated circuit device |
JPH1187649A (en) | 1997-09-04 | 1999-03-30 | Hitachi Ltd | Semiconductor storage device |
US6242775B1 (en) | 1998-02-24 | 2001-06-05 | Micron Technology, Inc. | Circuits and methods using vertical complementary transistors |
JP3467416B2 (en) | 1998-04-20 | 2003-11-17 | Necエレクトロニクス株式会社 | Semiconductor memory device and method of manufacturing the same |
JP2000039628A (en) | 1998-05-16 | 2000-02-08 | Semiconductor Energy Lab Co Ltd | Semiconductor display device |
JP3718058B2 (en) | 1998-06-17 | 2005-11-16 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor integrated circuit device |
JP4078721B2 (en) | 1998-08-24 | 2008-04-23 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
US6204187B1 (en) | 1999-01-06 | 2001-03-20 | Infineon Technologies North America, Corp. | Contact and deep trench patterning |
JP2000243085A (en) | 1999-02-22 | 2000-09-08 | Hitachi Ltd | Semiconductor device |
JP3621844B2 (en) | 1999-02-24 | 2005-02-16 | シャープ株式会社 | Amplification type solid-state imaging device |
JP2000357736A (en) | 1999-06-15 | 2000-12-26 | Toshiba Corp | Semiconductor device and manufacture thereof |
EP1063697B1 (en) | 1999-06-18 | 2003-03-12 | Lucent Technologies Inc. | A process for fabricating a CMOS integrated circuit having vertical transistors |
US6392271B1 (en) | 1999-06-28 | 2002-05-21 | Intel Corporation | Structure and process flow for fabrication of dual gate floating body integrated MOS transistors |
JP4666723B2 (en) | 1999-07-06 | 2011-04-06 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
US6483171B1 (en) | 1999-08-13 | 2002-11-19 | Micron Technology, Inc. | Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same |
DE19945136A1 (en) | 1999-09-21 | 2001-04-12 | Infineon Technologies Ag | Vertical pixel cells |
JP2001237421A (en) | 2000-02-24 | 2001-08-31 | Toshiba Corp | Semiconductor device, sram and method of manufacturing the same |
US6882012B2 (en) | 2000-02-28 | 2005-04-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and a method of manufacturing the same |
JP2002231951A (en) | 2001-01-29 | 2002-08-16 | Sony Corp | Semiconductor device and its manufacturing method |
US6624459B1 (en) | 2000-04-12 | 2003-09-23 | International Business Machines Corp. | Silicon on insulator field effect transistors having shared body contact |
JP3713418B2 (en) | 2000-05-30 | 2005-11-09 | 光正 小柳 | Manufacturing method of three-dimensional image processing apparatus |
JP2001352047A (en) | 2000-06-05 | 2001-12-21 | Oki Micro Design Co Ltd | Semiconductor integrated circuit |
JP4021602B2 (en) | 2000-06-16 | 2007-12-12 | 株式会社東芝 | Semiconductor memory device |
JP2002033399A (en) | 2000-07-13 | 2002-01-31 | Toshiba Corp | Semiconductor integrated circuit and its manufacturing method |
JP4064607B2 (en) | 2000-09-08 | 2008-03-19 | 株式会社東芝 | Semiconductor memory device |
US6406962B1 (en) | 2001-01-17 | 2002-06-18 | International Business Machines Corporation | Vertical trench-formed dual-gate FET device structure and method for creation |
US6448601B1 (en) | 2001-02-09 | 2002-09-10 | Micron Technology, Inc. | Memory address and decode circuits with ultra thin body transistors |
US6531727B2 (en) | 2001-02-09 | 2003-03-11 | Micron Technology, Inc. | Open bit line DRAM with ultra thin body transistors |
JP3899236B2 (en) | 2001-02-16 | 2007-03-28 | シャープ株式会社 | Manufacturing method of image sensor |
JP3908911B2 (en) | 2001-02-16 | 2007-04-25 | シャープ株式会社 | Manufacturing method of image sensor |
FR2823009B1 (en) | 2001-04-02 | 2004-07-09 | St Microelectronics Sa | METHOD FOR MANUFACTURING A VERTICAL TRANSISTOR WITH INSULATED GRID WITH LOW COVERAGE OF THE GRID ON THE SOURCE AND ON THE DRAIN, AND INTEGRATED CIRCUIT COMPRISING SUCH A TRANSISTOR |
US6927433B2 (en) | 2001-06-28 | 2005-08-09 | Isetec, Inc | Active pixel image sensor with two transistor pixel, in-pixel non-uniformity correction, and bootstrapped reset lines |
JP2003068883A (en) | 2001-08-24 | 2003-03-07 | Hitachi Ltd | Semiconductor storage device |
US6461900B1 (en) | 2001-10-18 | 2002-10-08 | Chartered Semiconductor Manufacturing Ltd. | Method to form a self-aligned CMOS inverter using vertical device integration |
JP2003142684A (en) | 2001-11-02 | 2003-05-16 | Toshiba Corp | Semiconductor element and semiconductor device |
US6657259B2 (en) | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
US6670642B2 (en) | 2002-01-22 | 2003-12-30 | Renesas Technology Corporation. | Semiconductor memory device using vertical-channel transistors |
US6658259B2 (en) | 2002-03-07 | 2003-12-02 | Interwave Communications International, Ltd. | Wireless network having a virtual HLR and method of operating the same |
JP2004096065A (en) | 2002-07-08 | 2004-03-25 | Renesas Technology Corp | Semiconductor memory device and method of manufacturing the same |
JP2004079694A (en) | 2002-08-14 | 2004-03-11 | Fujitsu Ltd | Standard cell |
JP4639040B2 (en) | 2002-10-10 | 2011-02-23 | パナソニック株式会社 | Manufacturing method of semiconductor device |
JP2004165462A (en) | 2002-11-14 | 2004-06-10 | Sony Corp | Solid-state imaging device and its manufacturing method |
US7138685B2 (en) | 2002-12-11 | 2006-11-21 | International Business Machines Corporation | Vertical MOSFET SRAM cell |
KR100467027B1 (en) | 2003-01-07 | 2005-01-24 | 삼성전자주식회사 | Static random access memory having vertical transistors and method for fabricating the same |
JP2004259733A (en) | 2003-02-24 | 2004-09-16 | Seiko Epson Corp | Solid-state image pickup device |
CN1764982B (en) | 2003-03-18 | 2011-03-23 | 株式会社东芝 | Phase-change memory device and its manufacture method |
US6902962B2 (en) | 2003-04-04 | 2005-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon-on-insulator chip with multiple crystal orientations |
JP2004319808A (en) | 2003-04-17 | 2004-11-11 | Takehide Shirato | Mis field effect transistor and its manufacturing method |
JP4108537B2 (en) | 2003-05-28 | 2008-06-25 | 富士雄 舛岡 | Semiconductor device |
US6943407B2 (en) | 2003-06-17 | 2005-09-13 | International Business Machines Corporation | Low leakage heterojunction vertical transistors and high performance devices thereof |
JP4651920B2 (en) | 2003-07-15 | 2011-03-16 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US7612416B2 (en) | 2003-10-09 | 2009-11-03 | Nec Corporation | Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same |
JP4758061B2 (en) | 2003-10-16 | 2011-08-24 | パナソニック株式会社 | Solid-state imaging device and manufacturing method thereof |
JP4416474B2 (en) | 2003-10-28 | 2010-02-17 | 株式会社ルネサステクノロジ | Semiconductor memory device |
US7372091B2 (en) | 2004-01-27 | 2008-05-13 | Micron Technology, Inc. | Selective epitaxy vertical integrated circuit components |
US6878991B1 (en) | 2004-01-30 | 2005-04-12 | Micron Technology, Inc. | Vertical device 4F2 EEPROM memory |
KR100532564B1 (en) | 2004-05-25 | 2005-12-01 | 한국전자통신연구원 | Multiple-gate MOS transistor and a method for manufacturing the same |
JP4218894B2 (en) | 2004-07-08 | 2009-02-04 | シャープ株式会社 | Solid-state imaging device and manufacturing method thereof |
US7518182B2 (en) | 2004-07-20 | 2009-04-14 | Micron Technology, Inc. | DRAM layout with vertical FETs and method of formation |
US7247570B2 (en) | 2004-08-19 | 2007-07-24 | Micron Technology, Inc. | Silicon pillars for vertical transistors |
US7241655B2 (en) | 2004-08-30 | 2007-07-10 | Micron Technology, Inc. | Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array |
US7442970B2 (en) | 2004-08-30 | 2008-10-28 | Micron Technology, Inc. | Active photosensitive structure with buried depletion layer |
US7271052B1 (en) | 2004-09-02 | 2007-09-18 | Micron Technology, Inc. | Long retention time single transistor vertical memory gain cell |
US8110869B2 (en) | 2005-02-11 | 2012-02-07 | Alpha & Omega Semiconductor, Ltd | Planar SRFET using no additional masks and layout method |
JP5017795B2 (en) | 2005-04-13 | 2012-09-05 | 日本電気株式会社 | Method for manufacturing field effect transistor |
US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
US20060261406A1 (en) | 2005-05-18 | 2006-11-23 | Yijian Chen | Vertical integrated-gate CMOS device and its fabrication process |
US7429536B2 (en) | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
KR100673012B1 (en) | 2005-09-02 | 2007-01-24 | 삼성전자주식회사 | Double-gate type dynamic random access memory device having vertical channel transistors and method of fabricating the same |
FR2891664B1 (en) | 2005-09-30 | 2007-12-21 | Commissariat Energie Atomique | VERTICAL MOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME |
KR100800469B1 (en) | 2005-10-05 | 2008-02-01 | 삼성전자주식회사 | Circuitry device comprising vertical transistors with buried bit lines and manufacturing method for the same |
US7977736B2 (en) | 2006-02-23 | 2011-07-12 | Samsung Electronics Co., Ltd. | Vertical channel transistors and memory devices including vertical channel transistors |
JP2008028240A (en) | 2006-07-24 | 2008-02-07 | Toshiba Corp | Solid-state imaging apparatus |
JP2008053388A (en) | 2006-08-23 | 2008-03-06 | Toshiba Corp | Semiconductor device, and its manufacturing method |
US8685909B2 (en) * | 2006-09-21 | 2014-04-01 | Advanced Technology Materials, Inc. | Antioxidants for post-CMP cleaning formulations |
US8058683B2 (en) | 2007-01-18 | 2011-11-15 | Samsung Electronics Co., Ltd. | Access device having vertical channel and related semiconductor device and a method of fabricating the access device |
JP5114968B2 (en) | 2007-02-20 | 2013-01-09 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
JP2008227026A (en) | 2007-03-12 | 2008-09-25 | Toshiba Corp | Manufacturing method of semiconductor device |
JP5130596B2 (en) | 2007-05-30 | 2013-01-30 | 国立大学法人東北大学 | Semiconductor device |
JP2009037115A (en) | 2007-08-03 | 2009-02-19 | Sony Corp | Semiconductor device, its manufacturing method, and display device |
US8330089B2 (en) | 2007-09-12 | 2012-12-11 | Unisantis Electronics Singapore Pte Ltd. | Solid-state imaging device |
EP2197032B1 (en) | 2007-09-12 | 2014-11-05 | Unisantis Electronics Singapore Pte. Ltd. | Solid-state imaging device |
US8101500B2 (en) | 2007-09-27 | 2012-01-24 | Fairchild Semiconductor Corporation | Semiconductor device with (110)-oriented silicon |
JP2009088134A (en) | 2007-09-28 | 2009-04-23 | Elpida Memory Inc | Semiconductor device, method of manufacturing the same, and data processing system |
JP4900195B2 (en) | 2007-10-26 | 2012-03-21 | 大日本印刷株式会社 | Authoring apparatus, method and computer program |
US8183628B2 (en) | 2007-10-29 | 2012-05-22 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor structure and method of fabricating the semiconductor structure |
WO2009057194A1 (en) | 2007-10-29 | 2009-05-07 | Unisantis Electronics (Japan) Ltd. | Semiconductor structure, and manufacturing method for that semiconductor structure |
JP2009117518A (en) | 2007-11-05 | 2009-05-28 | Toshiba Corp | Semiconductor memory device and method of manufacturing the same |
US7935598B2 (en) | 2007-12-24 | 2011-05-03 | Hynix Semiconductor Inc. | Vertical channel transistor and method of fabricating the same |
US7956434B2 (en) | 2007-12-27 | 2011-06-07 | Dongbu Hitek Co., Ltd. | Image sensor and method for manufacturing the same |
JP5317343B2 (en) | 2009-04-28 | 2013-10-16 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and manufacturing method thereof |
WO2009095999A1 (en) | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | Semiconductor storage device |
US8154086B2 (en) | 2008-01-29 | 2012-04-10 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor surround gate SRAM storage device |
US8212298B2 (en) | 2008-01-29 | 2012-07-03 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor storage device and methods of producing it |
WO2009096001A1 (en) | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | Semiconductor storage device and memory embedded semiconductor device, and manufacturing method thereof |
JP4316658B2 (en) | 2008-01-29 | 2009-08-19 | 日本ユニサンティスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
WO2009095998A1 (en) | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | Semiconductor storage device |
US8188537B2 (en) | 2008-01-29 | 2012-05-29 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor device and production method therefor |
JP4316657B2 (en) * | 2008-01-29 | 2009-08-19 | 日本ユニサンティスエレクトロニクス株式会社 | Semiconductor device |
WO2009096002A1 (en) | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | Manufacturing method of semiconductor storage device |
US8378425B2 (en) | 2008-01-29 | 2013-02-19 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor storage device |
WO2009095997A1 (en) * | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | Semiconductor device and its manufacturing method |
WO2009101704A1 (en) * | 2008-02-15 | 2009-08-20 | Unisantis Electronics (Japan) Ltd. | Method for manufacturing semiconductor device |
US8097907B2 (en) | 2008-05-02 | 2012-01-17 | Unisantis Electronics Singapore Pte Ltd. | Solid-state imaging device |
WO2009133623A1 (en) | 2008-05-02 | 2009-11-05 | 日本ユニサンティスエレクトロニクス株式会社 | Solid-state imaging element |
KR100971412B1 (en) | 2008-05-21 | 2010-07-21 | 주식회사 하이닉스반도체 | Method for forming vertical channel transistor of semiconductor device |
JP2010034191A (en) | 2008-07-28 | 2010-02-12 | Toshiba Corp | Semiconductor memory device and manufacturing method thereof |
TWI368315B (en) | 2008-08-27 | 2012-07-11 | Nanya Technology Corp | Transistor structure, dynamic random access memory containing the transistor structure, and method of making the same |
JP2010171055A (en) | 2009-01-20 | 2010-08-05 | Elpida Memory Inc | Semiconductor device and method of manufacturing the same |
US8338292B2 (en) | 2009-02-18 | 2012-12-25 | International Business Machines Corporation | Body contacts for FET in SOI SRAM array |
TWI388059B (en) | 2009-05-01 | 2013-03-01 | Niko Semiconductor Co Ltd | The structure of gold-oxygen semiconductor and its manufacturing method |
US7968876B2 (en) | 2009-05-22 | 2011-06-28 | Macronix International Co., Ltd. | Phase change memory cell having vertical channel access transistor |
JP4987926B2 (en) | 2009-09-16 | 2012-08-01 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device |
JP2011071235A (en) | 2009-09-24 | 2011-04-07 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
KR101116354B1 (en) | 2009-09-30 | 2012-03-09 | 주식회사 하이닉스반도체 | Semiconductor device with buried bitline interconnected one side contact and method for manufacturing the same |
JP5356970B2 (en) | 2009-10-01 | 2013-12-04 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device |
JP5031809B2 (en) * | 2009-11-13 | 2012-09-26 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device |
US8067800B2 (en) | 2009-12-28 | 2011-11-29 | Force Mos Technology Co., Ltd. | Super-junction trench MOSFET with resurf step oxide and the method to make the same |
JP4912513B2 (en) | 2010-03-08 | 2012-04-11 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Solid-state imaging device |
JP5054182B2 (en) | 2010-03-12 | 2012-10-24 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Solid-state imaging device |
JP2011216657A (en) * | 2010-03-31 | 2011-10-27 | Unisantis Electronics Japan Ltd | Semiconductor device |
JP5066590B2 (en) | 2010-06-09 | 2012-11-07 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and manufacturing method thereof |
JP5087655B2 (en) | 2010-06-15 | 2012-12-05 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and manufacturing method thereof |
US8378400B2 (en) | 2010-10-29 | 2013-02-19 | Unisantis Electronics Singapore Pte Ltd. | Solid state imaging device |
-
2010
- 2010-06-15 JP JP2010136470A patent/JP5087655B2/en active Active
-
2011
- 2011-05-23 KR KR1020110048345A patent/KR101253419B1/en active IP Right Grant
- 2011-05-25 SG SG2011037819A patent/SG177062A1/en unknown
- 2011-05-26 US US13/116,506 patent/US9153697B2/en active Active
- 2011-05-26 TW TW100118445A patent/TW201145516A/en unknown
- 2011-06-01 CN CN201110151947.9A patent/CN102290441B/en active Active
-
2015
- 2015-08-20 US US14/831,303 patent/US20150357428A1/en not_active Abandoned
-
2016
- 2016-06-24 US US15/191,853 patent/US20160308013A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100207201A1 (en) * | 2008-01-29 | 2010-08-19 | Fujio Masuoka | Semiconductor device and production method therefor |
US20100219464A1 (en) * | 2008-02-15 | 2010-09-02 | Fujio Masuoka | Production method for semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11742400B2 (en) * | 2018-08-14 | 2023-08-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field effect transistor (FinFET) device structure with deep contact structure |
Also Published As
Publication number | Publication date |
---|---|
KR20110136696A (en) | 2011-12-21 |
KR101253419B1 (en) | 2013-04-11 |
CN102290441A (en) | 2011-12-21 |
SG177062A1 (en) | 2012-01-30 |
TW201145516A (en) | 2011-12-16 |
JP5087655B2 (en) | 2012-12-05 |
JP2012004244A (en) | 2012-01-05 |
US20150357428A1 (en) | 2015-12-10 |
US9153697B2 (en) | 2015-10-06 |
US20110303973A1 (en) | 2011-12-15 |
CN102290441B (en) | 2014-01-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9153697B2 (en) | Surrounding gate transistor (SGT) structure | |
TWI409952B (en) | Semiconductor device and method for production | |
US6815285B2 (en) | Methods of forming dual gate semiconductor devices having a metal nitride layer | |
US6908801B2 (en) | Method of manufacturing semiconductor device | |
US10483366B2 (en) | Semiconductor device | |
US6780717B2 (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
JP2010538460A (en) | CMOS device having gate insulating layers of different types and thicknesses, and method for forming the same | |
EP1227521A2 (en) | A method to form a transistor with multiple threshold voltages using a combination of different work function gate materials | |
US9059309B2 (en) | Semiconductor device and production method | |
US10340184B2 (en) | Method for producing a semiconductor device | |
JP2009176997A (en) | Semiconductor device and its production process | |
US7445981B1 (en) | Method for forming a dual metal gate structure | |
US10026842B2 (en) | Method for producing semiconductor device | |
US9741801B2 (en) | Method for producing a semiconductor device | |
US20050205940A1 (en) | Semiconductor device and method for manufacturing the same | |
JP4842592B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2002057331A (en) | Semiconductor device and its manufacturing method | |
JP4011014B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2005347631A (en) | Semiconductor device and method for manufacturing the same | |
JPH09246541A (en) | Manufacture of semiconductor device | |
JP2005340280A (en) | Semiconductor device and its manufacturing method | |
KR20080011215A (en) | A semiconductor device having a gate dielectric of different blocking characteristics |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: ADVISORY ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: ADVISORY ACTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |