JP2005347631A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable selective formation of a metal film or a metal compound film only on an insulating substance of a sample substrate having the insulating substance and a conductive substance mixedly present therein. <P>SOLUTION: In a method for forming a film containing a metal on a sample substrate having a conductive substance and an insulating substance mixedly present therein, an organic compound is first adsorbed on the conductive substance. An organic metal compound is then adsorbed on the insulating substrate. And a reducing agent is supplied which causes the organic compound adsorbed on the conductive substance to desorb and reduces the organic metal compound, thus depositing a film containing a metal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device. More specifically, the present invention relates to a semiconductor device having two types of metal gates containing different metals and a method for manufacturing the same.

  In recent years, with the high integration and miniaturization of semiconductor devices, the gate insulating film of transistors is also being thinned. Specifically, the gate insulating film of the transistor has an EOT (equivalent oxide film thickness) of about 2.0 nm or less.

  On the other hand, with the miniaturization of a semiconductor device and the thinning of a gate insulating film, a reduction in capacity due to depletion of the electrode becomes a problem in the gate electrode. When conventional polysilicon is used as the gate electrode material, this decrease in capacitance corresponds to an increase in film thickness of about 0.5 nm in terms of the thickness of the silicon oxide film. This value is not negligible compared with the thickness of the gate insulating film to be thinned. Therefore, in order to suppress depletion of the gate electrode, it is considered to use a metal instead of polysilicon as the material of the gate electrode.

  On the other hand, with the increase in functionality and integration of semiconductor devices, one semiconductor includes an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor: hereinafter referred to as nMIS) and a p-type MISFET (hereinafter referred to as pMIS). CMIS (complementary MIS) in which both of the above are installed is used. In this cMIS, the threshold voltage is significantly lowered (rolled off) with the miniaturization. Therefore, a dual gate structure is used in which the nMIS gate electrode is n-type and the pMIS gate electrode is p-type.

  For example, in the case of a conventional polysilicon gate electrode using polysilicon as the gate electrode material, an n-type impurity is applied to the nMIS gate electrode, and a p-type impurity is applied to the pMIS gate electrode. Each can be ion-implanted to easily form a dual gate structure (Dual Work Function).

  However, in the case of a metal gate electrode using a metal as a gate electrode material, a work function can be easily obtained by a method such as a polysilicon gate electrode, that is, by depositing one kind of film (polysilicon film) and then ion implantation. No method has been established to control the above. Therefore, when forming a metal gate electrode, it is common to deposit two types of metal films separately.

18 to 21 are schematic cross-sectional views for explaining a conventional method of forming cMIS having a metal gate electrode.
Hereinafter, a conventional method for forming a metal gate in which two types of metal gates made of different metals are separately formed will be described with reference to the drawings.

First, as shown in FIG. 18, a p well 104 and an n well 106 are respectively formed in a region for forming an nMIS and a region for forming a pMIS of the Si substrate 102, and further, HfO is formed on the Si substrate 102. _{The two} films 108 and the like are formed as a gate insulating film material, and the TiN film 110 is formed as a gate electrode material of pMIS.

  Next, as shown in FIG. 19, the TiN film 110 on the pMIS region side is left, and the TiN film on the nMIS region side is removed by a lithography process, an etching process, or the like. Next, as shown in FIG. 20, a TaSiN film 112 which is an nMIS gate electrode material is formed on the entire surface.

Next, as shown in FIG. 21, a polysilicon film 114 is formed on the TaSiN film 112, and the gate electrode is processed by a normal process.
As a result, a gate electrode composed of a laminated film of the TiN film 110 and the polysilicon film 114 is formed in the pMIS region, and a gate electrode composed of a laminated film of the TaSiN film 112 and the polysilicon film 114 is formed in the nMIS region. (See Non-Patent Document 1, for example).

As another method for forming a metal gate electrode, there has been proposed a method in which the entire polysilicon is thermally reacted with a metal and replaced with a metal silicide.
22 to 24 are schematic cross-sectional views for explaining a method of forming a metal gate electrode using metal silicide.
Hereinafter, this method will be briefly described with reference to FIGS.

  First, as shown in FIG. 22, a well 124, an impurity diffusion layer 126, a gate insulating film 128, a polysilicon gate electrode 130, a sidewall 132, and the like are formed on a Si substrate 122 by a conventional method to form a polysilicon gate. An insulating film 134 is deposited so as to embed the electrode 130, the sidewall 132, and the like. Thereafter, polishing by CMP is performed until the surface of the polysilicon gate electrode 130 is exposed by CMP.

  Next, as shown in FIG. 23, a metal film 136 is formed on the insulating film 134 and the polysilicon gate electrode 130. Then, by annealing in a non-oxidizing atmosphere, the silicon of the polysilicon gate electrode 130 reacts with the metal of the metal film 136, and the polysilicon gate electrode 130 is converted into a metal silicide gate electrode 138 made of metal silicide. . Thereafter, as shown in FIG. 24, the metal film 136 remaining without being silicided is removed. Thereby, a transistor having a metal silicide as a gate electrode is formed (see, for example, Non-Patent Document 2).

Samavedam et al., IEDM Tech. Digest, 2002, p. 443 Z. Krivokapic et al., IEDM Tech. Digest, 2002, P. 271

  By the way, when using the method of forming separately the metal gate electrode which consists of a different metal, as a deposition method of the metal for gate electrodes, PVD (Physical Vapor Deposition) method or CVD (Chemical Vapor Deposition; Chemical vapor deposition method is used. However, for example, when film formation is performed by the PVD method, metal particles with large kinetic energy or charged metal particles directly collide with the surface of the thin gate insulating film. Therefore, defects may occur in the interface between the metal and the gate insulating film or in the gate insulating film.

On the other hand, in the case of the CVD method, the source gas generally contains halogens such as F and Cl, and organic substances. The material film of the gate insulating film, for example, SiO ₂ or SiON, or an oxide of Hf or Zr and a film to which Si, N, or Al is added may be etched in an atmosphere containing halogen. The deposited metal film contains halogen and C. If halogen or C is taken into the metal film, it may diffuse into the insulating film and cause defects in the subsequent thermal process. In addition, from the viewpoint of work function, thermal and chemical stability, a raw material compound having a sufficiently high vapor pressure is not always obtained for a suitable metal.

  Further, in this method, it is necessary to remove a part of the metal deposited on the gate insulating film (that is, the TiN film 110 on the pMIS region side in the above case) by etching. Therefore, the gate insulating film once deposited is exposed to an etching solution or an etching gas. As a result, there is a possibility that the film characteristics of the gate insulating film are deteriorated, for example, the gate breakdown voltage of the gate insulating film is lowered.

On the other hand, in the method of forming a metal film on a polysilicon film and forming a metal silicide, it is not necessary to form a metal film directly on the gate insulating film. Therefore, PVD is not directly performed on the gate insulating film, and damage to the gate insulating film can be avoided. A polysilicon film is formed immediately above the gate insulating film. Even if a polysilicon film is formed directly on the gate insulating film by the CVD method, the source gas used is SiH ₄ , Si ₂ H _6, etc., and avoids the use of gases containing halogen such as F and Cl be able to. For this reason, film quality deterioration of the gate insulating film and the like due to the halogen gas can be avoided.

  However, in this method, a method for forming a dual gate structure composed of two types of metal gates has not been established. For example, it is conceivable that an nMIS metal film and a pMIS metal film are separately formed in each region on a polysilicon film and then silicided. However, when the same polysilicon film is silicided with different metals, different types of metals may be mixed, making it difficult to control the work function of each gate electrode.

  Therefore, the present invention provides a semiconductor device having two types of gate electrodes made of different metals and a method for manufacturing the same while solving the above-described problems and suppressing damage to the gate insulating film.

  According to the method for manufacturing a semiconductor device of the present invention, a gate insulating film forming step for forming a gate insulating film on a substrate having a first region and a second region, and a silicon film is formed on the gate insulating film. A silicon film forming step, a first metal film forming step of forming a first metal film made of a first metal on the silicon film in the first region, the first metal film, and the A second metal film forming step of forming a second metal film made of a second metal on the silicon film in a second region; the silicon film in the first region; A first silicidation step of forming a silicide of the first metal by reacting with a metal film; reacting the silicon film in the second region with the second metal film; Second silicidation to form second metal silicide And a degree. Here, the second metal has an absolute value of the heat generated per 1 mol of silicon in the reaction between the first metal and silicon when the second metal reacts with silicon to form a compound. It is a smaller metal.

  Alternatively, in the method of manufacturing a semiconductor device according to the present invention, the first reaction step and the second reaction step may be performed simultaneously by heat treatment.

The semiconductor device of the present invention includes a substrate including a first region and a second region, a first transistor, and a second transistor. The first transistor is formed in the first region and includes a first gate insulating film, a first gate electrode, and a first impurity diffusion layer, and the second transistor includes: The second region is formed in the second region and includes a second gate insulating film, a second gate electrode, and a second impurity diffusion layer. The first gate electrode includes a first metal silicide film including a first metal, and the second gate electrode includes a second metal silicide film including a second metal.
Furthermore, when the second metal reacts with silicon to form a compound, the absolute value of the heat generated per mol of silicon is equal to that per mol of silicon when the first metal reacts with silicon. It is a metal that is smaller than the absolute value of the heat of formation.

  In the present invention, after a silicon film is formed on the gate insulating film, a first metal film and a second metal film are formed in appropriate regions, and silicon and these metals are reacted to form a metal. A gate electrode of silicide is formed. Here, a second metal film is also formed on the first metal film. In addition, as the first metal, a metal whose absolute value of heat generated in silicidation is larger than the absolute value of heat generated in the reaction between the second metal and silicon is selected and used. Accordingly, a gate electrode made of the first metal silicide can be formed in the region where the first metal is formed, and a gate electrode made of the second metal silicide can be formed in the region where the second metal is formed. . Thereby, a semiconductor device having two kinds of gate electrodes made of different metals can be easily obtained.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is simplified or omitted.

Embodiment.
FIG. 1 is a schematic cross-sectional view for explaining a semiconductor device according to an embodiment of the present invention.
First, the semiconductor device in the embodiment will be described with reference to FIG.

  The semiconductor device in this embodiment includes an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor: hereinafter referred to as nMIS) and a p-type MISFET (hereinafter referred to as pMIS) which are mixed. Hereinafter, it is referred to as cMIS). In this specification, for simplification, a region where nMIS is formed is referred to as an nMIS region, and a region where pMIS is formed is referred to as a pMIS region. In each figure, the left side is an nMIS and the right side is a pMIS region, and one nMIS and one pMIS are shown in each region. However, in an actual semiconductor device, it is needless to say that the substrate is complicatedly divided into pMIS and nMIS regions, and a large number of transistors are formed in each region.

  In the cross-sectional shape shown in FIG. 1, an STI (Shallow Trench Isolation) 4 is formed on the Si substrate 2, and the Si substrate 2 is separated into an nMIS region and a pMIS region. Further, a p-well 6 into which p-type impurities are implanted is formed in the nMIS region, and an n-well 8 into which n-type impurities are implanted is formed in the pMIS region. An extension 10 is formed in the vicinity of the surface of the Si substrate 2 in each region. The extension 10 is a low-concentration impurity diffusion layer having a relatively shallow junction depth. A source / drain 12 is formed outside the extension 10. The source / drain 12 is a high-concentration impurity diffusion layer having a junction depth deeper than that of the extension 10. A halo 14 is formed so as to surround the lower portion of the extension 10.

A first interlayer insulating film 18 is formed on the Si substrate 2 via an etching stopper film 16. The film thickness of the first interlayer insulating film 18 is about 100 nm. A gate is embedded in the first interlayer insulating film 18. Specifically, in the nMIS region, a gate groove 20 is formed in the first interlayer insulating film 18 on the channel portion sandwiched between the extensions 10 of the Si substrate 2, and along the inner wall surface of the gate groove 20. Thus, a gate insulating film 22 is formed. The physical film thickness of the gate insulating film 22 on the Si substrate 2, that is, at the bottom of the gate groove 20, is about 2 nm. A gate electrode 24 is formed on the gate insulating film 22 inside the gate trench 20. The gate length of the gate electrode 24 is about 30 nm, and the total film thickness is about 100 nm. The gate electrode 24 includes a TiSi ₂ film 26 formed along the gate insulating film 22 inside the gate groove 20, a Ti film 28, and a Ni film 30 formed by filling the gate groove 20 on the Ti film 28. Consists of.

Similarly, in the pMIS region, a gate groove 20 is formed in the first interlayer insulating film 18 on the channel region of the Si substrate 2, and a gate insulating film 22 is formed along the inner wall surface of the gate groove 20. Has been. The thickness of the gate insulating film 22 is the same as that of the nMIS region, and is about 2 nm at the bottom of the gate groove 20. A gate electrode 32 is formed on the gate insulating film 22 inside the gate trench 20. The gate length of the gate electrode 32 is about 30 nm, and the film thickness is about 100 nm. The gate electrode 32 includes a NiSi ₂ film 34 formed along the gate insulating film 22 in the gate groove 20 and a Ni film 36 formed by filling the gate groove 20.

  In each region, side walls 38 are formed on the side surfaces of the gate electrodes 24 and 32 with the gate insulating film 22 interposed therebetween. An etching stopper film 16 is disposed on the side surface of the side wall 38 and the surface of the Si substrate 2, and a first interlayer insulating film 18 is formed thereon.

  A second interlayer insulating film 40 is formed on the first interlayer insulating film 18. Contact plugs that pass through the second interlayer insulating film 40 and / or the first interlayer insulating film 18 and are connected to the source / drain 12, the gate electrode 24, and the like are formed. The contact plug is formed by burying a metal 46 through a barrier metal 44 in a contact hole penetrating a predetermined position in the second interlayer insulating film 40 and / or the first interlayer insulating film 18. .

FIG. 2 is a flowchart for illustrating the method for manufacturing a semiconductor device in the embodiment of the present invention. 3 to 17 are schematic cross-sectional views for explaining states in each manufacturing process of the semiconductor device.
Hereinafter, the manufacturing method of the above-described semiconductor device will be described with reference to FIGS.

  First, as shown in FIG. 3, the STI 4 is formed on the Si substrate 2, and the Si substrate 2 is separated into an nMIS region and a pMIS region, and p-type and n-type impurities are added to each region. Implantation is performed to form a p-well 6 and an n-well 8 (step S2).

  Next, a dummy gate oxide film 50a is formed by thermal oxidation (step S4). Further, a polysilicon film 52a is formed on the dummy gate oxide film 50a by a CVD (Chemical Vapor Deposition) method (step S6).

  As shown in FIG. 4, the polysilicon film 52a is processed to form a dummy gate electrode 52. Specifically, a resist mask 54 is formed by photolithography, and the polysilicon film 52a is anisotropically etched by RIE (Reactive Ion Etching) using the resist mask 54 as a mask. Thereafter, the resist mask 54 is removed. At this time, the gate length of the dummy gate electrode 52 is about 30 nm for both the nMIS region and the pMIS region.

  Next, as shown in FIG. 5, the extension 10 and the Halo 14 are formed in the nMIS region (step S10). Specifically, after forming a resist mask covering the pMIS region by lithography, first, n-type impurities are ion-implanted using the resist mask and the dummy gate electrode 52 as a mask, and further, p-type impurities are formed thereunder. Are ion-implanted to form an n-type extension 10 and a p-type Halo 14 in the nMIS region.

  Next, the extension 10 and Halo 14 are formed in the pMIS region (step S12). Specifically, a resist mask that covers the nMIS region is formed, p-type impurities are ion-implanted using the dummy gate electrode 52 as a mask, and n-type ions are further implanted thereunder. Thereby, the p-type extension 10 and the n-type Halo 14 are formed in the pMIS region.

  Next, as shown in FIG. 6, a sidewall 38 is formed on the side surface of the dummy gate electrode 52 (step S14). Here, first, an insulating film such as SiN is deposited by LPCVD (Low Pressure CVD). Thereafter, a side wall 38 is formed on the insulating film by performing so-called side wall remaining etching by anisotropic etching such as RIE (Reactive Ion Etching). At the same time, the portion of the dummy gate oxide film 50a exposed on the Si substrate 2 is also removed, and the dummy gate oxide film 50 remains only directly under the sidewall 38 and the dummy gate electrode 52.

  Next, the source / drain 12 is formed in the nMIS region (step S16). Here, a resist mask is formed in the pMIS region, and n-type ion implantation is performed using this resist mask, the dummy gate electrode 52 and the sidewall 38 as a mask, so that the source / drain 12 is formed outside the extension 10. Is formed.

Next, the source / drain 12 is formed in the pMIS region (step S18). Here, a resist mask is formed in the nMIS region, and p-type ion implantation is performed using the resist mask, the dummy gate electrode 52 and the sidewall 38 as a mask, so that the source is formed outside the extension 10 of the pMIS region. / Drain 12 is formed.
Thereafter, annealing is performed at about 1000 ° C. for about 1 second in order to activate the impurities in the extension 10 and the source / drain 12 (step S20).

  Next, as shown in FIG. 7, the etching stopper film 16a is formed along the entire surface exposed on the surfaces of the dummy gate electrode 52, the sidewall 38, the Si substrate 2, and the like (step S22). An SiN film or the like is used as the etching stopper film 16a. Further, a first interlayer insulating film 18a is deposited on the etching stopper film 16a by the CVD method so as to fill the dummy gate electrode 52 and the like (step S24).

  Next, as shown in FIG. 8, the surface of the first interlayer insulating film 18a is polished by a CMP (Chemical Mechanical Polishing) method or the like (step S26). Here, first, CMP of the surface of the first interlayer insulating film 18a is performed, and the grinding by the CMP is stopped by the etching stopper film 16a. Further, the surface of the etching stopper film 16a is removed by wet etching or dry etching. As a result, the dummy gate electrode 52 is exposed on the surface of the first interlayer insulating film 18. The final film thickness from the surface of the Si substrate 2 to the surface of the first interlayer insulating film 18 after the CMP is about 100 nm.

  Next, as shown in FIG. 9, the dummy gate electrode 52 and the dummy gate oxide film 50 immediately below the dummy gate electrode 52 are removed (step S28). As a result, a gate groove 20 for forming a gate electrode is formed in the first interlayer insulating film 18.

Next, as shown in FIG. 10, at least the bottom surface of the gate groove 20 is completely covered, and the gate including ZrO ₂ or HfO ₂ or Si, Al, N, or the like is added to the entire surface including the inner wall of the gate groove 20. An insulating film 22 is formed (step S30), and a silicon film (amorphous or polysilicon) 60 is formed thereon (step S32). Here, it deposits to about 5 nm by CVD method.

  Next, as shown in FIG. 11, a Ti film 62 is formed as a first metal film on the entire surface of the silicon film 60 (step S34). The Ti film 62 is formed to a film thickness of about 5 nm using a PVD (Physical Vapor Deposition) method.

  Next, as shown in FIG. 12, the Ti film 62 in the pMIS region is removed (step S36). Here, a resist mask 64 that covers the nMIS region is formed by lithography, and using this as a mask, only the Ti film 62 on the pMIS region side is selectively etched and removed. Thereafter, the resist mask 64 is peeled off.

  Next, as shown in FIG. 13, a Ni film 66 is formed on the entire surface of the substrate (step S38). The Ni film 66 is formed to a film thickness of about 50 nm using the PVD method. As a result, the inside of the gate groove 20 is filled with the Ti film 62, the Ni film 66, and the like.

  Next, annealing is performed in a non-oxidizing atmosphere (step S40). The annealing temperature here is about 800 ° C., and the annealing time is about 10 seconds. This condition is a condition in which the Ti film 62 and the Ni film 66 are silicided for the entire thickness of the silicon 60.

In this annealing, the Ti film 62 and the silicon film 60 react in the nMIS region as shown in the following equation (1).
Ti + 2Si → TiSi ₂ + ΔHf _n (1)
In the formula (1), ΔHf _n represents heat of formation.

Further, in the pMIS region, the Ni film 66 and the silicon film 60 cause a reaction represented by the following equation (2).
_{Ni + 2Si → NiSi 2 + ΔHf} p ···· (2)
Note that in equation (2), .DELTA.Hf _p represents the generated heat.

Here, in the reaction between Ti or Ni and Si as described above, the absolute value of the heat generated per mol of silicon is larger in the case of Ti, that is, in the case of equation (1). That is, the absolute value of the generated heat ΔHf _n is larger than the absolute value of the generated heat ΔHf _p . Specifically, the absolute value of the heat of formation of Ti is 16 (kcal / mol), and the absolute value of the heat of formation of Ni is 10.4 (kcal / mol).

Therefore, as shown in FIG. 14, in the nMIS region, the Ni film 64 is formed on the Ti film 62. However, even if annealing is performed, only the Ti film 62 is silicided, and Ni film 64 is formed. The film 66 is left as it is without being silicided. Accordingly, in the nMIS region, the TiSi ₂ film 26a, the Ti film 28a remaining without reacting, and the Ni film 30a are stacked on the gate insulating film 22, and in the pMIS region, the NiSi ₂ film is stacked. The Ni film 36a remaining without reacting with 34a is laminated.

Next, as shown in FIG. 15, the TiSi ₂ film 26a, the Ti film 28a, the Ni film 20a, the NiSi ₂ film 34a, and the Ni film 66, which are formed in portions other than the inside of the gate groove 20, are removed (step S42). . Here, these films on the first interlayer insulating film 18 can be removed by polishing by CMP.

  Next, as shown in FIG. 16, a second interlayer insulating film 40 is deposited on the first interlayer insulating film (step S44). Here, the second interlayer insulating film 40 is formed using a CVD method or the like. After the formation of the second interlayer insulating film 40, the contact hole 70 that penetrates the second interlayer insulating film 40 and reaches the surface of the gate electrode 24, the first and second interlayer insulating films 40 and 18, and the etching stopper film A contact hole 72 or the like penetrating through 16 and reaching the source / drain 12 is opened (step S46). Here, after a resist mask having a predetermined pattern is formed by photolithography, the first and second interlayer insulating films 18 and 40 and the etching stopper film 16 are etched using the resist mask as a mask.

  Next, as shown in FIG. 17, the barrier metal 44a is formed on the entire surface including the inner walls of the contact holes 70 and 72 (step S48). Here, a barrier metal film is formed by sputtering. Thereafter, a metal is buried in the contact hole at a depth to bury the inner walls of the contact holes 70 and 72 (step S50).

  Next, planarization by CMP is performed so that at least a part of the surface of the interlayer insulating film 42 is exposed (step S52). Thereby, the semiconductor device as shown in FIG. 1 is formed. Thereafter, multilayer wiring or the like may be formed as necessary.

As described above, in this embodiment, the Ti film 62 and the Ni film 66 are stacked in the nMIS region, and the annealing for silicidation is performed with the Ni film 66 formed in the pMIS region. Do. Here, the absolute value of the heat generated per 1 mol of silicon in the reaction between Ti and Si is larger than that of Ni. Therefore, in the nMIS region, annealing is performed while the Ti film 62 and the Ni film 66 are stacked, but the Ni film is not silicided and remains as it is. On the other hand, since only the Ni film 66 is formed in the pMIS region, Ni is silicided.
Therefore, in this embodiment, two kinds of metal gates made of metals having different work functions can be easily formed by one annealing.

In addition, the silicon film 60 is directly formed on the gate insulating film 22 in the metal gate formation process. Accordingly, although the PVD method is sometimes used on the silicon film 60 in the subsequent process of forming the metal film (for example, the Ti film 62 and the Ni film 66), It does not sputter. Therefore, damage to the gate insulating film 22 can be suppressed when the metal film is formed, that is, when the gate electrodes 24 and 32 are formed.
Similarly, in the case where the metal film is formed using the CVD method instead of the PVD method, a gas containing halogen may be used in the CVD film forming process. However, even in this film formation, since the silicon film 60 has already been formed on the gate insulating film 22, mixing of halogen into the gate insulating film 22 can be suppressed.
Accordingly, in any of the PVD method and the CVD method used for forming the metal film, damage to the gate insulating film 22 can be suppressed, and a semiconductor device having a gate insulating film with good film quality is formed. can do.

  In this embodiment, the case where the annealing is performed in the state where the Ti film 62 and the Ni film 66 are stacked on the nMIS region side and only the Ni film 66 is formed on the pMIS region side has been described. However, the present invention is not limited to this. However, the metal film to be formed is preferably a metal having a work function necessary for its gate electrode when silicided.

  Specifically, for example, when two types of gate electrodes are formed by applying the present invention, for example, first, two types of metals having appropriate conditions are selected from the work function and the like. Then, in the silicidation reaction between each metal and silicon, a film made of a metal having a larger absolute value of heat generated per mol of silicon is first formed on the polysilicon film. Thereafter, the metal silicide having the larger absolute value of the generated heat is removed from the region other than the region used as the gate electrode. Then, a film made of a metal having the smaller absolute value of the other heat generated is formed on the entire surface. Thereafter, annealing is performed to form a gate electrode containing a desired metal silicide in each region.

Table 1 shows the work function calculated from the Shotky barrier height. Here, the work function calculated from the Shotky barrier height is slightly different from that in the case where the gate electrode is formed, but the rough tendency coincides. Table 2 shows the heat of formation of each silicide per 1 mol of silicon.
When determining the metal for forming the gate electrode for nMIS and pMIS, for example, first, an appropriate metal is selected from the metals in Table 1, respectively. Then, by comparing the selected metals, the metal having the larger absolute value of the generated heat shown in the right column of each element in Table 2 is formed first, and then the metal is deleted from the unnecessary region. The gate electrode can be formed by forming the surface with the smaller generation heat on the entire surface and then performing annealing.

  Further, in this embodiment, the case where the gate groove 20 is formed and then the gate insulating film 22 and the gate electrodes 24 and 32 are embedded in the gate groove 20 has been described. However, the present invention is not limited to this. For example, a gate insulating film is formed on a Si substrate, and a polysilicon film, a first metal film, and a second metal film are formed on the gate insulating film on appropriate regions. After being deposited, each of the silicides can be processed into a gate, and this can be used as a mask to form a diffusion layer. Further, not only the gate electrode but also other portions where two types of metal silicide films need to be stacked can be formed.

  In this embodiment, the cross section of each transistor in the nMIS region and the pMIS region is illustrated and described. However, in the present invention, the semiconductor device is not limited to such a shape. In the present invention, the film type, film thickness, formation method, and the like of each film are not limited to those described in the embodiment. These can be appropriately selected within the scope of the present invention.

  For example, in this embodiment, the nMIS region and the pMIS region correspond to the “first region” and the “second region” of the present invention, respectively, and the silicon film 60, the Ti 62, and the Ni film 66 are These correspond to the “silicon film”, “first metal film”, and “second metal film” in the present invention, respectively.

Further, for example, in the embodiment, the gate insulating film 22 and the gate electrode 24 formed in the nMIS region correspond to the “first gate insulating film” and the “first gate electrode” of the present invention, and the nMIS region The extension 10 and the source / drain 12 correspond to the “first impurity diffusion layer”. Further, for example, in the embodiment, the gate insulating film 22 and the gate electrode 32 formed in the pMIS region correspond to the “second gate insulating film” and “second gate electrode” of the present invention, and the pMIS region. The extension 10 and the source / drain 12 correspond to the “second impurity diffusion layer”. Further, for example, the TiSi ₂ film 26 and the NiSi ₂ film 34 correspond to “first metal silicide” and “second metal silicide” of the present invention, respectively.

  Further, for example, in the embodiment, by executing steps S30 and S32, the “gate insulating film forming step” and the “silicon film forming step” of the present invention are executed, respectively. Further, for example, by executing steps S34 and S38, the “first metal film forming step” and the “second metal film forming step” of the present invention are executed, respectively. Further, for example, by executing step S40, the “first silicidation process” and the “second silicidation process” of the present invention are performed.

It is a cross-sectional schematic diagram for demonstrating the semiconductor device in embodiment of this invention. It is a flowchart for demonstrating the manufacturing method of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the conventional semiconductor device. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the conventional semiconductor device. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the conventional semiconductor device. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the conventional semiconductor device. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the conventional semiconductor device. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the conventional semiconductor device. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the conventional semiconductor device.

Explanation of symbols

2 Si substrate 4 STI
6 p-well 8 n-well 10 extension 12 source / drain 14 Halo
16 Etching stopper film 18 First interlayer insulating film 20 Gate groove 22 Gate insulating film 24 Gate electrode 26 TiSi ₂ film 28 Ti film 30 Ni film 32 Gate electrode 34 NiSi ₂ film 36 Ni film 38 Side wall 40 Second interlayer insulation Film 44 Barrier metal 46 Metal 50 Dummy gate oxide film 52 Dummy gate electrode 54 Resist mask 60 Silicon film 62 Ti film 64 Resist mask 66 Ni film

Claims (4)

A gate insulating film forming step of forming a gate insulating film on a substrate having a first region and a second region;
A silicon film forming step of forming a silicon film on the gate insulating film;
A first metal film forming step of forming a first metal film made of a first metal on the silicon film in the first region;
When a compound is formed by reacting with silicon, the generated heat per 1 mol of silicon is a second metal composed of a second metal that is smaller than the absolute value of the generated heat per 1 mol of silicon in the reaction between the first metal and silicon. A second metal film forming step of forming a second metal film on the first metal film and on the silicon film in the second region;
A first silicidation step of reacting the silicon film in the first region with the first metal film to form a silicide of the first metal;
A second silicidation step of reacting the silicon film in the second region with the second metal film to form a silicide of the second metal;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first reaction step and the second reaction step are performed simultaneously by heat treatment.   3. The first metal according to claim 1, wherein the first metal is any one of Ti, Mo, and W, and the second metal is any one of Ni and Co. The manufacturing method of the semiconductor device of description. A substrate including a first region and a second region;
A first transistor formed in the first region and including a first gate insulating film, a first gate electrode, and a first impurity diffusion layer;
A second transistor formed in the second region and including a second gate insulating film, a second gate electrode, and a second impurity diffusion layer;
A semiconductor device comprising:
The first gate electrode includes a first metal silicide film including a first metal,
When the second gate electrode reacts with silicon to form a compound, the absolute value of the heat generated per mol of silicon is equal to that per mol of silicon when the first metal reacts with silicon. A semiconductor device comprising: a second metal silicide containing a second metal that is smaller than an absolute value of generated heat.

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