JP2008258354A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate digging of side portion of a gate electrode of a semiconductor substrate, and to reduce variations of an overlap region between the gate electrode and an extension diffusion layer. <P>SOLUTION: The semiconductor device comprises a gate insulating film 160 which is formed on a semiconductor substrate 100 and is higher in dielectricity than silicon oxide, a gate electrode 220 of polysilicon which is formed on the gate insulating film, an offset side wall oxide film 320 which is formed on the side surface of the gate electrode and is thinner in film thickness than the gate insulating film, a side wall 340 which is formed on the side surface of the gate electrode with the offset side wall oxide film in between, being thicker in film thickness than the gate insulating film, and an N-type extension diffusion layer 260 formed on the lower side at the side end of the gate electrode of the semiconductor substrate as well as on the lower side of the side wall and the offset side wall oxide film. The upper surface of the N-type extension diffusion layer of the semiconductor substrate is flat. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device made of a MIS (Metal-Insulator-Semiconductor) type field effect transistor and a manufacturing method thereof.

  In recent years, along with higher integration, higher functionality, and higher speed of semiconductor integrated circuit devices, miniaturization of MIS field effect transistors has progressed, and the gate length is short, for example, about 60 nm, and the thickness of the gate insulating film. Tends to be thin, for example, about 2 nm. As a result of this miniaturization, the parasitic resistance of the region where the high concentration impurity diffusion layer and the gate electrode overlap with each other on both sides of the gate electrode in the gate length direction on the semiconductor substrate overlaps the transistor characteristics. It influences driving ability.

  However, the conventional technique has a problem that the upper surface of the semiconductor substrate on which the high-concentration impurity layer is formed is dug during the manufacturing process, resulting in a deterioration in driving capability in transistor characteristics. Furthermore, the main component that determines the width dimension of the overlap region is the thickness of the so-called gate electrode side wall oxide film (offset side wall oxide film) formed on the side surface or the side portion of the gate electrode in the gate length direction. Therefore, the variation in the thickness of the offset sidewall oxide film is greatly affecting the variation in the transistor characteristics.

  Hereinafter, with reference to FIGS. 12A to 12D, a method for manufacturing a semiconductor device shown in the following Patent Document 1 in which the surface of the gate electrode is wet-oxidized and then subjected to extension implantation will be described. .

  First, as shown in FIG. 12A, a P-type well diffusion layer 15 is formed on an upper portion of a semiconductor substrate 10 made of silicon by a known method. Thereafter, a gate insulating film 16 made of silicon oxide is formed on the main surface of the semiconductor substrate 10, and then a gate electrode 22 made of polysilicon is selectively formed on the gate insulating film 16.

  Next, as shown in FIG. 11B, an offset sidewall oxide film 32 is formed on both sides of the gate electrode 22 by oxidizing the surface of the gate electrode 22 by a wet oxidation method. At this time, the upper surface of the gate electrode 22 and the region under the gate insulating film 16 in the semiconductor substrate 10 are simultaneously oxidized.

  Next, as shown in FIG. 12C, by using the gate electrode 22 and the offset sidewall oxide film 32 as a mask, an N-type impurity 24 is implanted into the upper portion of the semiconductor substrate 10 via the gate insulating film 16. An N type extension diffusion layer 26 is formed.

Next, as shown in FIG. 12D, a silicon oxide film is formed so as to cover the gate insulating film 16 and the offset sidewall oxide film 32 on the gate electrode 22 by chemical vapor deposition (CVD). (CVD oxide film) is deposited, and thereafter, the deposited CVD oxide film is entirely dry-etched to form sidewalls 34 on both sides of the gate electrode 22 from the CVD oxide film. Subsequently, an N-type source drain (S / D) diffusion layer 37 is formed by implanting an N-type impurity into the upper portion of the semiconductor substrate 10 using the gate electrode 22, the offset sidewall oxide film 32 and the sidewall 34 as a mask. Form. Thereafter, the extension diffusion layer 26 and the source drain diffusion layer 37 are activated by rapid high-temperature heat treatment.
JP 2001-168330 A

  However, the conventional method for manufacturing a semiconductor device is for forming an offset sidewall oxide film 32 before injecting an N-type impurity for forming the extension diffusion layer 26 into the upper portion of the semiconductor substrate 10. When wet oxidation is performed, both side portions of the gate electrode 22 in the gate insulating film 16 are also oxidized. Therefore, both side portions of the gate electrode 22 on the upper surface of the semiconductor substrate 10 are lower than the interface between the semiconductor substrate 10 and the lower portion of the gate electrode 22 in the gate insulating film 16.

  The digging by the oxide film on both sides of the gate electrode 22 in the semiconductor substrate 10 is formed between the channel region and the extension diffusion layer 26 formed below the gate electrode 22 in the semiconductor substrate (P-type well diffusion layer 15). A step portion is formed between them. Since this stepped portion becomes a parasitic resistance during the operation of the transistor, there is a problem that the transistor characteristics are deteriorated.

  Further, the gate insulating film 16 and the offset sidewall oxide film 32 are formed before the extension diffusion layer 26 is formed, and the side end portion of the gate electrode 22 and the gate electrode 22 are changed by the variation in the depth of the extension diffusion layer 26. There is a problem that the size of the region (overlap region) where the extension diffusion layer 26 overlaps with the gate insulating film 16 varies. The transistor characteristics vary due to the dimensional variation of the overlap region.

  In view of the above-described conventional problems, the present invention eliminates the dug-up of both sides of the gate electrode in the semiconductor substrate (semiconductor region) and reduces variations in the overlap region between the gate electrode and the extension diffusion layer. For the purpose.

  In order to achieve the above object, according to the present invention, a semiconductor device and a method for manufacturing the same are formed by reducing the thickness of an offset sidewall oxide film (first gate electrode sidewall insulating film) formed on both side surfaces of a gate electrode. The thickness is smaller than the thickness of the film, and the first gate electrode sidewall insulating film is formed before the implantation of the extension diffusion layer (impurity diffusion layer).

  Specifically, a first semiconductor device according to the present invention includes a gate insulating film formed on a semiconductor region and having a dielectric constant higher than that of silicon oxide, and a gate formed of polysilicon and formed on the gate insulating film. An electrode, a first gate electrode sidewall insulating film formed on a side surface of the gate electrode and having a thickness smaller than that of the gate insulating film, and a first gate electrode sidewall insulating film interposed on the side surface of the gate electrode A second gate electrode side wall insulating film having a thickness larger than that of the gate insulating film, a lower side edge of the gate electrode in the semiconductor region, the first gate electrode side wall insulating film, and the second gate electrode side wall insulating film. And an impurity diffusion layer formed below the film, and the upper surface of the impurity diffusion layer in the semiconductor region is flat.

  According to the first semiconductor device, since the thickness of the first gate electrode sidewall insulating film formed on the side surface of the gate electrode is smaller than that of the gate insulating film, the first sidewall for forming the offset sidewall is formed. In the step of forming the gate electrode sidewall insulating film, a new insulating layer such as an oxide layer is not formed on the impurity diffusion layer. Therefore, digging of the upper portion of the semiconductor region due to the newly formed insulating layer on the upper portion of the semiconductor region does not occur. In addition, there is no problem of a decrease in the absolute amount of impurities implanted when forming the impurity diffusion layer. Accordingly, it is possible to realize a MIS field effect transistor having no parasitic resistance during operation and excellent driving ability.

  A second semiconductor device according to the present invention includes an NMIS field effect transistor and a PMIS field effect transistor formed in a semiconductor region, and the NMIS field effect transistor is formed in a P type well diffusion formed in an upper portion of the semiconductor region. A gate insulating film formed on the semiconductor region and having a dielectric constant higher than that of silicon oxide; an NMIS gate electrode made of polysilicon formed on the P-type well diffusion layer with a gate insulating film interposed therebetween; The first NMIS gate electrode side wall insulating film formed on the side surface of the NMIS gate electrode and having a thickness smaller than that of the gate insulating film, and the first NMIS gate electrode side wall insulating film interposed on the side surface of the NMIS gate electrode And a second NMIS gate electrode sidewall insulating film having a thickness greater than that of the gate insulating film, and an NMIS gate electrode in the P-type well diffusion layer. And an N-type impurity diffusion layer formed below the first NMIS gate electrode side wall insulating film and the second NMIS gate electrode side wall insulating film. An N-type well diffusion layer formed on the semiconductor region by a P-type well diffusion layer and an element isolation layer; a gate insulating film formed on the semiconductor region; and an N-type well diffusion layer. A PMIS gate electrode made of polysilicon and formed on the side surface of the PMIS gate electrode, the first PMIS gate electrode sidewall insulating film being thinner than the gate insulating film, A second PMIS gate electrode sidewall insulating film formed on the side surface of the gate electrode with a first PMIS gate electrode sidewall insulating film interposed therebetween and thicker than the gate insulating film; and an N-type well diffusion layer A P-type impurity diffusion layer formed on the lower side of the side end portion of the PMIS gate electrode and on the lower side of the first PMIS gate electrode side wall insulating film and the second PMIS gate electrode side wall insulating film. The upper surface of the N-type impurity diffusion layer in the well diffusion layer and the upper surface of the P-type impurity diffusion layer in the N-type well diffusion layer are flat.

  According to the second semiconductor device, the first and second gate electrode sidewall insulating films formed on the side surfaces of the NMIS gate electrode and the PMIS gate electrode are thinner than the gate insulating film. Therefore, a new insulating layer such as an oxide layer is not formed on the impurity diffusion layer in the step of forming the first and second gate electrode sidewall insulating films for forming the offset sidewall. For this reason, the upper digging of the semiconductor region due to the new insulating layer formed on the upper portion of the semiconductor region does not occur. Further, there is no problem that the impurities implanted when forming the N-type and P-type impurity diffusion layers are reduced. Therefore, an NMIS type and PMIS type field effect transistor having no parasitic resistance during operation and excellent driving ability can be realized.

  A first method for manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film having a dielectric constant higher than that of silicon oxide on a semiconductor region, and a gate electrode forming film made of polysilicon on the gate insulating film. Forming a gate electrode made of polysilicon by patterning the gate electrode formation film, leaving a gate insulating film on both sides of the gate electrode in the semiconductor region, and forming a gate electrode in the semiconductor region. A step of forming an impurity diffusion layer in the semiconductor region by implanting impurity ions through the gate insulating film as a mask, and after forming the impurity diffusion layer, a gate insulating film is formed on the side surface of the gate electrode by an oxidation method And a step of forming a gate electrode side wall insulating film having a smaller film thickness.

  According to the first method for manufacturing a semiconductor device, after forming an impurity diffusion layer to be an extension diffusion layer, a gate electrode sidewall insulating film (offset side) having a thickness smaller than that of the gate insulating film is formed on the side surface of the gate electrode by an oxidation method. Wall). For this reason, the width of the overlap region where the gate electrode and the impurity diffusion layer overlap is reduced from the diffusion length of the impurity diffusion layer by the subsequent activation annealing due to the formation of the offset sidewall on the side edge of the gate electrode. The value after subtracting minutes. On the other hand, in the conventional technique, after forming the offset sidewall, an impurity diffusion layer to be an extension diffusion layer is formed. Therefore, the width of the overlap region is determined from the diffusion length of the impurity diffusion layer by activation annealing. The value is obtained by subtracting the wall thickness. Here, the variation in the film thickness of the offset sidewall in the overlap region of the prior art is in the direction in which the opposite side surfaces of the gate electrode face each other in addition to the film thickness variation caused by oxidation or the like at the side edge of the gate electrode. Including variation due to oxidation growth. Therefore, in contrast to the variation in the width of the overlap region in the prior art, the present invention can further reduce the variation in the width of the overlap region. Therefore, it is possible to realize a MIS field effect transistor having excellent short channel characteristics and driving capability.

  The second method of manufacturing a semiconductor device according to the present invention includes a step (a) of forming a P-type well diffusion layer and an N-type diffusion layer separated by an element isolation layer in a semiconductor region, a P-type well diffusion layer, and an N-type diffusion layer. A step (b) of forming a gate insulating film having a dielectric constant higher than that of silicon oxide on the mold diffusion layer; a step (c) of forming a gate electrode forming film made of polysilicon on the gate insulating film; By patterning the gate electrode formation film, an NMIS gate electrode made of polysilicon is formed on the P-type well diffusion layer, a PMIS gate electrode made of polysilicon is formed on the N-type well diffusion layer, and a semiconductor (D) leaving gate insulating films on both sides of the NMIS gate electrode and the PMIS gate electrode in the region, and the NMIS gate electrode in the P-type well diffusion layer after step (d) By implanting N-type impurity ions through the gate insulating film as a mask, an N-type impurity diffusion layer is formed in the P-type well diffusion layer, and N-type impurity ions are implanted into at least the side of the NMIS gate electrode. After step (e) and step (d), P-type impurity ions are implanted into the N-type well diffusion layer using the PMIS gate electrode as a mask and through the gate insulating film, so that P-type impurity is diffused into the N-type well diffusion layer. A step (f) of forming a p-type impurity diffusion layer and implanting p-type impurity ions into at least a side portion of the PMIS gate electrode; and after the steps (e) and (f), the NMIS gate electrode and the PMIS gate electrode A step (g) of forming a gate electrode sidewall insulating film having a thickness smaller than that of the gate insulating film by an oxidation method on each of the side surfaces.

  According to the second method for manufacturing a semiconductor device, an N-type impurity diffusion layer is formed in a P-type well diffusion layer, N-type impurity ions are implanted into at least a side portion of the NMIS gate electrode, and the N-type well diffusion layer is formed. After forming a P-type impurity diffusion layer and implanting P-type impurity ions into at least the side of the PMIS gate electrode, the gate is thinner on each side of the NMIS gate electrode and the PMIS gate electrode than the gate insulating film. An electrode sidewall insulating film is formed. Therefore, the thickness of the insulating film formed on the side of the PMIS gate electrode implanted with the P-type impurity having a larger oxidation coefficient than the thickness of the insulating film on the side of the NMIS gate electrode implanted with the N-type impurity. Is thicker. On the other hand, the P-type impurity injected into the P-type impurity diffusion layer has a larger diffusion length during the activation process by annealing than the N-type impurity injected into the N-type impurity diffusion layer formed in the semiconductor region. Therefore, an overlap region between the NMIS gate electrode and the N-type impurity diffusion layer and an overlap region between the PMIS gate electrode and the P-type impurity diffusion layer are formed in a self-aligned manner. Therefore, an NMIS type and PMIS type field effect transistor excellent in short channel characteristics and driving capability can be realized.

  The third method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a P-type well diffusion layer and an N-type diffusion layer separated by an element isolation layer in a semiconductor region, a P-type well diffusion layer, and an N-type diffusion layer. A step (b) of forming a gate insulating film having a dielectric constant higher than that of silicon oxide on the mold diffusion layer; a step (c) of forming a gate electrode forming film made of polysilicon on the gate insulating film; By patterning the gate electrode formation film, an NMIS gate electrode made of polysilicon is formed on the P-type well diffusion layer, a PMIS gate electrode made of polysilicon is formed on the N-type well diffusion layer, and a semiconductor (D) leaving gate insulating films on both sides of the NMIS gate electrode and the PMIS gate electrode in the region, and the NMIS gate electrode in the P-type well diffusion layer after step (d) By implanting N-type impurity ions through the gate insulating film as a mask, an N-type impurity diffusion layer is formed in the P-type well diffusion layer, and N-type impurity ions are implanted into at least the side of the NMIS gate electrode. Step (e) and a step of forming a gate electrode sidewall insulating film having a thickness smaller than that of the gate insulating film on each side surface of the NMIS gate electrode and the PMIS gate electrode by an oxidation method after the step (e). After (f) and step (f), P-type impurity ions are implanted into the N-type well diffusion layer using the PMIS gate electrode as a mask and through the gate insulating film, so that the N-type well diffusion layer is P-type. And a step (g) of forming an impurity diffusion layer.

  According to the third method of manufacturing a semiconductor device, an N-type impurity diffusion layer is formed in a P-type well diffusion layer and N-type impurity ions are implanted into at least a side portion of the NMIS gate electrode, and then an NMIS gate electrode and a PMIS gate electrode A gate electrode sidewall insulating film having a thickness smaller than that of the gate insulating film is formed on each of the side surfaces. Thereafter, a P-type impurity diffusion layer is formed in the N-type well diffusion layer. For this reason, the film thickness of the insulating film formed by oxidizing the side portion of the NMIS gate electrode into which the N-type impurity is implanted is formed on the side portion of the PMIS gate electrode in a state where the P-type impurity is not implanted into the side portion. This is almost the same as the thickness of the insulating film. In a semiconductor device, an N-type extension diffusion layer, an N-type source drain diffusion layer, a P-type extension diffusion layer, and a P-type source drain diffusion layer are annealed to activate the N-type extension diffusion layer. In order for the N-type impurity forming the extension diffusion layer to have an overlap region with the NMIS gate electrode, an offset sidewall oxide film (gate electrode sidewall insulating film) formed by oxidizing at least the side of the NMIS gate electrode It is necessary to thermally diffuse a distance of about half the thickness. On the other hand, in order for the P-type impurity forming the P-type extension diffusion layer in the N-type well diffusion layer to have an overlap region with the PMIS gate electrode, at least the side of the PMIS gate electrode is oxidized to form an offset side. It is necessary to thermally diffuse a distance corresponding to the thickness of the wall oxide film. By the way, the P-type impurity of the P-type extension diffusion layer has a larger diffusion length when activated by the annealing process than the N-type impurity of the N-type extension diffusion layer. As a result, an overlap region between the NMIS gate electrode and the N-type extension diffusion layer and an overlap region between the PMIS gate electrode and the P-type extension diffusion layer are formed in a self-aligned manner. Therefore, an NMIS type and PMIS type field effect transistor excellent in short channel characteristics and driving capability can be realized.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, the digging of both sides of the gate electrode in the semiconductor substrate or the semiconductor region is eliminated, and the variation of the overlap region between the gate electrode and the extension diffusion layer (impurity diffusion layer) is eliminated. Is reduced. Thereby, it is possible to realize a MIS type semiconductor device having excellent short channel characteristics and excellent driving capability.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a cross-sectional configuration of a main part of a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, a gate electrode 220 with a gate insulating film 160 interposed is formed on the main surface of a semiconductor substrate 100 made of silicon (Si), on which a P-type well diffusion layer 150 is formed. ing. The gate electrode 220 is a gate insulating film 160 having a desired size and a polysilicon film in which, for example, an N-type impurity such as phosphorus (P), arsenic (As), or antimony (Sb) is implanted into a non-doped polysilicon film. Is patterned so as to be located at the center portion in the gate length direction.

The gate insulating film 160 is an insulating film for the gate electrode 220 in the N-type MIS field effect transistor, and at the same time, is an antioxidant film for preventing oxidation of the surface of the semiconductor substrate 100 on which the P-type well diffusion layer 150 is formed. . The constituent material of the gate insulating film 160 has a dielectric constant higher than that of silicon oxide (SiO ₂ ), for example, silicon nitride (SiN), hafnium silicon oxide (HfSiO), hafnium silicon nitride (HfSiN), hafnium oxynitride (HfON) ), Hafnium oxide (HfO ₂ ), hafnium aluminum oxide (HfAlO), lanthanum aluminum oxide (LaAlO ₃ ), ruthenium oxide (Lu ₂ O ₃ ), praseodymium oxide (Pr ₂ O ₃ ), zirconium oxide (ZrO ₂ ), oxide Tantalum (Ta ₂ O ₅ ), dysprosium oxide (Dy ₂ O ₃ ), gadolinium oxide (Gd ₂ O ₃ ), or the like can be used.

  An N-type extension diffusion layer 260 is formed on both sides of the gate electrode 220 in the semiconductor substrate 100 and immediately below the gate insulating film 160, and a P-type pocket diffusion layer is formed below the N-type extension diffusion layer 260. 310 is formed.

  On both side surfaces of the gate electrode 220 and on the gate insulating film 160, an offset sidewall oxide film 320 having an L-shaped cross section as a first gate electrode sidewall insulating film is formed by thermal oxidation. . Here, the thickness (physical film thickness) of the offset sidewall oxide film 320 is formed thinner than the film thickness (physical film thickness) of the gate insulating film 160. On the outer side surface and bottom surface of the offset sidewall oxide film 320, a sidewall 340, which is a laminated film of silicon oxide and silicon nitride, is formed as a second gate electrode sidewall insulating film.

  An N-type source drain (S / D) diffusion layer 370 is formed in a region outside the sidewall 340 above the P-type well diffusion layer 150.

  In the semiconductor device according to the first embodiment, since the thickness of the gate insulating film 160 having a function of preventing the semiconductor substrate 100 from being oxidized is larger than the thickness of the offset sidewall oxide film 320, the offset sidewall oxide film In the thermal oxidation process for forming 320, the surface of the semiconductor substrate 100 on which the N-type extension diffusion layer 260 is formed is hardly oxidized. For this reason, the reduction | decrease (digging) of the substrate surface which arises when the surface of the semiconductor substrate 100 is oxidized does not arise. In addition, there is no problem that impurities implanted for forming the N-type extension diffusion layer 260 are reduced.

  Therefore, it is possible to realize a MIS field effect transistor having excellent short channel characteristics and driving capability.

  In the first embodiment, an N-type MIS field effect transistor is shown. However, the present invention can also be applied to a semiconductor device including a P-type MIS field effect transistor.

  Hereinafter, a method of manufacturing the semiconductor device configured as described above will be described with reference to the drawings.

  2A to FIG. 2D, FIG. 3A to FIG. 3D, and FIG. 4A to FIG. 4D are N-type MISs according to the first embodiment of the present invention. The cross-sectional structure in order of the process of the manufacturing method of a field effect transistor is shown.

First, as shown in FIG. 2A, P-type impurities such as boron (B), boron fluoride (BF ₂ ), indium (In), or cluster ions are formed on the semiconductor substrate 100 made of silicon. (B ₁₀ H ₁₄ , B ₁₈ H ₂₂ ) is ion-implanted at a dose of about 1 × 10 ¹³ / cm ² to form a P-type well diffusion layer 150. Thereafter, for example, the dielectric constant of silicon nitride or hafnium silicon oxide described above is higher than that of silicon oxide by atomic layer deposition (ALD) method or metal-organic chemical vapor deposition (MOCVD) method. A gate insulating film 160 made of a high dielectric material and having a film thickness (physical film thickness) of about 10 nm is formed on the main surface of the semiconductor substrate 100 on which the P-type well diffusion layer 150 is formed.

  Next, as shown in FIG. 2B, a non-doped polysilicon film to which an impurity having a thickness of about 150 nm is not added on the gate insulating film 160 formed on the semiconductor substrate 100 by, for example, the CVD method. 170A is deposited.

Next, as shown in FIG. 2C, the first N-type impurity 200 made of, for example, phosphorus, arsenic, or antimony is applied to the non-doped polysilicon film 170A with an acceleration energy of ¹⁵ keV and 1 × 10 ^15. By implanting at a dose of about / cm ² , a polysilicon film 170B doped with a first N-type impurity is formed.

  Next, as shown in FIG. 2D, a resist pattern 330 having a gate electrode formation pattern is formed on the polysilicon film 170B doped with the first N-type impurity by lithography.

  Next, as shown in FIG. 3A, the polysilicon film 170B is patterned by dry etching, for example, using the resist pattern 330 as a mask to form the gate electrode 220 from the polysilicon film 170B. Thereafter, the resist pattern 330 is removed by ashing or cleaning. Here, the gate length Lg of the gate electrode 220 is about 60 nm.

Next, as shown in FIG. 3B, a second N-type impurity 240 made of, for example, phosphorus, arsenic, antimony, or the like is formed on the semiconductor substrate 100 through the gate insulating film 160 using the gate electrode 220 as a mask. Implantation is performed with an acceleration energy of 3 keV and a dose of about 1 × 10 ¹⁵ / cm ² . As a result, an N-type extension diffusion layer 260 in which the second N-type impurity is implanted is formed on the P-type well diffusion layer 150. At this time, the second N-type impurity is also implanted into both sides of the gate electrode 220.

Next, as illustrated in FIG. 3C, for example, boron, boron fluoride, indium, or cluster ions (B ₁₀ H ₁₄ , B) are formed on the semiconductor substrate 100 through the gate insulating film 160 using the gate electrode 220 as a mask. P type impurities 290 made of B ₁₈ H ₂₂ ) or the like are implanted at an acceleration energy of 10 keV and a dose of about 1 × 10 ¹³ / cm ^2, so that the N type extension diffusion layer 260 of the P type well diffusion layer 150 is formed. A P-type pocket diffusion layer 310 is formed on the lower side.

Next, as shown in FIG. 3D, the gate electrode 220 is subjected to thermal oxidation for about 10 minutes in an ozone (O ₃ ) atmosphere at a temperature of about 400 ° C. An offset sidewall oxide film 320 having a film thickness of 6 nm is formed on the portion. At this time, the thickness of the offset sidewall oxide film 320 is made thinner than the thickness of the gate insulating film 160. The offset sidewall oxide film 320 controls the width of a region (overlap region) where the gate electrode 220 and the N-type extension diffusion layer 260 overlap with the gate insulating film 160 interposed therebetween.

  Next, a gate is formed on the semiconductor substrate 100 by a low pressure-chemical vapor deposition (LP-CVD) method or an atmospheric pressure-chemical vapor deposition (AP-CVD) method. A silicon oxide film having a thickness of about 10 nm and a silicon nitride film having a thickness of about 50 nm are deposited over the entire surface including the electrode 220 and the offset sidewall oxide film 320. Thereafter, the deposited silicon nitride film and silicon oxide film are etched back over the entire surface, thereby forming the gate electrode 220 on both side surfaces of the gate electrode 220 and the gate insulating film 160 as shown in FIG. A sidewall 340 made of a laminated film of a silicon oxide film and a silicon nitride film with an offset sidewall oxide film 320 interposed is formed on the both side portions.

Next, as shown in FIG. 4B, a third N type made of, for example, phosphorus, arsenic, antimony, or the like is formed on the semiconductor substrate 100 using the gate electrode 220, the offset sidewall oxide film 320, and the sidewall 340 as a mask. Impurities are implanted at an acceleration energy of 30 keV and a dose of about 2 × 10 ¹⁵ / cm ² . As a result, the N-type source drain (S / D) diffusion layer 370 is located on both sides of the gate electrode 220 in the P-type well diffusion layer 150 and outside the N-type extension diffusion layer 260 and the P-type pocket diffusion layer 310. Is formed. Subsequently, a rapid thermal annealing (RTA) process is performed at a temperature of 1050 ° C. for about 20 seconds, whereby the N-type extension diffusion layer 260, the P-type pocket diffusion layer 310, and the N-type S / D diffusion layer 370 are processed. Are activated respectively. By this step, a region (overlap region) where the gate electrode 220 and the N-type extension diffusion layer 260 overlap with the gate insulating film 160 interposed therebetween is determined.

Next, as shown in FIG. 4C, cobalt silicide (CoSi ₂ ) or nickel silicide (NiSi) or the like is formed on the upper portion of the gate electrode 220 and the upper portion of the N-type S / D diffusion layer 370 by a known technique. A silicide layer 390 is formed to reduce the resistance of the gate electrode 220 and the N-type S / D diffusion layer 370.

  Next, as shown in FIG. 4 (d), silicon oxide is used to cover the silicided N-type S / D diffusion layer 370, the silicided gate electrode 220, and the sidewalls 340 by a known technique. An interlayer film buffer layer 400 and an interlayer insulating film 410 are deposited. Subsequently, after planarizing the upper surface of the deposited interlayer insulating film 410, a contact hole exposing one of the N-type S / D diffusion layers 370 is formed in the interlayer insulating film 410 and the interlayer film buffer layer 400. Thereafter, a contact barrier metal 420 is formed along the bottom and wall surfaces of the formed contact hole, and a contact plug 430 is filled on the contact barrier metal 420. Subsequently, a metal wiring 440 is selectively formed on the interlayer insulating film 410 so as to be connected to the contact plug 430 to obtain the semiconductor device according to the first embodiment.

  In the above-described prior art, after the gate electrode 22 is oxidized to form the offset sidewall oxide film 32, the impurity implantation for forming the extension diffusion layer 26 is performed. As shown in FIG. 12D, the width of the overlapping region (overlap region) is a value obtained by subtracting the thickness of the offset sidewall oxide film 32 from the diffusion length Δd of the extension diffusion layer 26, that is, [Expression 1]

(Overlap region) = (diffusion length Δd of extension diffusion layer) − (film thickness of offset sidewall oxide film)... [Formula 1]
On the other hand, in the first embodiment, after the impurity implantation for forming the extension diffusion layer 260 is performed, the oxidation for forming the offset sidewall oxide film 320 is performed. This is a value obtained by subtracting the film loss due to the oxidation of the side portion of the gate electrode 220 from the diffusion length Δd of the extension diffusion layer 260 shown in FIG. 3B, and is expressed by the following [Equation 2].

(Overlap region) = (diffusion length Δd of extension diffusion layer) − (film reduction amount due to oxidation of gate electrode side wall)... [Formula 2]
The variation in the thickness of the offset sidewall oxide film in the overlap region of the prior art shown in [Equation 1] is not only the variation caused by the film thickness reduction due to oxidation on the side of the gate electrode, but also the both sides of the gate electrode in the gate length direction. It also includes variations caused by the oxidative growth of the surfaces facing each other.

  Therefore, in the first embodiment, the overlap of the width of the overlap region of the prior art does not include the variation caused by the oxidation growth of both side surfaces of the gate electrode facing the gate length direction. Variation in the width of the region can be reduced.

  In addition, in the first embodiment, since the thickness of the gate insulating film 160 that prevents the semiconductor substrate 100 from being oxidized is larger than the thickness of the offset sidewall oxide film 320, the offset sidewall oxide film 320 is formed. In the thermal oxidation process, the surface of the semiconductor substrate 100 on which the N-type extension diffusion layer 260 is formed is hardly oxidized. For this reason, the problem that the surface of the silicon layer of the semiconductor substrate 100 is lowered (digged) by thermal oxidation does not occur. Further, there is no problem that impurities implanted into the N-type extension diffusion layer 260 are reduced.

  Therefore, it is possible to realize a MIS field effect transistor having excellent short channel characteristics and driving capability.

  In the first embodiment, the N-type MIS field effect transistor and the manufacturing method thereof have been described. However, the present invention can also be applied to a P-type MIS field effect transistor.

  Further, the offset sidewall oxide film 320 formed on the side surface of the gate electrode 220 may be formed by an inductively coupled plasma oxidation method formed at room temperature.

(Second Embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to the drawings.

  5 (a) to 5 (c), FIG. 6 (a) to FIG. 6 (c), FIG. 7 (a) to FIG. 7 (c) and FIG. 8 (a) to FIG. 10 shows a cross-sectional configuration in the order of steps of a method for manufacturing a complementary MIS field effect transistor according to the second embodiment.

First, as shown in FIG. 5A, a trench is selectively formed on an upper portion of a semiconductor substrate 100 made of silicon (Si), and an insulating film is buried in the formed trench to form an element isolation layer (shallow). trench isolation (STI) 110 is formed. As a result, the semiconductor substrate 100 is partitioned into the NMIS region 120 and the PMIS region 130. Thereafter, P-type impurities such as boron (B), boron fluoride (BF ₂ ), indium (In), or cluster ions (B ₁₀ H ₁₄ , B ₁₈ H ₂₂ ) are formed on the NMIS region 120. P-type well diffusion layer 150 is formed by implanting at a dose of about 1 × 10 ¹³ / cm ² . Subsequently, an N-type impurity such as phosphorus (P), arsenic (As), or antimony (Sb) is implanted into the upper portion of the PMIS region 130 at a dose of about 1 × 10 ¹³ / cm ² . An N-type well diffusion layer 140 is formed. The order of forming the P-type well diffusion layer 150 and the N-type well diffusion layer 140 is not particularly limited. Thereafter, the gate insulating film 160 made of a dielectric having a dielectric constant higher than that of silicon oxide and having a film thickness (physical film thickness) of about 10 nm is formed on the P-type well diffusion layer by, for example, atomic layer deposition or metal organic chemical vapor deposition. 150 and the N-type well diffusion layer 140 are formed on the main surface of the semiconductor substrate 100 formed thereon.

Here, the gate insulating film 160 is an insulating film of the MIS field effect transistor, and at the same time, an antioxidant that prevents oxidation of the surface of the semiconductor substrate 100 on which the P-type well diffusion layer 150 and the N-type well diffusion layer 140 are formed. It is a membrane. As in the first embodiment, the gate insulating film material may be, for example, silicon nitride (SiN), hafnium silicon oxide (HfSiO), hafnium silicon nitride (HfSiN), hafnium oxynitride (HfON), hafnium oxide ( HfO ₂ ), hafnium aluminum oxide (HfAlO), lanthanum aluminum oxide (LaAlO ₃ ), ruthenium oxide (Lu ₂ O ₃ ), praseodymium oxide (Pr ₂ O ₃ ), zirconium oxide (ZrO ₂ ), tantalum oxide (Ta ₂ O) ₅ ), dysprosium oxide (Dy ₂ O ₃ ), gadolinium oxide (Gd ₂ O ₃ ), or the like can be used.

Next, as shown in FIG. 5B, a non-doped polysilicon film 170A having a thickness of about 150 nm is deposited on the gate insulating film 160 formed on the semiconductor substrate 100 by, for example, the CVD method. Subsequently, a first resist pattern 330 that covers the PMIS region 130 is formed on the non-doped polysilicon film 170A by lithography. Subsequently, using the first resist pattern 330 as a mask, the first N-type impurity 200 made of, for example, phosphorus, arsenic, or antimony is applied to the non-doped polysilicon film 170A with an acceleration energy of ¹⁵ keV and 1 × 10 ^15. By implanting at a dose of about / cm ² , a polysilicon film 170B doped with a first N-type impurity is formed in the NMIS region 120 of the non-doped polysilicon film 170A.

Next, as shown in FIG. 5C, after removing the first resist pattern 330, a second resist pattern 331 covering the NMIS region 120 is formed on the polysilicon film 170B by lithography. . Subsequently, using the second resist pattern 331 as a mask, for example, boron, boron fluoride, indium, or cluster ions (B ₁₀ H ₁₄ , B ₁₈ H ₂₂ ) or the like with respect to the non-doped polysilicon film 170 A in the PMIS region 130. The first P-type impurity 210 is implanted at a dose of about 1 × 10 ¹⁵ / cm ² with an acceleration energy of 2 keV, so that the first P-type impurity is doped from the non-doped polysilicon film 170A. A polysilicon film 170C is formed.

  Next, as shown in FIG. 6A, after removing the second resist pattern 331, an NMIS gate electrode formation pattern is formed on the polysilicon film 170B doped with the first N-type impurity by lithography. And a third resist pattern 332 having a PMIS gate electrode formation pattern is formed on the polysilicon film 170C doped with the first P-type impurity.

  Next, as shown in FIG. 6B, the polysilicon film 170B in the NMIS region 120 and the polysilicon film 170C in the PMIS region 130 are patterned by dry etching, for example, using the third resist pattern 332 as a mask. An NMIS gate electrode 220 is formed from the polysilicon film 170B, and a PMIS gate electrode 230 is formed from the polysilicon film 170C. Thereafter, the third resist pattern 330 is removed by ashing or cleaning. Here, each gate length Lg of the NMIS gate electrode 220 and the PMIS gate electrode 230 is about 60 nm.

Next, as shown in FIG. 6C, a fourth resist pattern 333 covering the PMIS region 130 including the PMIS gate electrode 230 is formed by lithography. Subsequently, using the formed fourth resist pattern 333 and the NMIS gate electrode 220 as a mask, the second N-type impurity 240 made of, for example, phosphorus, arsenic, or antimony is about 3 keV through the gate insulating film 160. Implantation is performed with acceleration energy and a dose of about 1 × 10 ¹⁵ / cm ² . As a result, an N-type extension diffusion layer 260 in which the second N-type impurity is implanted is formed on the P-type well diffusion layer 150. At this time, the second N-type impurity is also implanted into both sides of the NMIS gate electrode 220.

Next, as shown in FIG. 7A, for example, boron, boron fluoride, indium, or cluster ions (for example, boron ion, boron fluoride, indium, or cluster ions (through the gate resist film 160) using the fourth resist pattern 333 and the NMIS gate electrode 220 as a mask. By implanting a third P-type impurity 290 made of B ₁₀ H ₁₄ , B ₁₈ H ₂₂ ) or the like with an acceleration energy of about 10 keV and a dose of about 1 × 10 ¹³ / cm ² , a P-type well diffusion layer A P-type pocket diffusion layer 310 is formed below the N-type extension diffusion layer 260 at 150. Thereafter, the fourth resist pattern 333 is removed by ashing or cleaning.

Next, as shown in FIG. 7B, a fifth resist pattern 334 covering the NMIS region 120 including the NMIS gate electrode 220 is formed by lithography. Subsequently, for example, boron, boron fluoride, indium, or cluster ions (B ₁₀ H ₁₄ , B ₁₈ H ₂₂₎ are formed through the gate resist film 160 using the formed fifth resist pattern 334 and the PMIS gate electrode 230 as a mask. ) And the like are implanted at an acceleration energy of about 1 keV and a dose of about 1 × 10 ¹⁵ / cm ² . As a result, the P-type extension diffusion layer 270 in which the third P-type impurity is implanted is formed on the N-type well diffusion layer 140. At this time, the third P-type impurity is also implanted into both sides of the PMIS gate electrode 230.

Next, as shown in FIG. 7C, the third resist pattern 334 and the PMIS gate electrode 230 are used as a mask again and the third insulating film 160 made of, for example, phosphorus, arsenic, or antimony is interposed through the gate insulating film 160. By implanting the N-type impurity 280 with an acceleration energy of 30 keV and a dose of about 1 × 10 ¹³ / cm ² , the N-type pocket diffusion layer is formed below the P-type extension diffusion layer 270 in the N-type well diffusion layer 140. 300 is formed. Thereafter, the fifth resist pattern 334 is removed by ashing or cleaning.

Next, as shown in FIG. 8A, the NMIS gate electrode 220 and the PMIS gate electrode 230 are subjected to thermal oxidation for about 10 minutes in an ozone (O ₃ ) atmosphere at a temperature of about 400 ° C. An offset sidewall oxide film 320 having a thickness of 6 nm is formed on each upper part and both sides of the gate electrode 220 and the PMIS gate electrode 230. At this time, the thickness of the offset sidewall oxide film 320 is made thinner than the thickness of the gate insulating film 160. The offset sidewall oxide film 320 causes the NMIS gate electrode 220 and the N-type extension diffusion layer 260 and the PMIS gate electrode 230 and the P-type extension diffusion layer 270 to overlap with each other via the gate insulating film 160 (overlap region). The width of is controlled. Here, the thickness of the offset sidewall oxide film 320 formed on the side surface and the upper surface of the PMIS gate electrode 230 is larger than the thickness of the offset sidewall oxide film 320 formed on the side surface and the upper surface of the NMIS gate electrode 220. 1.1 times thicker.

  Next, the film thickness is increased over the entire surface including the NMIS gate electrode 220, the PMIS gate electrode 230, and each offset sidewall oxide film 320 on the semiconductor substrate 100 by low pressure chemical vapor deposition or atmospheric pressure chemical vapor deposition. A silicon oxide film having a thickness of about 10 nm and a silicon nitride film having a thickness of about 50 nm are deposited. Thereafter, the deposited silicon nitride film and silicon oxide film are etched back over the entire surface, thereby forming an NMIS gate on both side surfaces of the NMIS gate electrode 220 and in the gate insulating film 160 as shown in FIG. Silicon oxide with offset sidewall oxide films 320 interposed on both side portions of the electrode 220 and on both side surfaces of the PMIS gate electrode 230 and on both side portions of the PMIS gate electrode 230 in the gate insulating film 160, respectively. A sidewall 340 made of a laminated film of a film and a silicon nitride film is formed.

Thereafter, an N-type source drain (S / D) diffusion layer 370 is formed in the NMIS region 120 of the semiconductor substrate 100, and then a P-type source drain (S / D) diffusion layer 380 is formed in the PMIS region 130. Specifically, the PMIS region 130 is covered with a resist film (not shown), and the NMIS gate electrode 220, the offset sidewall oxide film 320, and the sidewall 340 are used as a mask on the semiconductor substrate 100, for example, phosphorus, arsenic, antimony, or the like. The fourth N-type impurity is implanted at an acceleration energy of about 30 keV and a dose of about 2 × 10 ¹⁵ / cm ² . As a result, the N-type source drain (S / S) is formed on both sides of the NMIS gate electrode 220 in the P-type well diffusion layer 150 of the NMIS region 120 and outside the N-type extension diffusion layer 260 and the P-type pocket diffusion layer 310. D) A diffusion layer 370 is formed. Subsequently, after removing the resist film covering the PMIS region 130, the NMIS region 120 is covered with a resist film (not shown), and the PMIS gate electrode 230, the offset sidewall oxide film 320 and the sidewall 340 are used as a mask. A fourth P-type impurity made of, for example, boron, boron fluoride, indium, or cluster ions (B ₁₀ H ₁₄ , B ₁₈ H ₂₂ ) or the like is added to the substrate 100 with an acceleration energy of about 2 keV and about 2 × 10 ¹⁵ / cm ^2. Inject at a dose of. As a result, the P-type source drain (S / S) is formed on both sides of the PMIS gate electrode 230 in the N-type well diffusion layer 140 of the PMIS region 130 and outside the P-type extension diffusion layer 270 and the N-type pocket diffusion layer 300. D) A diffusion layer 380 is formed. The formation order of the N-type S / D diffusion layer 370 and the P-type S / D diffusion layer 380 is not particularly limited.

  Subsequently, the N-type extension diffusion layer 260, the P-type pocket diffusion layer 310, and the N-type S / D diffusion layer 370 are formed in the NMIS region 120 by performing a rapid high-temperature heat treatment at a temperature of 1050 ° C. for about 20 seconds, for example. In addition, the P-type extension diffusion layer 270, the N-type pocket diffusion layer 300, and the P-type S / D diffusion layer 380 are activated in the PMIS region 130, respectively.

  By this step, a region where the NMIS gate electrode 220 and the N-type extension diffusion layer 260 overlap with the gate insulating film 160 interposed therebetween (overlap region), and the PMIS gate electrode 230 and the P-type extension diffusion layer 270 form the gate insulating film. An overlapping area (overlap area) is determined with 160 interposed.

  Thereafter, cobalt silicide or nickel is formed on the upper portion of the NMIS gate electrode 220 and the upper portion of the N-type S / D diffusion layer 370, the upper portion of the PMIS gate electrode 230, and the upper portion of the P-type S / D diffusion layer 380 by a known technique. A silicide layer 390 such as silicide is formed to reduce the resistance of the NMIS gate electrode 220 and the N-type S / D diffusion layer 370, as well as the PMIS gate electrode 230 and the P-type S / D diffusion layer 380.

  Next, as shown in FIG. 8C, the silicided N-type S / D diffusion layer 370 and the P-type S / D diffusion layer 380, the silicided NMIS gate electrode 220, and the PMIS are formed by a known technique. An interlayer buffer layer 400 made of silicon oxide and an interlayer insulating film 410 are deposited so as to cover the gate electrode 230. Subsequently, after planarizing the upper surface of the deposited interlayer insulating film 410, one of the N-type S / D diffusion layer 370 and one of the P-type S / D diffusion layer 380 is formed on the interlayer insulating film 410 and the interlayer film buffer layer 400. A contact hole is formed to expose each of. Thereafter, a contact barrier metal 420 is formed along the bottom and wall surfaces of each formed contact hole, and a contact plug 430 is filled on each contact barrier metal 420. Subsequently, a metal wiring 440 is selectively formed on the interlayer insulating film 410 so as to be connected to the contact plugs 430, thereby obtaining a complementary semiconductor device according to the second embodiment.

  In the above-described prior art, after the gate electrode 22 is oxidized to form the offset sidewall oxide film 32, the impurity implantation for forming the extension diffusion layer 26 is performed. As shown in FIG. 12D, the width of the overlapping region (overlap region) is a value obtained by subtracting the film thickness of the offset sidewall oxide film 32 from the diffusion length Δd of the extension diffusion layer 26, that is, [Expression 1]

  In contrast, in the second embodiment, after the impurity implantation for forming the extension diffusion layers 260 and 270 is performed, the oxidation for forming the offset sidewall oxide film 320 is performed. FIG. 8B shows a value obtained by subtracting the film loss due to the oxidation of the side portion of the NMIS gate electrode 220 from the diffusion length Δd of the N-type extension diffusion layer 260 shown in FIG. . The same applies to the P-type extension diffusion layer 270.

  The variation in the thickness of the offset sidewall oxide film in the overlap region of the prior art shown in [Equation 1] is opposite to the gate electrode in the gate length direction in addition to the variation caused by the film thickness reduction due to oxidation at the side of the gate electrode. It also includes variations caused by oxidation growth on both side surfaces.

  Accordingly, in the second embodiment, the overlap of the overlap region of the conventional technique does not include the variation caused by the oxidation growth of both side surfaces of the gate electrode facing the gate length direction. Variation in the width of the region can be reduced.

  In addition, in the second embodiment, the thickness of the gate insulating film 160 that prevents the semiconductor substrate 100 from being oxidized is larger than the thickness of the offset sidewall oxide film 320, and thus the offset sidewall oxide film 320 is formed. In the thermal oxidation process, the surface of the semiconductor substrate 100 on which the N-type extension diffusion layer 260 and the P-type extension diffusion layer 270 are formed is hardly oxidized. For this reason, the problem that the surface of the silicon layer of the semiconductor substrate 100 is lowered (digged) by thermal oxidation does not occur. Further, there is no problem that impurities injected into the N-type extension diffusion layer 260 and the P-type extension diffusion layer 270 are reduced.

  Further, in the second embodiment, the N-type extension diffusion layer 260 is formed in the NMIS region 120 and the second N-type impurity 240 is implanted into both sides of the NMIS gate electrode 220 at the same time. After forming the P-type extension diffusion layer 270 and simultaneously injecting the second P-type impurity 250 into both sides of the PMIS gate electrode 230, oxidation for forming the offset sidewall oxide film 320 is performed. For this reason, the second P-type impurity 250 having a larger oxidation coefficient than the thickness of the oxide film on the side of the NMIS gate electrode 220 into which the second N-type impurity 240 has been implanted into the side is implanted into the side. The thickness of the oxide film formed on the side portion of the PMIS gate electrode 230 is about 1.1 times thicker.

  On the other hand, the second N-type impurity 240 injected into the N-type extension diffusion layer 260 formed in the semiconductor substrate 100 made of silicon is injected into the P-type extension diffusion layer 270 formed in the semiconductor substrate 100. The second P-type impurity 250 has a diffusion length about 1.2 times larger when activated by annealing. Therefore, the NMIS gate electrode 220 and the N-type extension diffusion layer 260 overlap with the gate insulating film 160 interposed therebetween, and the PMIS gate electrode 230 and the P-type extension diffusion layer 270 overlap with the gate insulating film 160 interposed therebetween. The region is formed in a self-aligned manner.

  Therefore, a complementary MIS field effect transistor excellent in short channel characteristics and driving capability can be realized.

  The offset sidewall oxide film 320 formed on the side portions of the gate electrodes 220 and 230 may be formed by an inductively coupled plasma oxidation method formed at room temperature.

(One Modification of Second Embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to a modification of the second embodiment will be described with reference to the drawings.

  9 (a) to 9 (c), 10 (a) to 10 (c), 11 (a), and 11 (b) relate to a modification of the second embodiment of the present invention. The cross-sectional structure of the order of the process of the manufacturing method of a complementary (complementary type) MIS field effect transistor is shown.

  In this modified example, the process up to patterning the NMIS gate electrode and the PMIS gate electrode in the complementary MIS field effect transistor is the same as that in the second embodiment, and thus the description thereof is omitted. This will be explained later.

  9A, the semiconductor substrate 100 made of silicon is partitioned into an NMIS region 120 and a PMIS region 130 by the element isolation layer 110, and a P-type well is formed above the NMIS region 120 in the semiconductor substrate 100. A diffusion layer 150 is formed, and an N-type well diffusion layer 140 is formed above the PMIS region 130. On the main surface of the semiconductor substrate 100 on which the P-type well diffusion layer 150 and the N-type well diffusion layer 140 are formed, a gate insulating film 160 having a film thickness of about 10 nm and a high dielectric constant is formed. An NMIS gate electrode 220 having a gate length of about 60 nm is formed in the NMIS region 120 of the gate insulating film 160, and a PMIS gate electrode 230 having a gate length of about 60 nm is formed in the PMIS region 130.

Next, as shown in FIG. 9B, a first resist pattern 330 that covers the PMIS region 130 including the PMIS gate electrode 230 is formed by lithography. Subsequently, using the formed first resist pattern 330 and NMIS gate electrode 220 as a mask, the second N-type impurity 240 made of, for example, phosphorus, arsenic, or antimony is accelerated by 3 keV through the gate insulating film 160. Implantation is performed at a dose of about 1 × 10 ¹⁵ / cm ^{2 with} energy. As a result, an N-type extension diffusion layer 260 in which the second N-type impurity is implanted is formed on the P-type well diffusion layer 150. At this time, the second N-type impurity is also implanted into both sides of the NMIS gate electrode 220.

Next, as shown in FIG. 9C, again using the first resist pattern 330 and the NMIS gate electrode 220 as a mask and through the gate insulating film 160, for example, boron, boron fluoride, indium, or cluster ions ( By implanting a third P-type impurity 290 made of B ₁₀ H ₁₄ , B ₁₈ H ₂₂ ) or the like with an acceleration energy of 10 keV and a dose of about 1 × 10 ¹³ / cm ² , the P-type well diffusion layer 150 A P-type pocket diffusion layer 310 is formed below the N-type extension diffusion layer 260 in FIG. Thereafter, the first resist pattern 330 is removed by ashing or cleaning.

Next, as shown in FIG. 10A, the NMIS gate electrode 220 and the PMIS gate electrode 230 are subjected to thermal oxidation for about 10 minutes in an ozone (O ₃ ) atmosphere at a temperature of about 400 ° C. An offset sidewall oxide film 320 having a thickness of 6 nm is formed on each upper part and both sides of the gate electrode 220 and the PMIS gate electrode 230. The offset sidewall oxide film 320 is formed to be thinner than the gate insulating film 160. The offset sidewall oxide film 320 causes the NMIS gate electrode 220 and the N-type extension diffusion layer 260 and the PMIS gate electrode 230 and the P-type extension diffusion layer 270 to overlap with each other via the gate insulating film 160 (overlap region). The width of is controlled.

Next, as shown in FIG. 10B, a second resist pattern 331 covering the NMIS region 120 including the NMIS gate electrode 220 is formed by lithography. Subsequently, using the formed second resist pattern 331, PMIS gate electrode 230 and offset sidewall oxide film 320 as a mask, and via the gate insulating film 160 and offset sidewall oxide film 320, for example, boron, boron fluoride, A second P-type impurity 250 made of indium or cluster ions (B ₁₀ H ₁₄ , B ₁₈ H ₂₂ ) or the like is implanted with an acceleration energy of about 1 keV and a dose of about 1 × 10 ¹⁵ / cm ² . As a result, the P-type extension diffusion layer 270 in which the third P-type impurity is implanted is formed on the N-type well diffusion layer 140.

Next, as shown in FIG. 10C, again using the second resist pattern 331, the PMIS gate electrode 230 and the offset sidewall oxide film 320 as a mask, the gate insulating film 160 and the offset sidewall oxide film 320 are formed. Then, a third N-type impurity 280 made of, for example, phosphorus, arsenic, antimony, or the like is implanted at an acceleration energy of 30 keV and a dose of about 1 × 10 ¹³ / cm ² . An N-type pocket diffusion layer 300 is formed below the P-type extension diffusion layer 270. Thereafter, the second resist pattern 331 is removed by ashing or cleaning.

  Next, the film thickness is increased over the entire surface including the NMIS gate electrode 220, the PMIS gate electrode 230, and each offset sidewall oxide film 320 on the semiconductor substrate 100 by low pressure chemical vapor deposition or atmospheric pressure chemical vapor deposition. A silicon oxide film having a thickness of about 10 nm and a silicon nitride film having a thickness of about 50 nm are deposited. Thereafter, the deposited silicon nitride film and silicon oxide film are etched back over the entire surface, thereby forming an NMIS gate on both side surfaces of the NMIS gate electrode 220 and in the gate insulating film 160 as shown in FIG. Silicon oxide with offset sidewall oxide films 320 interposed on both side portions of the electrode 220 and on both side surfaces of the PMIS gate electrode 230 and on both side portions of the PMIS gate electrode 230 in the gate insulating film 160, respectively. A sidewall 340 made of a laminated film of a film and a silicon nitride film is formed.

Thereafter, an N-type source drain (S / D) diffusion layer 370 is formed in the NMIS region 120 of the semiconductor substrate 100, and then a P-type source drain (S / D) diffusion layer 380 is formed in the PMIS region 130. Specifically, the PMIS region 130 is covered with a resist film (not shown), and the NMIS gate electrode 220, the offset sidewall oxide film 320, and the sidewall 340 are used as a mask for the semiconductor substrate 100, such as phosphorus, arsenic, or antimony. A fourth N-type impurity is implanted at an acceleration energy of 30 keV and a dose of about 2 × 10 ¹⁵ / cm ² . As a result, the N-type source drain (S / S) is formed on both sides of the NMIS gate electrode 220 in the P-type well diffusion layer 150 of the NMIS region 120 and outside the N-type extension diffusion layer 260 and the P-type pocket diffusion layer 310. D) A diffusion layer 370 is formed. Subsequently, after removing the resist film covering the PMIS region 130, the NMIS region 120 is covered with a resist film (not shown), and the PMIS gate electrode 230, the offset sidewall oxide film 320, and the sidewall 340 are used as a mask. A fourth P-type impurity made of, for example, boron, boron fluoride, indium, or cluster ions (B ₁₀ H ₁₄ , B ₁₈ H ₂₂ ) or the like is added to the substrate 100 at an acceleration energy of 2 keV and about 2 × 10 ¹⁵ / cm ^2. Inject at a dose of. As a result, the P-type source drain (S / S) is formed on both sides of the PMIS gate electrode 230 in the N-type well diffusion layer 140 of the PMIS region 130 and outside the P-type extension diffusion layer 270 and the N-type pocket diffusion layer 300. D) A diffusion layer 380 is formed. The formation order of the N-type S / D diffusion layer 370 and the P-type S / D diffusion layer 380 is not particularly limited.

  Subsequently, the N-type extension diffusion layer 260, the P-type pocket diffusion layer 310, and the N-type S / D diffusion layer 370 are respectively formed in the NMIS region 120 by performing a rapid high-temperature heat treatment at a temperature of 1050 ° C. for about 20 seconds. In addition, the P-type extension diffusion layer 270, the N-type pocket diffusion layer 300, and the P-type S / D diffusion layer 380 are activated in the PMIS region 130, respectively.

  By this step, a region where the NMIS gate electrode 220 and the N-type extension diffusion layer 260 overlap with the gate insulating film 160 interposed therebetween (overlap region), and the PMIS gate electrode 230 and the P-type extension diffusion layer 270 form the gate insulating film. An overlapping area (overlap area) is determined with 160 interposed.

  Thereafter, cobalt silicide or nickel is formed on the upper portion of the NMIS gate electrode 220 and the upper portion of the N-type S / D diffusion layer 370, the upper portion of the PMIS gate electrode 230, and the upper portion of the P-type S / D diffusion layer 380 by a known technique. A silicide layer 390 such as silicide is formed to reduce the resistance of the NMIS gate electrode 220 and the N-type S / D diffusion layer 370, as well as the PMIS gate electrode 230 and the P-type S / D diffusion layer 380.

  Next, as shown in FIG. 11B, the silicided N-type S / D diffusion layer 370 and the P-type S / D diffusion layer 380, the silicided NMIS gate electrode 220, and the PMIS are formed by a known technique. An interlayer buffer layer 400 made of silicon oxide and an interlayer insulating film 410 are deposited so as to cover the gate electrode 230. Subsequently, after planarizing the upper surface of the deposited interlayer insulating film 410, one of the N-type S / D diffusion layer 370 and one of the P-type S / D diffusion layer 380 is formed on the interlayer insulating film 410 and the interlayer film buffer layer 400. A contact hole is formed to expose each of. Thereafter, a contact barrier metal 420 is formed along the bottom and wall surfaces of each formed contact hole, and a contact plug 430 is filled on each contact barrier metal 420. Subsequently, a metal wiring 440 is selectively formed on the interlayer insulating film 410 so as to be connected to each contact plug 430, thereby obtaining a complementary semiconductor device according to this modification.

  In the above-described prior art, after the gate electrode 22 is oxidized to form the offset sidewall oxide film 32, the impurity implantation for forming the extension diffusion layer 26 is performed. As shown in FIG. 12D, the width of the overlapping region (overlap region) is a value obtained by subtracting the film thickness of the offset sidewall oxide film 32 from the diffusion length Δd of the extension diffusion layer 26, that is, [Expression 1]

  On the other hand, in this modification, after the impurity implantation for forming the N-type extension diffusion layer 260 is performed, the oxidation for forming the offset sidewall oxide film 320 is performed. This is a value obtained by subtracting the film loss due to the oxidation of the side portion of the NMIS gate electrode 220 from the diffusion length Δd of the N-type extension diffusion layer 260 shown in FIG.

  The variation in the thickness of the offset sidewall oxide film in the overlap region of the prior art shown in [Equation 1] is opposite to the gate electrode in the gate length direction in addition to the variation caused by the film thickness reduction due to oxidation at the side of the gate electrode. It also includes variations caused by oxidation growth on both side surfaces.

  Therefore, in contrast to the variation in the width of the overlap region of the prior art, in this modification, the variation caused by the oxidation growth of both side surfaces of the gate electrode facing the gate length direction is not included. Variation in width can be reduced.

  In addition, in this modification, the thickness of the gate insulating film 160 that prevents the semiconductor substrate 100 from being oxidized is thicker than the thickness of the offset sidewall oxide film 320, so that the offset sidewall oxide film 320 is formed. In the thermal oxidation step, the surface of the semiconductor substrate 100 on which the N-type extension diffusion layer 260 and the P-type extension diffusion layer 270 are formed is hardly oxidized. For this reason, the problem that the surface of the silicon layer of the semiconductor substrate 100 is lowered (digged) by thermal oxidation does not occur. Further, there is no problem that the concentration of the impurity implanted into the N-type extension diffusion layer 260 and the P-type extension diffusion layer 270 is lowered.

  Further, in the present modification, after forming the N-type extension diffusion layer 260 in the NMIS region 120 and simultaneously injecting the second N-type impurity 240 into both sides of the NMIS gate electrode 220, each gate electrode 220, 230 is oxidized to form the offset sidewall oxide film 320, and then a P-type extension diffusion layer 270 is formed in the PMIS region 130. For this reason, the film thickness of the oxide film formed on the side of the NMIS gate electrode 220 into which the second N-type impurity 240 is implanted on the side is the side of the PMIS gate electrode 230 on which no impurity is implanted on the side. This is almost the same as the thickness of the oxide film formed on the portion.

  In the configuration according to this modification, in the annealing process for activating each implanted impurity, the second N-type impurity 240 implanted into the N-type extension diffusion layer 260 in the NMIS region 120 is converted into the gate insulating film 160. In order to have a region overlapping with the NMIS gate electrode 220 across the n-type electrode, the N-type impurity 240 has a distance of about half the thickness of the offset sidewall oxide film 320 formed by oxidizing at least the side portion of the NMIS gate electrode 220. Need to spread.

  On the other hand, at least the PMIS gate electrode 230 has a region where the second P-type impurity 250 implanted into the P-type extension diffusion layer 270 in the PMIS region 130 overlaps the PMIS gate electrode 230 with the gate insulating film 160 interposed therebetween. It is necessary to thermally diffuse a distance corresponding to the thickness of the offset sidewall oxide film 320 formed by oxidizing the side portion of the first sidewall.

  The second P-type impurity 250 of the P-type extension diffusion layer 270 formed on the semiconductor substrate 100 is different from the second N-type impurity 240 of the N-type extension diffusion layer 260 formed on the semiconductor substrate 100 made of silicon. When activated by annealing, the diffusion length is about 1.2 times larger. Therefore, a region where the NMIS gate electrode 220 and the N-type extension diffusion layer 260 overlap with the gate insulating film 160 interposed therebetween, and a region where the PMIS gate electrode 230 and the P-type extension diffusion layer 270 overlap with the gate insulating film 160 interposed therebetween. Are formed in a self-aligning manner.

  Therefore, a complementary MIS field effect transistor excellent in short channel characteristics and driving capability can be realized.

  The offset sidewall oxide film 320 formed on the side portions of the gate electrodes 220 and 230 may be formed by an inductively coupled plasma oxidation method formed at room temperature.

  INDUSTRIAL APPLICABILITY The semiconductor device and the manufacturing method thereof according to the present invention can realize an MIS type semiconductor device having excellent short channel characteristics and excellent driving capability, and is particularly useful for a semiconductor device composed of an MIS type field effect transistor having an extension diffusion layer. is there.

It is sectional drawing which shows the principal part of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(d) is sectional drawing of the process order of the principal part which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(d) is sectional drawing of the process order of the principal part which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(d) is sectional drawing of the process order of the principal part which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(c) is sectional drawing of the process order of the principal part which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing of the process order of the principal part which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing of the process order of the principal part which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing of the process order of the principal part which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing of the process order of the principal part which shows the manufacturing method of the semiconductor device which concerns on the modification of the 2nd Embodiment of this invention. (A)-(c) is sectional drawing of the process order of the principal part which shows the manufacturing method of the semiconductor device which concerns on the modification of the 2nd Embodiment of this invention. (A) And (b) is sectional drawing of the order of the process of the principal part which shows the manufacturing method of the semiconductor device which concerns on the modification of the 2nd Embodiment of this invention. (A)-(d) is sectional drawing of the order of the process of the principal part which shows the manufacturing method of the conventional semiconductor device.

Explanation of symbols

100 Semiconductor substrate 110 Element isolation layer 120 NMIS region 130 PMIS region 140 N-type well diffusion layer 150 P-type well diffusion layer 160 Gate insulating film 170A Non-doped polysilicon film 170B Polysilicon film 170C Polysilicon film 200 First N-type impurity 210 First P-type impurity 220 (NMIS) gate electrode 230 PMIS gate electrode 240 Second N-type impurity 250 Second P-type impurity 260 N-type extension diffusion layer 270 P-type extension diffusion layer 280 Third N-type impurity 290 (Third) P-type impurity 300 N-type pocket diffusion layer 310 P-type pocket diffusion layer 320 Offset sidewall oxide film (first gate electrode sidewall insulating film)
330 (first) resist pattern 331 second resist pattern 332 third resist pattern 333 fourth resist pattern 334 fifth resist pattern 340 sidewall (second gate electrode sidewall insulating film)
370 N-type source drain (S / D) diffusion layer 380 P-type source drain (S / D) diffusion layer 390 Silicide layer 400 Interlayer film buffer layer 410 Interlayer insulating film 420 Barrier metal 430 Contact plug 440 Metal wiring

Claims (5)

A gate insulating film formed on the semiconductor region and having a dielectric constant higher than that of silicon oxide;
A gate electrode formed on the gate insulating film and made of polysilicon;
A first gate electrode sidewall insulating film formed on a side surface of the gate electrode and having a thickness smaller than that of the gate insulating film;
A second gate electrode sidewall insulating film formed on the side surface of the gate electrode with the first gate electrode sidewall insulating film interposed therebetween, and having a thickness greater than that of the gate insulating film;
An impurity diffusion layer formed below the side edge of the gate electrode in the semiconductor region and below the first gate electrode sidewall insulating film and the second gate electrode sidewall insulating film;
A semiconductor device, wherein an upper surface of the impurity diffusion layer in the semiconductor region is flat. An NMIS field effect transistor and a PMIS field effect transistor formed in a semiconductor region;
The NMIS field effect transistor is
A P-type well diffusion layer formed on the semiconductor region;
A gate insulating film formed on the semiconductor region and having a dielectric constant higher than that of silicon oxide;
An NMIS gate electrode formed of polysilicon and formed on the P-type well diffusion layer with the gate insulating film interposed therebetween;
A first NMIS gate electrode sidewall insulating film formed on a side surface of the NMIS gate electrode and having a thickness smaller than that of the gate insulating film;
A second NMIS gate electrode side wall insulating film formed on the side surface of the NMIS gate electrode with the first NMIS gate electrode side wall insulating film interposed therebetween and thicker than the gate insulating film;
N-type impurity diffusion formed below the side end portion of the NMIS gate electrode in the P-type well diffusion layer and below the first NMIS gate electrode sidewall insulating film and the second NMIS gate electrode sidewall insulating film. And having a layer
The PMIS type field effect transistor is:
An N-type well diffusion layer formed on the semiconductor region by being separated from the P-type well diffusion layer by an element isolation layer;
The gate insulating film formed on the semiconductor region;
A PMIS gate electrode formed of polysilicon and formed on the N-type well diffusion layer with the gate insulating film interposed therebetween;
A first PMIS gate electrode sidewall insulating film formed on a side surface of the PMIS gate electrode and having a thickness smaller than that of the gate insulating film;
A second PMIS gate electrode sidewall insulating film formed on the side surface of the PMIS gate electrode with the first PMIS gate electrode sidewall insulating film interposed therebetween, and having a thickness greater than that of the gate insulating film;
P-type impurity diffusion formed below the side edge of the PMIS gate electrode in the N-type well diffusion layer and below the first PMIS gate electrode side wall insulating film and the second PMIS gate electrode side wall insulating film. And having a layer
The semiconductor device according to claim 1, wherein an upper surface of the N-type impurity diffusion layer in the P-type well diffusion layer and an upper surface of the P-type impurity diffusion layer in the N-type well diffusion layer are flat. Forming a gate insulating film having a dielectric constant higher than that of silicon oxide on the semiconductor region;
Forming a gate electrode forming film made of polysilicon on the gate insulating film;
Forming a gate electrode made of polysilicon by patterning the gate electrode formation film, and leaving the gate insulating film on both sides of the gate electrode in the semiconductor region;
Forming an impurity diffusion layer in the semiconductor region by implanting impurity ions through the gate insulating film using the gate electrode as a mask in the semiconductor region;
Forming a gate electrode sidewall insulating film having a thickness smaller than that of the gate insulating film on the side surface of the gate electrode by an oxidation method after forming the impurity diffusion layer. Device manufacturing method. Forming a P-type well diffusion layer and an N-type diffusion layer separated by an element isolation layer in a semiconductor region (a);
Forming a gate insulating film having a dielectric constant higher than that of silicon oxide on the P-type well diffusion layer and the N-type diffusion layer;
Forming a gate electrode formation film made of polysilicon on the gate insulating film;
By patterning the gate electrode formation film, an NMIS gate electrode made of polysilicon is formed on the P-type well diffusion layer, and a PMIS gate electrode made of polysilicon is formed on the N-type well diffusion layer. And (d) leaving the gate insulating film on both sides of the NMIS gate electrode and the PMIS gate electrode in the semiconductor region,
After the step (d), N-type impurity ions are implanted into the P-type well diffusion layer by using the NMIS gate electrode as a mask and implanting the P-type well diffusion layer through the gate insulating film. (E) forming an impurity diffusion layer and implanting the N-type impurity ions into at least a side portion of the NMIS gate electrode;
After the step (d), P-type impurity ions are implanted into the N-type well diffusion layer by using the PMIS gate electrode as a mask and through the gate insulating film. (F) forming an impurity diffusion layer and implanting the P-type impurity ions into at least a side portion of the PMIS gate electrode;
After step (e) and step (f), a gate electrode sidewall insulating film having a thickness smaller than that of the gate insulating film is formed on each side surface of the NMIS gate electrode and the PMIS gate electrode by an oxidation method. And a step (g) of manufacturing a semiconductor device. Forming a P-type well diffusion layer and an N-type diffusion layer separated by an element isolation layer in a semiconductor region (a);
Forming a gate insulating film having a dielectric constant higher than that of silicon oxide on the P-type well diffusion layer and the N-type diffusion layer;
Forming a gate electrode formation film made of polysilicon on the gate insulating film;
By patterning the gate electrode formation film, an NMIS gate electrode made of polysilicon is formed on the P-type well diffusion layer, and a PMIS gate electrode made of polysilicon is formed on the N-type well diffusion layer. And (d) leaving the gate insulating film on both sides of the NMIS gate electrode and the PMIS gate electrode in the semiconductor region,
After the step (d), N-type impurity ions are implanted into the P-type well diffusion layer by using the NMIS gate electrode as a mask and implanting the P-type well diffusion layer through the gate insulating film. (E) forming an impurity diffusion layer and implanting the N-type impurity ions into at least a side portion of the NMIS gate electrode;
After the step (e), a step (f) of forming a gate electrode sidewall insulating film having a thickness smaller than that of the gate insulating film on each side surface of the NMIS gate electrode and the PMIS gate electrode by an oxidation method. When,
After the step (f), P-type impurity ions are implanted into the N-type well diffusion layer using the PMIS gate electrode as a mask and through the gate insulating film, so that the N-type well diffusion layer is P-type. And a step (g) of forming an impurity diffusion layer.

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