JP4078721B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a field effect transistor structure using a vertical channel and a method for manufacturing the same.
[0002]
[Prior art]
Usually, the field effect transistor has a channel formed along the surface direction of the semiconductor substrate. In this configuration, the occupied area cannot be sufficiently reduced, and sufficient density cannot be increased in the integrated circuit. Also, when increasing the density, it becomes difficult to secure a sufficiently large channel width, and it becomes difficult to sufficiently increase the cutoff frequency.
[0003]
[Problems to be solved by the invention]
The present invention has a vertical channel configuration, can obtain a channel width of up to 100 nm, can improve the cutoff frequency as compared with a transistor having a conventional planar channel configuration, and is uniform with good reproducibility. It is an object of the present invention to provide a semiconductor device capable of mass-producing a semiconductor device having characteristics and a manufacturing method thereof.
[0004]
[Means for Solving the Problems]
The semiconductor device according to the present invention has a structure in which a columnar semiconductor is formed on a semiconductor, and a gate insulating layer is formed on the entire peripheral surface of the columnar semiconductor.
A gate conductive layer is formed on the outer peripheral surface of the gate insulating layer.
In addition, an insulating layer is formed on the outer periphery of the columnar semiconductor and the gate conductive layer. However, the upper ends of the columnar semiconductor and the gate conductive layer are exposed on the upper surface of the insulating layer.
Further, a gate electrode extraction conductive layer connected to the gate conductive layer is formed on the insulating layer, and the gate electrode extraction conductive layer is embedded and formed on the outer periphery of the above-described columnar semiconductor and the outer periphery of the gate conductive layer. A surface insulating layer is formed on the buried insulating layer.
[0005]
First and second contact holes communicating with the surface insulating layer on the gate electrode extraction conductive layer and the columnar semiconductor are opened, respectively, and the surface insulating layer and the buried insulating layer are formed outside the columnar semiconductor forming portion. A third contact hole is opened on the semiconductor.
Then, the gate electrode is brought into contact with the gate electrode take-out conductive layer through the first contact hole, and the source or the upper side of the columnar semiconductor and the semiconductor outside the columnar semiconductor formation portion through the second and third contact holes. The drain electrode is in contact.
[0006]
The method for manufacturing a semiconductor device according to the present invention includes a step of forming a columnar semiconductor on the semiconductor, a step of oxidizing the periphery of the columnar semiconductor to form a gate insulating layer, and a gate conductive layer on the outer periphery of the gate insulating layer. Forming a buried insulating layer in which the columnar semiconductor and the gate conductive layer are embedded, and the upper ends of the columnar semiconductor and the gate conductive layer are exposed to the surface, and the gate conductive layer is formed on the buried insulating layer. A step of forming a gate electrode extraction conductive layer to be connected; a step of embedding the gate electrode extraction conductive layer to form a surface insulating layer on the embedded insulating layer; and a step of extracting the gate electrode on the columnar semiconductor of the surface insulating layer First and second contact holes are opened on the conductive layer, and a third contact hole is opened on the semiconductor outside the columnar semiconductor formation across the surface insulating layer and the buried insulating layer. A gate electrode through the first contact hole to contact the gate electrode and the conductive layer, and through the second and third contact holes, the upper end of the columnar semiconductor and the semiconductor outside the columnar semiconductor formation portion to the source electrode or A target semiconductor device is formed through a process of contacting the drain electrode.
[0007]
That is, in the configuration of the present invention described above, a columnar semiconductor is formed on a semiconductor, and the semiconductor and the upper end of the columnar semiconductor are used as one of the source and drain regions and the other, and a gate is formed on the peripheral surface of the columnar semiconductor. By forming the insulating layer and the gate conductive layer, a vertical channel is formed, and the channel width becomes the peripheral length of the columnar semiconductor, so that the channel width can be increased.
[0008]
In the manufacturing method of the present invention, a method of forming a columnar semiconductor on a semiconductor is employed in the manufacturing. Since this method uses a manufacturing method of a columnar semiconductor that is uniform and excellent in reproducibility, it is designed uniformly. The same semiconductor device can be manufactured.
[0009]
The order in which the first to third contact holes are opened and the order in which the electrodes are formed are not limited, and the contact holes can be simultaneously opened or the electrodes can be simultaneously formed.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of a semiconductor device and a manufacturing method thereof according to the present invention will be described. Prior to this, a method for manufacturing a columnar semiconductor in the manufacturing method of the present invention will be described.
In manufacturing the columnar semiconductor, a VLS (Vapor Liquid Solid) method is used. This VLS method can be based on the method proposed by the applicant of the present application, Japanese Patent Application No. 8-325555, Japanese Patent Application No. 9-256045, and the like.
[0011]
FIG. 5 is a process chart showing an example of a method for forming the columnar semiconductor 2 on the substrate 1.
The substrate 1 is, for example, a Si semiconductor substrate having a specific resistance ρ = 0.4 Ω · cm and having one principal surface 1a of {111} crystal plane. One main surface 1a of the substrate 1 is polished, further washed with, for example, acetone, and etched with a mixed solution of nitric acid and hydrofluoric acid to remove the surface oxide film. In this way, the pretreatment for the substrate 1 is performed.
[0012]
As shown in FIG. 5A, in order to form a molten alloy droplet with Si, which will be described later, on the main surface 1a of the substrate 1, a metal such as Au serving as a catalyst for the growth of a columnar semiconductor is deposited to have a diameter of about 0.6 nm. A metal layer 5 made of these particles is deposited.
Thereafter, under heating at a substrate temperature of 300 ° C. to 900 ° C., for example, 520 ° C., one or more of Si source gas, particularly silane (Si _n H _{2n + 2} ), for example, monosilane, disilane, and trisilane is supplied. Perform pyrolysis of gas. In this case, the supply of the Si source gas is set to a partial pressure of 0.5 mTorr or more, for example, 10 mTorr. As a result, molten alloy droplets 3 are formed as shown in FIG. 5B.
Subsequently, as shown in FIG. 5C, when the above-described raw material gas is continuously supplied in a state where the substrate 1 is heated, silane decomposition is caused by the catalytic action of the molten alloy droplet 3 by Au. Here, the columnar semiconductor 2 made of Si grows. The columnar semiconductor 2 is formed such that its axial direction is the <111> direction.
[0013]
The columnar semiconductor 2 is grown to a length (height) of about 1 μm at a growth rate of 1 hour, for example. The diameter can be formed in the range of 10 nm to 100 nm.
[0014]
In the example described with reference to FIG. 5, the metal layer 5 that forms the molten alloy droplet 3 is deposited on the entire surface of the substrate 1. In this case, the generated molten alloy droplet 3, and thus the columnar semiconductor 2. However, it is not necessarily formed at the target position. In order to avoid such an inconvenience, it is possible to restrict the formation position of the metal layer 5 and to form the molten alloy droplet 3 and thus the columnar semiconductor 2 at the target position. An example of this case will be described with reference to FIG.
[0015]
In this case, as shown in FIG. 6A, for example, a position regulating film 31 is formed on the same substrate 1 as described in FIG. The position restricting film 31 is formed, for example, by forming a SiO ₂ film with a thickness of about 100 nm, and performing pattern etching by photolithography, for example, and finally forming a through hole 31a in a portion where the columnar semiconductor 2 is formed. A limited part of the surface of the substrate 1 is exposed to the outside through the through hole 31a. The through holes are, for example, 1 μm to 0.8 μm in diameter.
[0016]
After the formation of the through-holes 31a in the position regulating film 31, the substrate 1 is washed and dried, and the surface is cleaned by heating to 700 ° C. in vacuum, for example, and a metal such as Au serving as a catalyst for the growth of the columnar semiconductor is used. For example, a metal layer 5 having a thickness of 0.6 nm is formed by vapor deposition. At this time, the Au metal layer 5 is not formed on the position restricting film 31 made of SiO ₂ , but the metal layer 5 is selectively formed only on the surface of the substrate 1, that is, the portion where the semiconductor is exposed through the through hole 31 a. .
[0017]
Next, the above-described Si source gas, for example, SiH ₄ is supplied, and heat treatment is performed at, for example, 700 ° C. for 30 minutes. In this way, as shown in FIG. 11B, Si and Au molten alloy droplets 3 are formed in the through holes 31 a of the position regulating film 31. In this way, the formation position of the molten alloy droplet 3 can be defined. Therefore, if the columnar semiconductor 2 is grown thereafter, the formation position of the columnar semiconductor 2 is also defined at this position.
The position restricting film 31 can be removed by etching in an appropriate process.
[0018]
An example of the semiconductor device according to the present invention will be described together with an example of the manufacturing method of the present invention with reference to FIGS. However, the present invention is not limited to this example.
As shown in FIG. 1A, a substrate 1 is prepared. The substrate 1 is made of a semiconductor whose one principal surface 1a is a {111} crystal plane. In the example of FIG. 1, oxygen ions are implanted from one surface of a {111} Si substrate, an insulating layer 11 made of SiO ₂ is formed to a required depth, and a semiconductor layer 12 is left on its main surface 1a. It can be constituted by a substrate having a so-called SIMOX (Separation by Implanted Oxygen) structure.
[0019]
As shown in FIG. 1B, pattern etching by photolithography, for example, is performed on the semiconductor layer 12 to leave a portion constituting a target semiconductor element and etch away an isolation region from other elements.
[0020]
After that, the above-described pretreatment is performed on the main surface 1a of the surface of the semiconductor layer 12, and the columnar semiconductor 2 is formed on the semiconductor layer 12 as shown in FIG. 1C by the method shown in FIGS. .
[0021]
The molten alloy droplet 3 remains at the tip of the columnar semiconductor 2 and is removed with a mixed solution of hydrochloric acid and nitric acid. Thereafter, an oxidation treatment is performed to form an insulating layer 13 of SiO _{2 on} the entire surface of the semiconductor layer 12 and the columnar semiconductor 2 as shown in FIG. 1D. In this case, the oxidation treatment conditions are selected so that the insulating layer 13 formed on the peripheral surface of the columnar semiconductor 2 has a thickness that functions as the gate insulating layer 13g.
[0022]
As shown in FIG. 2A, a gate conductive layer 14 is formed around the columnar semiconductor 2. The gate conductive layer 14 is formed on the entire surface of the substrate 1 by, for example, forming a polycrystalline Si semiconductor layer by, for example, a CVD (Chemical Vapor Deposition) method and etching back to form a so-called side surface around the columnar semiconductor 2. Form a wall.
That is, for example, when a polycrystalline Si film is formed by the CVD method, the deposition of the polycrystalline Si by the CVD method is made almost isotropic. Therefore, the polycrystalline Si film formed on the side surface of the columnar semiconductor 2 is also Although the thickness is almost the same as that of the other portion, the apparent thickness in the direction along the axial direction of the columnar semiconductor 2 is sufficiently larger than, for example, the thickness of the top surface of the columnar semiconductor 2 or the flat surface of the semiconductor layer 12. It becomes. Therefore, when this polycrystalline Si is etched back along the surface direction of the substrate 1 (the axial direction of the columnar semiconductor 2), it is formed on the peripheral surface of the columnar semiconductor 2 having a large apparent thickness. Only polycrystalline Si can be left as a sidewall. The polycrystalline Si can be given conductivity by doping impurities during the deposition, and in addition to or without this doping, the polycrystalline Si can be doped by impurities by ion implantation in the next step. The polycrystalline Si is provided with conductivity to form the gate conductive layer 14.
[0023]
Next, as shown in FIG. 2B, impurities, for example, n-type impurities, are ion-implanted to form polycrystalline Si constituting the gate conductive layer 14, the top of the columnar semiconductor 2, and the columnar semiconductor 2 of the semiconductor layer 12. Further, impurities are doped into the outer peripheral portion of the gate conductive layer 14 formation portion. In this way, source or drain regions (hereinafter referred to as S / D regions) 15 and 16, one of which serves as a source region and the other serves as a drain region, are formed on the top of the columnar semiconductor 2 and the outer periphery of the semiconductor layer 12. Form.
[0024]
Thereafter, as shown in FIG. 2C, a buried insulating layer 17 such as SiO ₂ is formed by a CVD method or the like so as to bury the columnar semiconductor 2 and the gate conductive layer 14 on the outer periphery thereof.
[0025]
As shown in FIG. 2D, the buried insulating layer 17 is polished flatly from the surface to a position where the S / D region 15 at the top of the columnar semiconductor 2 is exposed by chemical mechanical polishing, so-called CMP (Chemical Mechanical Polishing). To do.
[0026]
Further, as shown in FIG. 3A, the flat polished surface by the CMP is etched back to expose a part of the upper end of the gate conductive layer 14 to the outside.
[0027]
As shown in FIG. 3B, a conductive layer 18 made of polycrystalline Si doped with impurities, for example, is entirely formed on the buried insulating layer 17 by a CVD method.
[0028]
As shown in FIG. 3C, the conductive layer 18 is further polished to the required thickness by CMP to planarize the surface.
[0029]
Thereafter, as shown in FIG. 3D, the conductive layer 18 is subjected to pattern etching by, for example, photolithography, into a required pattern in contact with the gate conductive layer 14 to form a gate electrode extraction conductive layer.
[0030]
Further, if necessary, that is, even if the polycrystalline Si of the conductive layer 18 is not doped with impurities or is doped with impurities, the specific resistance is further reduced to achieve the same as the regions 15 and 16. Conduction type impurity ion implantation is performed to reduce the specific resistance of the conductive layer 18.
[0031]
As shown in FIG. 4B, for example, SiO ₂ is formed on the entire surface by thermal oxidation or CVD to form a surface insulating layer 19.
[0032]
As shown in FIG. 4C, the first and the first insulating layers 19 are connected in a limited manner on the gate electrode extraction conductive layer 18 and on the S / D region 15 at the upper end (top) of the columnar semiconductor 2. Second contact holes 21 and 22 are opened, and a third contact hole 23 communicating with the S / D region 16 is opened in the surface insulating layer 19 and the buried insulating layer 17 therebelow.
Then, through the contact hole 21 and the contact holes 22 and 23, on the gate electrode extraction conductive layer 18 and the S / D regions 15 and 16, respectively, a gate electrode 24 made of, for example, a metal electrode, a source or drain electrode 25, and 26 is in ohmic contact.
In this way, the upper and base sides of the columnar semiconductor 2 are the source or drain regions, respectively, and the gate conductive layer 14 is formed on the peripheral surface of the columnar semiconductor 2 along the axial direction via the gate insulating layer 13g. A semiconductor device in which a target semiconductor element in which a vertical channel is formed is formed on the substrate 1 is configured.
[0033]
Although the semiconductor device thus configured has a vertical channel configuration, a channel is formed on the peripheral surface of the columnar semiconductor 2 even though the area occupied by the substrate 1 can be reduced. Therefore, a wide channel width that reaches 100 nm can be obtained.
Therefore, the cutoff frequency can be improved as compared with a transistor having a conventional planar channel configuration.
[0034]
In the manufacture of the columnar semiconductor 2 described above, by using silane as the Si source gas, the columnar semiconductor is sufficiently thin at a sufficiently low temperature as compared with the case of using a chemically stable silicon chloride gas as in the past. A semiconductor can be constituted.
[0035]
1 to 4 show a state in which one semiconductor element is formed on the substrate 1, a plurality of similarly vertical channel field effect elements are formed on the common substrate 1 at the same time. Then, each element can be divided, or a plurality of similar elements can be formed, or a semiconductor integrated circuit in which other semiconductor elements are formed on the common substrate 1 can be configured. it can.
[0036]
Further, as a method for forming the columnar semiconductor 2, the apparatus of the present invention and the method of the present invention are not limited to the above-described examples. For example, the method described with reference to FIG.
[0037]
In the above-described example, in the formation of the molten alloy droplet 3, the molten alloy droplet is formed while supplying the Si raw material gas. However, when the columnar semiconductor is formed on the Si semiconductor substrate, this Si semiconductor is used. A method of supplying Si source gas after forming molten alloy droplets 3 with an alloy of Si and a catalytic metal such as Au can be employed.
[0038]
【The invention's effect】
As described above, according to the configuration of the present invention, the channel is formed on the peripheral surface of the columnar semiconductor 2 even though the occupation area of the base 1 can be reduced by adopting the vertical channel configuration. Since it is formed, it is possible to obtain a wide channel width of up to 100 nm.
Therefore, it is possible to improve conductance and cut-off frequency as compared with a transistor having a conventional planar channel configuration.
[0039]
In addition, according to the above-described manufacturing method of the present invention, the semiconductor device is constituted by a columnar semiconductor, and by forming the columnar semiconductor by the above-described VLS method, it can be configured with excellent reproducibility and uniformly. The semiconductor device having the above-described target characteristics can be stably manufactured in a mass production.
[Brief description of the drawings]
FIGS. 1A to 1D are schematic cross-sectional views in the main steps of an example of a manufacturing method of an apparatus of the present invention.
FIGS. 2A to 2D are schematic cross-sectional views in the main steps of an example of the manufacturing method of the apparatus of the present invention.
FIGS. 3A to 3D are schematic cross-sectional views in the main steps of an example of the manufacturing method of the apparatus of the present invention.
FIGS. 4A to 4C are schematic cross-sectional views in the main steps of an example of the manufacturing method of the apparatus of the present invention.
FIGS. 5A to 5C are process diagrams of an example of a method for manufacturing a columnar semiconductor for use in explaining the present invention. FIGS.
FIGS. 6A and 6B are process charts of an example of a method for manufacturing a columnar semiconductor for use in explaining the present invention. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Substrate, 1a ... Main surface, 2 ... Columnar semiconductor, 3 ... Molten alloy droplet, 4 ... Side surface, 5 ... Metal layer, 11 ... Insulating layer, 12. ..Semiconductor layer, 13 insulating layer, 13g ... gate insulating layer, 14 ... gate conductive layer, 15, 16 ... source or drain region, 17 ... buried insulating layer, 18 ... gate electrode Extraction conductive layer, 19 ... surface insulating layer, 21 ... first contact hole, 22 ... second contact hole, 23 ... third contact hole, 24 ... gate electrode, 25 , 26... Source or drain electrode 31... Position restricting film, 31 a.

Claims (4)

A columnar semiconductor is formed on the semiconductor, and a gate insulating layer is formed on the entire circumferential surface of the columnar semiconductor.
A gate conductive layer is formed on the outer peripheral surface of the gate insulating layer;
A buried insulating layer is formed on the outer periphery of the columnar semiconductor and the gate conductive layer so as to embed the columnar semiconductor and the gate conductive layer, and the columnar semiconductor and the gate conductive layer are exposed to the outside.
A gate electrode extraction conductive layer connected to the gate conductive layer is formed on the buried insulating layer,
A surface insulating layer is formed on the buried insulating layer by embedding the gate electrode conductive layer,
First and second contact holes are opened on the gate electrode extraction conductive layer and the columnar semiconductor of the surface insulating layer,
A third contact hole is opened on the semiconductor outside the formation portion of the columnar semiconductor over the surface insulating layer and the buried insulating layer below the surface insulating layer,
The gate electrode is brought into contact with the gate electrode extraction conductive layer through the first contact hole,
On the on the semiconductor of the pillar-shaped semiconductor of the upper end and the columnar semiconductor formed outsiders through the second and third contact holes, and wherein a source or drain electrode is formed by a contact. Forming a columnar semiconductor on the semiconductor;
Oxidizing the periphery of the columnar semiconductor to form a gate insulating layer;
Forming a gate conductive layer on the outer periphery of the gate insulating layer;
Burying the columnar semiconductor and the gate conductive layer, and forming a buried insulating layer exposing the top ends of the columnar semiconductor and the gate conductive layer to the surface;
Forming a gate electrode extraction conductive layer connected to the gate conductive layer on the buried insulating layer;
Forming a surface insulating layer on the buried insulating layer by embedding the gate electrode extraction conductive layer;
Opening first and second contact holes on the gate electrode extraction conductive layer of the surface insulating layer and the columnar semiconductor;
Opening a third contact hole over the surface insulating layer and the buried insulating layer therebelow on the semiconductor outside the columnar semiconductor formation portion;
The gate electrode is brought into contact with the gate electrode extraction conductive layer through the first contact hole, and the source is formed on the upper end of the columnar semiconductor and on the semiconductor outside the columnar semiconductor formation portion through the second and third contact holes. Or a method of manufacturing a semiconductor device, comprising the step of contacting a drain electrode. The step of forming a columnar semiconductor on the semiconductor includes
The semiconductor is made of silicon,
On said semiconductor, a step of depositing metal to form a silicon molten alloy droplets,
A heating step of forming molten alloy droplets of silicon and the metal,
3. The method of manufacturing a semiconductor device according to claim 2, wherein the method includes a step of thermally decomposing a silicon source gas to form a columnar semiconductor in the molten alloy droplet silicon forming portion. The silicone NHara material gas is a monosilane, disilane, a method of manufacturing a semiconductor device according to claim 3, characterized in that according to any one or more gases of trisilane.

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