JP2003142684A - Semiconductor element and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element and a semiconductor device which enable simplifying the control of characteristics and manufacturing processes. SOLUTION: A MOS transistor comprises an n<+> -type drain region 10 formed in the surface of a silicon substrate 1, a p-type well region 11 formed in the surface of the drain region 10, an n<+> -type source region 12 formed in the surface of the well region 11, and a gate electrode 13 which is embedded in the surface of the silicon substrate 1 via a gate insulation film 14 at a depth to the drain region 10 from the surface of the source region 12. Part of the drain region 10 and the well region 11 is extracted to the surface of the silicon substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element and a semiconductor device, and particularly to a miniaturized MOS (Metal Ox).
ide Semiconductor) relating to the structure of the transistor.

[0002]

2. Description of the Related Art In recent years, due to the rapid development of semiconductor manufacturing technology, miniaturization and high integration of devices have been advanced. However, with the miniaturization, adverse effects due to the short channel effect, the narrow channel effect and the like have become remarkable in the MOS transistor. Further, some problems have occurred due to miniaturization even in the manufacturing process, which is a factor that hinders further miniaturization and integration of elements.

The structure of a conventional MOS transistor will be described with reference to FIG. FIG. 30 shows a conventional MOS
It is sectional drawing of a transistor.

As shown in the figure, p
A mold well region 100 is provided. In the surface of the well region 100, the n ⁺ type source / drain region 11 is formed.
0 and 120 are provided so as to be separated from each other, and n ⁺ type LDD regions 130 and 140 are provided so as to be in contact with the source / drain regions 110 and 120 and be separated from each other. A gate electrode 160 is provided on the well region 100 between the LDD regions 130 and 140 with a gate insulating film 150 interposed, and a sidewall insulating film 170 is provided on the sidewall of the gate electrode 160. Further, the entire surface is covered with the interlayer insulating film 180, and the source / drain regions 110,
Source / drain electrodes 190, 200 connected to 120
Is provided. Then, the metal wiring layer 210 is provided on the interlayer insulating film 180 to form a MOS transistor.

Next, a method of manufacturing the MOS transistor having the above structure will be described with reference to FIGS. 31 (a) to 31 (e). 31A to 31E are cross-sectional views sequentially showing the manufacturing process of the MOS transistor.

First, as shown in FIG. 1A, a p-type well region 100 is formed by ion-implanting a p-type impurity into the surface of a silicon substrate. Next, as shown in FIG. 2B, a gate insulating film 150 is formed on the well region 100, and a gate electrode 160 is formed on the gate insulating film 150. Subsequently, LDD regions 130 and 140 are formed by ion-implanting n-type impurities into the surface of the well region 100 using the gate electrode 160 as a mask. Next, as shown in FIG. 6C, a sidewall insulating film 170 is formed on the sidewall of the gate electrode 160. Subsequently, the source / drain regions 110 and 120 are formed by ion-implanting n-type impurities into the well region surface using the gate electrode 160 and the sidewall insulating film 170 as a mask. Further, an interlayer insulating film 180 is deposited on the entire surface as shown in FIG.
As shown in the figure, the source / drain regions 110 and 120
A contact hole 220 reaching the above is formed in the interlayer insulating film 180. After that, the source / drain electrodes 190 and 200 are formed in the contact holes 220, and the metal wiring layer 210 is further formed on the interlayer insulating film 180, whereby the conventional MOS transistor shown in FIG. 30 is completed.

[0007]

However, the above-mentioned conventional M
The OS transistor has the following problems. (1) It is difficult to process the gate electrode. This is because the aspect ratio of the gate electrode becomes stricter (increased) as the device becomes finer. The aspect ratio of the gate electrode is the gate film thickness with respect to the gate length. This point will be described with reference to the cross-sectional view of the MOS transistor shown in FIG.

As shown in the figure, the gate length Lgate becomes smaller (gate length Lgate ') as the transistor generation progresses (miniaturization progresses), but on the other hand, the gate film thickness T increases.
The gate needs to maintain a constant size (gate film thickness Tgate '). This is due to the manufacturing process of the MOS transistor. As described above, the LDD regions 130, 1
The gate electrode 160 is used as a mask for ion implantation when forming 40, and the effective channel length Leff is controlled by this step. The gate electrode 160 also functions as a mask material when forming the source / drain regions 110 and 120. In order for the gate electrode to function as a mask material, a minimum film thickness is required to prevent ions from penetrating the gate electrode. That is, no matter how the miniaturization technology progresses, there is a limit to thinning the gate film thickness, and as a result, the aspect ratio of the gate electrode becomes strict.

If the aspect ratio becomes severe as described above, it becomes difficult to process the gate electrode. Because the gate electrode is usually processed by lithography process and etching process, when the aspect ratio becomes severe,
This is because resist collapse tends to occur during the lithography process. Further, a light source with a shorter wavelength is required for the exposure. Further, as shown in FIG. 33, the sidewall of the gate electrode has a taper angle (angle θ with respect to the direction perpendicular to the substrate surface).
To have. Then, it becomes difficult to control the characteristics of the ion implantation for forming the LDD region.

(2) It becomes difficult to control the characteristics of the MOS transistor. In the conventional MOS transistor manufacturing method as described above, the p-type impurity is ion-implanted when the well region 100 is formed, the source / drain regions 110, 120 and L are formed.
By the ion implantation at the time of forming the DD regions 130 and 140 and the heat treatment for activating the implanted impurities, MO
Characteristic control of the threshold voltage of the S-transistor, driving power, etc. is performed. Of these, the source / drain regions 110, 1
Ion implantation for forming the 20 and LDD regions 130 and 140 is performed using the gate electrode as a mask. Therefore, M
The characteristics of the OS transistor become very sensitive to the gate length Lgate of the gate electrode 160. Then, as the gate length Lgate becomes smaller, it becomes difficult to control the characteristics. Further, as described in (1) above, there is a problem that the characteristic control becomes difficult even when the side wall of the gate electrode has a taper angle.

(3) It is necessary to unnecessarily increase the thickness of the interlayer insulating film. This point will be described with reference to FIG. The thickness of the interlayer insulating film 180 is preferably such that the parasitic capacitance between the gate electrode 160 and the wiring layer 210 can be ignored. From this viewpoint, the ideal film thickness dsuit of the interlayer insulating film 180 is determined. However, since the gate electrode 160 is provided on the silicon substrate, it is actually necessary to additionally deposit the gate film thickness Tgate in addition to the ideal film thickness dsuit (interlayer insulation film thickness dins = dsuit + Tgate). This is not only a waste of the manufacturing process, but also makes the planarization process of the interlayer insulating film 180 difficult and requires a long time for the planarization process. In addition, unevenness is generated in the interlayer insulating film 180 between the portion where the gate electrode exists and the portion where the gate electrode does not exist. Therefore, even if the flattening process is performed, it is difficult to completely flatten the interlayer insulating film 180. As a result, there is a problem that the accuracy of the patterning process of the metal wiring layer 210 formed on the interlayer insulating film 180 is deteriorated.

(4) It is difficult to process the source / drain contact. As the device becomes finer, the contact holes that come into contact with the source / drain regions are naturally made finer. On the other hand, as described in (3) above, the film thickness of the interlayer insulating film needs to be increased excessively. as a result,
The aspect ratio of the contact hole (depth with respect to the bottom area of the contact hole) becomes large, making it difficult to open the contact hole and bury it.

In view of the above problems, a new MOS transistor structure capable of suppressing the short channel effect / narrow channel effect has been proposed. For example, IEEE Trans.
Electron Device, vol. 38, pp. 573-578, 1991 “Impa
ct of Surrounding Gate Transistor (SGT) for Ultra-
High-Density LSI's ”Hiroshi Takato et al.
A MOS transistor having a GT structure is disclosed. A MOS transistor having an SGT structure will be described with reference to FIGS. 34 and 35. 34 is a perspective sectional view of a MOS transistor having an SGT structure, and FIG. 35 is a sectional view.

As shown, drain regions 120, 120 are formed in the surface of the p-type well region (silicon substrate) 100.
Are provided so as to be separated from each other. A pillar-shaped well region 230 is provided on the well region 100 between the drain regions 120, 120, and a source region 110 is provided in the surface thereof. Then, by surrounding the side wall of the pillar-shaped well region 230,
A gate insulating film 150 and a gate electrode 160 are provided. Further, the entire surface is covered with the interlayer insulating film 180, and the drain electrode 200 connected to the drain region 120 is provided in the interlayer insulating film 180. Then, the interlayer insulating film 18
The MOS transistor is formed by providing the metal wiring layer 210 on 0.

The MOS transistor having the above structure has a structure in which a current flows between the source and the drain along the direction perpendicular to the substrate, and can solve the problems (1) and (2). However, the height dpillar of the pillar including the well region 230 and the source region 110 must be additionally added to the ideal film thickness dsuit to deposit the interlayer insulating film 180, and the problems (3) and (4) still remain. Remaining.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor element and a semiconductor device capable of simplifying characteristic control and simplifying a manufacturing process.

[0017]

In order to achieve the above object, a semiconductor element according to the present invention comprises a first semiconductor region of a first conductivity type provided in a surface of a semiconductor substrate, and the first semiconductor region.
A second semiconductor region of the second conductivity type provided in the surface of the semiconductor region, a third semiconductor region of the first conductivity type provided in the surface of the second semiconductor region, and a surface of the third semiconductor region A gate electrode embedded in the surface of the semiconductor substrate with a gate insulating film interposed to a depth reaching the first semiconductor region, part of the first and second semiconductor regions being the semiconductor substrate. It is characterized by being pulled out to the surface.

According to another aspect of the present invention, there is provided a semiconductor element having a first conductivity type first semiconductor region provided in a surface of a semiconductor substrate and a second conductivity type first semiconductor region provided in a surface of the first semiconductor region. A second semiconductor region, a third semiconductor region of the first conductivity type provided in the surface of the second semiconductor region, and a gate insulating film interposed at a depth from the surface of the third semiconductor region to the first semiconductor region. And an element portion having a gate electrode embedded in the surface of the semiconductor substrate and having a channel formed in the second semiconductor region in contact with the gate insulating film, and the first and second semiconductor regions. A contact portion that is drawn out to the surface of the semiconductor substrate and is electrically isolated from each other by a first insulating film, and a third semiconductor region and a gate electrode that are provided between the element portion and the contact portion. Previous Wherein the contact portion first, is characterized by comprising an insulating portion provided with the second insulating film to electrically isolate between the second semiconductor region.

Further, in the semiconductor element according to the present invention, the first conductive type first semiconductor region provided in the surface of the semiconductor substrate and the second conductive type region provided in the partial surface region of the first semiconductor region. -Type second semiconductor region, a third semiconductor region of the first conductivity type provided in a partial surface region of the second semiconductor region, and a depth from the surface of the third semiconductor region to the first semiconductor region A gate electrode embedded in the semiconductor substrate surface with a gate insulating film interposed between the first and second semiconductor regions adjacent to each other on the semiconductor substrate surface, and the third semiconductor region and the gate electrode. And an insulating film provided between the first and second semiconductor regions.

A semiconductor device according to the present invention includes a plurality of the above semiconductor elements, and the adjacent semiconductor elements share the gate electrode or one of the first to third semiconductor regions.

Further, a semiconductor device according to the present invention includes a plurality of the semiconductor elements described above, and any one of the first to third semiconductor regions commonly connected between the semiconductor elements is provided adjacent to each other. It is characterized by being.

Further, a semiconductor device according to the present invention includes at least two of the above semiconductor elements, the semiconductor elements share the gate electrode, and the first to third semiconductor regions are symmetrical with respect to the gate electrode. It is characterized in that any one of the second semiconductor region and the third semiconductor region, which are provided in the contact portion and are commonly connected to each other, are adjacent to each other in the contact portion.

In the semiconductor element and the semiconductor device as described above, the gate electrode is embedded in the semiconductor substrate, the gate length is controlled by the depth of the trench formed in the semiconductor substrate when the gate is embedded, and the gate film is formed. The thickness is controlled by its trench width. Therefore, when the gate length and the gate film thickness are reduced, problems caused by the lithography process such as resist collapse do not occur. Rather, since the trench depth becomes smaller as the miniaturization progresses, the trench opening step and the step of filling the trench with the gate electrode can be simplified, and the processing of the gate electrode can be facilitated.

Further, with the structure in which the gate electrode is embedded in the semiconductor substrate, it is not necessary to use the gate electrode as a mask material when forming the impurity diffusion layer as in the conventional case. Therefore,
Even if the miniaturization of the gate electrode progresses, it does not affect the impurity diffusion layer forming process at all. That is, it is possible to prevent deterioration of characteristic controllability such as threshold voltage and driving power of the element due to miniaturization of the semiconductor element.

Furthermore, by embedding the gate electrode in the semiconductor substrate, there is no extra protrusion on the semiconductor substrate.
Therefore, the interlayer insulating film that protects the semiconductor element can be deposited with an ideal film thickness. As a result, the planarization process of the interlayer insulating film can be simplified and the planarization process can be performed in a short time. Further, since the gate electrode does not exist on the base (semiconductor substrate surface) on which the interlayer insulating film is formed, unevenness on the surface of the deposited interlayer insulating film itself is reduced. Therefore, the flatness of the surface of the interlayer insulating film after the flattening step is improved. Consequently, the accuracy of the patterning process of the metal wiring layer formed on the interlayer insulating film can be improved. As described above, since it is not necessary to unnecessarily increase the film thickness of the interlayer insulating film, the aspect ratio of the contact hole formed in the interlayer insulating film can be made smaller than in the conventional case. Therefore, the process of opening the contact hole and the process of filling the contact hole can be simplified, and the contact can be easily processed.

Further, at least a part of each semiconductor region is exposed on the surface of the semiconductor substrate. That is, all the electrodes can be provided on the surface of the semiconductor substrate. Therefore, it is possible to reduce the occupied area and the number of wirings when a logic circuit or the like is formed.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. When explaining this,
Common parts are designated by common reference numerals.

A semiconductor element and a semiconductor device according to the first embodiment of the present invention are shown in FIGS.
This will be described with reference to (b) and FIG. FIG. 1 is a perspective sectional view of the MOS transistor according to the present embodiment.
1A is a perspective cross-sectional view including a cross section taken along line X1-X1 'in FIG. 1, FIG. 2B is a perspective cross-sectional view including a cross section taken along line X2-X2', and FIG. 3 is an equivalent circuit diagram. is there.

As shown in the figure, the MOS transistor according to this embodiment has three blocks of an element portion A1, a contact portion A2 and an insulating portion A3.

In the element portion A1, the well region (p-type semiconductor region) 11 is provided in the surface of the drain region (n ⁺ type semiconductor region) 10 provided in the surface of the silicon substrate 1, and the surface of the well region 11 is provided. A source region (n ⁺ type semiconductor region) 12 is provided inside. That is, the source region 12 is exposed on the surface of the silicon substrate 1. Then, the gate electrode 13 is buried so as to reach the drain region 10 from the surface of the source region 12 (the surface of the silicon substrate) with the gate insulating film 14 interposed. Further, a source electrode (not shown) is provided on the source region 12 exposed on the surface of the silicon substrate 1.

In the contact portion A2, a part of the drain region 10 in the element portion A1 is extended so as to reach the surface of the silicon substrate 1, and a part of the well region 11 in the element portion A1 also reaches the surface of the silicon substrate 1. Has been extended. An insulating film 15 buried from the surface of the silicon substrate 1 to a depth deeper than the well region 11 is provided between the drain region 10 and the well region 11 to electrically separate the two. Further, a drain electrode and a well electrode (not shown) are provided on the drain region 10 and the well region 11 exposed on the surface of the silicon substrate in the contact portion A2, respectively.

A region between the element portion A1 and the contact portion A2 is an insulating portion A3, and an insulating film 15 is provided so as to reach the drain region 10 from the surface of the silicon substrate 1. However, the well region 11 in the element portion A1
A part of the insulating film 15 located deeper than that is removed, and the well region 11 of the element portion A1 and the well region 11 of the contact portion A2 are electrically connected via this region. Further, the drain region 10 of the element portion A1 and the drain region 10 of the contact portion A2 are electrically connected via a position deeper than the insulating film 15. The gate electrode 13 and the source region 12 of the element portion A1 are electrically completely separated from the contact portion A2 by the insulating film 15.

Next, the operation of the MOS transistor having the above structure will be described. When a forward voltage is applied between the source and drain and a threshold voltage is applied to the gate electrode 13, a channel is formed in the well region 11 of the element portion A1 in contact with the gate insulating film 14 (channel formation in the figure). region). Then, the electrons in the source region 12 flow into the drain region via the channel, and the MOS transistor is turned on. That is, in the element portion A1, the current flows in the direction perpendicular to the surface of the silicon substrate 1.

Next, a method of manufacturing the MOS transistor having the above structure will be described with reference to FIGS. 4 (a) and 4 (b) and FIGS.
Will be explained. 4A, 4B, and 5 to 10 are perspective sectional views sequentially showing the manufacturing process of the MOS transistor according to the present embodiment. Note that FIG.
It is a perspective sectional view including a section of the X3-X3 'line direction in (a).

First, STI (Shallow Trench Isolatio)
n) a trench 16 for forming an insulating film is formed in the contact portion A2 and the insulating portion A3 of the silicon substrate 1 by the technique shown in FIG.
It is formed as shown in (a) and (b).

Next, as shown in FIG. 5, an insulating film 15 such as a silicon oxide film is deposited on the entire surface to completely fill the trench 16. Then, the insulating film 15 is formed by CMP (Chemical M
The surface of the silicon substrate 1 is exposed by polishing and flattening by an echanical polishing method or the like.

Next, as shown in FIG. 6, an n-type impurity such as arsenic is ion-implanted into the silicon substrate 1 to obtain n ^+.
A mold drain region 10 is formed. At this time, impurities are implanted to a certain depth or more of the silicon substrate 1 and the insulating portion A3
The ion implantation is performed by adjusting the acceleration voltage so as to reach the region directly below the insulating film 15 in the above. As a result, the element part A
1 and the drain region 10 in the contact portion A2,
Bonding is performed in a region immediately below the insulating film 15 in the insulating portion A3.
Further, in a part of the contact portion A2, an n-type impurity is further ion-implanted to form the drain region 10 to a depth corresponding to a well region formation planned region in the device region A1 later.

Subsequently, as shown in FIG. 7, p-type impurities such as boron are ion-implanted into the silicon substrate 1 to form the p-type well region 11. At this time, in the element portion A1, the impurities reach the surface of the drain region 10 from a certain depth from the surface of the silicon substrate 1 and the contact portion A1.
In part 2, the surface of the silicon substrate 1 is reached to the surface of the drain region 10, and in the insulating part A3, part of the insulating film 15 is penetrated, and the element part A1 and the contact part A are formed.
Ion implantation is performed by adjusting the accelerating voltage so that the well region 11 in 2 and the well region 11 are bonded to each other in the region immediately below the insulating film 15.

Subsequently, as shown in FIG. 8, an n-type impurity such as arsenic is ion-implanted into the silicon substrate 1 to form the element portion A1.
To complete the source region 12 and the drain region 10 in the contact portion A2. At this time, in the element portion A1, impurities are transferred from the surface of the silicon substrate 1 to the well region 1
1 is reached, and the ion implantation is performed by adjusting the acceleration voltage so as to reach the surface of the drain region 10 from the surface of the silicon substrate 1 in a part of the contact portion A2. However, it is necessary to prevent p-type impurities from being implanted into the region where the well region 11 is provided in the contact portion A2. In this step, the drain region 10, the well region 11, the source region 12 in the element portion A1,
And the drain region 10 and the well region 11 in the contact portion A2 are completed. The source region 12 in the element portion A1, the well region 11 and the drain region 10 in the contact portion A2 are exposed on the surface of the silicon substrate 1, and the source region 12 and the contact portion A in the element portion A1 are exposed.
The structure in which the second drain region 10 and the well region 11 are electrically separated by the insulating film 15 in the insulating portion A3 is completed.

Next, as shown in FIG. 9, a trench 17 extending from the surface of the source region 12 (surface of the silicon substrate 1) to the drain region 10 is formed in the element portion A1 by the STI technique. The trench 17 is a groove for forming a gate electrode, and is formed so that the entire surface in contact with the insulating portion A3 faces the insulating film 15.

Subsequently, as shown in FIG. 10, the side surface and the bottom surface of the trench 17 are oxidized by a thermal oxidation method or the like to form the gate insulating film 14.

After that, CVD (Chemical Vapor Deposit)
A conductive film such as a polycrystalline silicon film is formed on the entire surface by the ion method or the like to fill the trench 17. Then, the gate electrode 13 is formed by polishing and planarizing by CMP or the like until the surface of the silicon substrate 1 is exposed. Of course, the gate electrode 13 is insulated from the contact portion A2 by the insulating film 15 in the insulating portion A3. Through the above steps, the MOS transistor having the structure shown in FIGS. 1 and 2 is completed.

With the MOS transistor having the above structure,
The following effects can be obtained. (1) The gate electrode can be easily processed. This point will be described with reference to FIG. FIG. 11 shows M according to the present embodiment.
It is sectional drawing of an OS transistor. As described above, the gate length Lgate becomes smaller (gate length Lgate ') as the generation of transistors progresses (miniaturization progresses). On the other hand, in the conventional structure, since the gate electrode is used as a mask at the time of ion implantation, the gate film thickness Tgate cannot be made small, which makes the aspect ratio of the gate electrode strict and thus makes it difficult to process the gate electrode. Was there. However, in the MOS transistor according to this embodiment, the gate electrode 16 is not a mask material for forming the source / drain regions 10 and 12. Therefore, the gate film thickness Tgate can be made sufficiently small. Further, since the gate electrode 16 has a structure to be embedded in the trench 16 formed in the silicon substrate 1, the lithography process is no longer required for processing the gate electrode 160. That is, the gate length Lgate is controlled by the depth of the trench 16, and the gate film thickness Tgate is controlled by the width of the trench 16. Therefore, problems such as resist collapse do not occur when the gate length Lgate and the gate film thickness Tgate are reduced. On the contrary, since the depth of the trench 16 becomes smaller as the miniaturization progresses, the step of opening the trench 16 and the step of filling the trench 16 with the gate electrode 13 can be simplified, and the processing of the gate electrode can be facilitated. Of course, the problem that the gate electrode has a taper angle can be solved.

(2) It becomes easy to control the characteristics of the MOS transistor. As described in the prior art, in the conventional MOS transistor, since the source / drain regions are formed by ion implantation using the gate electrode as a mask, it becomes difficult to control the characteristics thereof as the gate length Lgate becomes smaller. It was However, in the MOS transistor according to this embodiment, the gate electrode 13 does not participate in the formation of the source / drain regions 10 and 12. Therefore, it is possible to prevent the adverse effect that the miniaturization of the gate electrode 13 has on the characteristic control. In addition, the characteristic control of the MOS transistor is
Since it is determined by the dose amount and the implantation depth of the impurities in the ion implantation at the time of forming the well / source regions 10, 11 and 12, the controllability of characteristics such as the threshold voltage of the MOS transistor and the driving power can be greatly improved and simplified. .

(3) The interlayer insulating film thickness can be minimized. This point will be described with reference to FIG. FIG. 12 is a cross-sectional view of the MOS transistor, particularly the element portion A1.
As shown in the drawing, an interlayer insulating film 18 is formed on the silicon substrate 1 on which the MOS transistor is formed, and a contact hole 19 reaching the source region 12 is formed in the interlayer insulating film 18, and the contact hole 19 is formed in the contact hole 19. The source electrode 20 is embedded and formed. Of course, in the contact portion (not shown), the well region 11 and the drain region 10
Is formed, and an electrode is formed therein. Then, the metal wiring layer 2 is formed on the interlayer insulating film 18.
1 is formed. In the case of the MOS transistor having the conventional structure, since the gate electrode is present on the silicon substrate, it is necessary to additionally deposit the interlayer insulating film by the gate thickness Tgate. However, in the MOS transistor according to this embodiment, the gate electrode 13 is embedded in the silicon substrate 1. That is, there is no extra protrusion (gate electrode) on the silicon substrate 1. Therefore, the interlayer insulating film 18
It is not necessary to increase the film thickness dins excessively during the deposition, and the interlayer insulating film 18 can be deposited with the ideal film thickness dsuit. As a result, the planarization process of the interlayer insulating film 18 can be simplified and the planarization process can be performed in a short time. Further, since the gate electrode is not present on the base (the surface of the silicon substrate 1) on which the interlayer insulating film 18 is formed, the surface of the deposited interlayer insulating film 18 itself has less unevenness. Therefore, the flatness of the surface of the interlayer insulating film 18 after the flattening step by the CMP method is improved. Therefore, the accuracy of the patterning process of the metal wiring layer 21 formed on the interlayer insulating film 18 can be improved.

(4) The source / drain contact can be easily processed. As described in (3) above, the film thickness dins of the interlayer insulating film 18 can be formed to have an ideal film thickness dsuit. As a result, the aspect ratio of the contact hole can be made smaller than in the conventional case. Therefore, the process of opening the contact hole and the process of filling the contact hole can be simplified, and the source / drain contact can be easily processed.

(5) It is possible to reduce the area occupied by the logic circuit and the wiring. This is because all the potentials of the source / drain / well regions can be applied from the surface of the silicon substrate. This point will be described in detail in the second to fourth embodiments below.

A semiconductor element and a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 13, 14A to 14C, and 15. In this embodiment,
The inverter circuit is configured by using the MOS transistor described in the first embodiment. FIG. 13 is a perspective sectional view of the inverter circuit according to the present embodiment. 14A is a perspective cross-sectional view including a cross section taken along line X4-X4 ′ in FIG. 13, and FIG. 14B is X5-X5 ′.
A perspective cross-sectional view including a cross section in a line direction, FIG.
FIG. 16 is a perspective cross-sectional view including a cross section in the X6 ′ line direction, and FIG. 15 is an equivalent circuit diagram.

As shown in FIG. 15, the inverter circuit has an nMOS transistor 50 having a gate connected to the input terminal IN and a source connected to the negative power supply potential Vss.
And the gate connected to the input terminal IN and the positive power supply potential V
It includes a pMOS transistor 51 having a source connected to cc and a drain connected to the drain of the nMOS transistor 50. The connection node between the drain of the nMOS transistor 50 and the drain of the pMOS transistor 51 becomes the output terminal OUT.

The nMOS transistor 50 has the structure described in the first embodiment, as shown in FIGS. 13 and 14A.

In the pMOS transistor 51, as shown in FIGS. 13 and 14C, the conductivity type of each semiconductor region of the nMOS transistor 50 is reversed. That is, in the element portion A1, the well region (n-type semiconductor region) 31 is formed in the surface of the drain region (p ⁺ type semiconductor region) 30 provided in the surface of the silicon substrate 1 in which the nMOS transistor 50 is formed. Well region 31 provided
A source region (p ⁺ type semiconductor region) 32 is provided in the surface of the. Then, the drain region 30 is reached from the surface of the source region 32 (the surface of the silicon substrate), and n
The gate electrode 13 shared with the MOS transistor 50 is embedded with the gate insulating film 14 interposed.

In the contact portion A2, a part of the drain region 30 in the element portion A1 is extended so as to reach the surface of the silicon substrate, and a part of the well region 31 in the element portion A1 also reaches the surface of the silicon substrate 1. Has been extended. Further, between the drain region 30 and the well region 31, there is an insulating film 15 buried from the surface of the silicon substrate 1 to a depth deeper than the well region 31 to electrically separate the two.

The region between the element portion A1 and the contact portion A2 is the insulating portion A3, and the insulating film 15 is provided so as to reach the drain region 30 from the surface of the silicon substrate 1. However, the well region 31 in the element portion A1
A part of the insulating film 15 located deeper than that is removed, and the well region 31 of the element portion A1 and the well region 31 of the contact portion A2 are electrically connected via this region. The drain region 30 of the element portion A1 and the drain region 30 of the contact portion A2 are electrically connected via a position deeper than the insulating film 15. Further, the gate electrode 13 and the source region 32 of the element portion A1 are electrically completely separated from the contact portion A2 by the insulating film 15.

The pMOS transistor 51 and the nMOS transistor 50 as described above share the gate electrode 13, and the drain region 10 in the contact portion A2,
30 are formed in the same silicon substrate 1 so as to be in contact with each other (see FIG. 14B). That is, two MOS transistors having opposite conductivity types are formed in the silicon substrate 1 so that their source / drain / well regions are symmetrical with respect to the gate electrode 13. And
The gate electrode 13 serves as the input terminal IN of the inverter, the drain regions 10 and 30 serve as the output terminal OUT, and the source regions 12 and 32 of the nMOS transistor 50 and the pMOS transistor 51 are connected to the power supply potential Vss and the power supply potential Vcc in the element portion A1. , Well regions 11 and 31 of both
Is connected to the ground potential at the contact portion A2.

Next, the operation of the MOS transistor having the above structure will be described with reference to FIG. FIG. 16 is a state diagram (truth table) of input / output signals of the inverter circuit.
When a negative threshold voltage (“0”) is applied to the gate electrode 13, a channel is formed in the well region 31 of the element portion A1 of the pMOS transistor 51 in the region in contact with the gate insulating film 14. Then, holes in the source region 32 flow into the drain region via the channel, and the pMOS transistor 51 is turned on. On the other hand, since no channel is formed in the well region 11 of the element portion A1 of the nMOS transistor 50, it is in the off state. As a result, the output terminal OUT becomes the power supply potential (output “1”).

On the contrary, when a positive threshold voltage (“1”) is applied to the gate electrode 13, the gate insulating film 14 is formed in the well region 11 of the element portion A 1 of the nMOS transistor 50.
A channel is formed in a region in contact with. Then, the electrons in the source region 12 flow into the drain region via the channel, and the nMOS transistor 50 is turned on.
On the other hand, since no channel is formed in the well region 31 of the element portion A1 of the pMOS transistor 51, it is in the off state. As a result, the output terminal OUT becomes the ground potential (output “0”).

If a logic circuit is constructed using the MOS transistors according to the first embodiment as in this embodiment,
It is possible to reduce the area occupied by the logic circuit and the wiring. This point will be described in comparison with the case where a MOS transistor having a conventional structure is used. FIG. 17 is a perspective sectional view of the inverter according to this embodiment. 18 and 19
FIG. 3 is a perspective cross-sectional view of an inverter configured using conventional planar type and SGT structure MOS transistors.

As shown in FIGS. 18 and 19, when an inverter is formed using conventional planar type and SGT structure MOS transistors, an nMOS transistor and a pM are used.
The OS transistor includes a p-type well region 100 and an n-type well region 30 which are electrically isolated by an element isolation region 400.
Each is formed within 0. The source region 110 of the nMOS transistor is connected to the power supply potential Vss through the metal wiring layer 210-1, and the source region 310 of the pMOS transistor is connected to the power supply potential Vcc through the metal wiring layer 210-2.
Connected to. Further, both drain regions 120 and 320
Are connected by the metal wiring layer 210-3 provided so as to straddle the element isolation region 400, and then the output terminal O
Connected to UT.

In contrast to the conventional inverter circuit described above, in the structure according to the present embodiment, as shown in FIG. 17, an nMOS transistor and a pMOS transistor are provided in a region separated by the gate electrode 13 so as to sandwich the gate electrode 13. Is forming. The source region 12 of the nMOS transistor is the metal wiring layer 21-1 and has the power supply potential V
Source region 3 of pMOS transistor connected to ss
2 is a metal wiring layer 21-2, which is connected to the power supply potential Vcc. Further, the drain regions 10 and 30 of the both are connected by the common drain electrode 21-3, and are directly connected to the output terminal OU.
Connected to T.

That is, the structure according to this embodiment does not require the element isolation region 400 for electrically isolating the well region. Therefore, the element area required for forming the inverter can be reduced. Two more drain regions 10, 3
Since 0s are adjacent to each other, the common electrode 21-3 can be used, and the metal wiring layer 210-3 for connecting the two is not required. Therefore, the number of wires for forming the inverter can be reduced. As a result, it is possible to reduce the manufacturing cost of the logic circuit and simplify the manufacturing process.

Next, a semiconductor element and a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIGS. In this embodiment, a NOR circuit is constructed using the MOS transistors described in the first embodiment. FIG. 20 is a perspective sectional view of a NOR circuit configured by using the MOS transistor described in the first embodiment. Also, FIG.
1A is a perspective sectional view including a section taken along line X7-X7 'in FIG. 20, FIG. 21B is a perspective sectional view including a section taken along line X8-X8', and FIG. A perspective cross-sectional view including a cross-sectional view taken along the line X9 ′, and FIG.
FIG. 22 is a perspective cross-sectional view including a cross-sectional view taken along the line −X10 ′, and FIG. 22 is an equivalent circuit diagram.

The NOR circuit as shown in FIG.
S transistors 52 and 54 and pMOS transistor 5
3, 55, and nMOS transistor 52 and p
The MOS transistor 53 constitutes an inverter 56. The nMOS transistor 52 has a gate connected to the input terminal IN1, a source connected to the negative power supply potential Vss, and a drain connected to the output terminal OUT. The nMOS transistor 54 has an input terminal IN2.
, A source connected to the power supply potential Vss, and a drain connected to the output terminal OUT. The pMOS transistor 53 has a gate connected to the input terminal IN1 and a drain connected to the output terminal OUT. The pMOS transistor 55 has a gate connected to the input terminal IN2, a source connected to the positive power supply potential Vcc, and a drain connected to the source of the pMOS transistor 53.

The inverter 56 composed of the nMOS transistor 52 and the pMOS transistor 53 is
As shown in FIGS. 20 and 21 (b), it has the structure described in the second embodiment. That is, the two MOS transistors 52 and 53 are formed in the silicon substrate so as to be symmetrical with respect to the shared gate electrode 13-1.

As shown in FIGS. 20, 21A and 21B, the nMOS transistor 54 is electrically connected to the source / drain regions 10 and 11 and the well region 11 which are shared with the nMOS transistor 52, and the gate electrode 13-1. The gate electrode 13-3 is electrically separated.

Further, the pMOS transistor 51 is similar to that shown in FIG.
0, as shown in FIG. 21D, in the element portion A1,
The source region (p ⁺⁾ provided in the surface of the silicon substrate 1
A well region (n-type semiconductor region) 31 is provided in the surface of the type semiconductor region 30 and a drain region (p ⁺ type semiconductor region) 32 is provided in the surface of the well region 31.
The p ⁺ type semiconductor region which is the drain region of the pMOS transistor is shared with the source region of the pMOS transistor. Then, the source region 30 is reached from the surface of the drain region 32 (the surface of the silicon substrate),
A gate electrode 13-2, which is electrically separated from the gate electrodes 13-1 and 13-3, is buried with a gate insulating film 14 interposed.

An isolation portion is provided between the pMOS transistors 53 and 55. In this separation part, the insulating film 15 of the insulating part A3 is extended to the element part A1 as well, and electrically separates the drain region 30-1 and the source region 30-2. Further, in the isolation portion, the well region 31-1 of the pMOS transistor 53 and the well region 31-2 of the pMOS transistor 55 are joined.

The gate electrode 13-1 serves as the input terminal IN1 of the NOR circuit, the gate electrodes 13-2 and 13-3 serve as the input terminal IN2, and the drain regions 10 and 30-1 serve as the output terminal OUT. The source region 12 shared by the nMOS transistors 52 and 54 is connected to the power supply potential Vss in the element portion A1, and the well regions 11 of the nMOS transistors 52 and 54 and the well regions 31-1 and 31-2 of the pMOS transistors 53 and 55 are formed. The contact portion A2 is connected to the ground potential, and the source region 30-2 of the pMOS transistor 55 is connected to the power supply potential Vcc at the contact portion A2.

Next, the operation of the MOS transistor having the above structure will be described with reference to FIG. FIG. 23 is a state diagram (truth table) of input / output signals of the NOR circuit. Gate electrode 13-1 (input terminal IN1) and gate electrode 13
-2, 13-3 (input terminal IN2) is applied with a negative threshold voltage ("0"), the pMOS transistor 53,
In the well regions 31-1 and 31-2 of the element portion A1 of 55, channels are formed in the regions in contact with the gate insulating films 14-1 and 14-2. Then, pMOS transistor 5
3, 55 are turned on. On the other hand, since no channel is formed in the well region 11 of the element portion A1 of the nMOS transistors 52 and 54, it is in the off state. As a result, the output terminal OUT becomes the power supply potential (output “1”).

A negative threshold voltage ("0") is applied to the gate electrode 13-1 (input terminal IN1), and the gate electrodes 13-2 and 13-.
When a positive threshold voltage (“1”) is applied to 3 (input terminal IN2), a channel is formed in the well region 11 of the element portion A1 of the nMOS transistor 54 in a region in contact with the gate insulating film 14-3. Then, the nMOS transistor 54 is turned on. Similarly, the pMOS transistor 53 is turned on. However, since the nMOS transistor 52 and the pMOS transistor 55 are in the off state, the output terminal OUT becomes the ground potential (output “0”).

A positive threshold voltage ("1") is applied to the gate electrode 13-1 (input terminal IN1), and the gate electrodes 13-2 and 13-
When a negative threshold voltage (“0”) is applied to 3 (input terminal IN2), a channel is formed in the well region 11 of the element portion A1 of the nMOS transistor 52 in a region in contact with the gate insulating film 14-1. Then, the nMOS transistor 52 is turned on. Similarly, the pMOS transistor 55 is turned on. However, since the nMOS transistor 54 and the pMOS transistor 53 are in the off state, the output terminal OUT becomes the ground potential (output “0”).

When a positive threshold voltage ("1") is applied to the gate electrode 13-1 (input terminal IN1) and the gate electrodes 13-2 and 13-3 (input terminal IN2), the element parts of the nMOS transistors 52 and 54 are applied. In the well region 11 of A1, a channel is formed in a region in contact with the gate insulating films 14-1 and 14-2. Then, the nMOS transistor 5
2, 54 are turned on. On the other hand, since the pMOS transistors 53 and 55 are off, the output terminal OUT
Becomes the ground potential (output “0”).

Even when the NOR circuit as well as the inverter circuit is constructed as in the present embodiment, the occupied area and wiring can be reduced. Of course, the same effect can be obtained not only when the inverter and the NOR circuit are used but also when another logic circuit such as a NAND circuit is configured.

Next, a semiconductor element and a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 24 and 25 (a).
26A to 26F, and FIGS. 26A to 26F and 27. In this embodiment, a semiconductor memory using the MOS transistor described in the first embodiment, particularly an S
A RAM (Static Random Access Memory) is configured. FIG. 24 is a perspective sectional view of the SRAM. Figure 2
5A is a perspective cross-sectional view including a cross section taken along line X11-X11 ′ in FIG. 24, and FIG. 25B is X12-X12 ′.
A perspective cross-sectional view including a cross section in the line direction, FIG.
25 is a perspective cross-sectional view including a cross section in the direction of the line X13 ′.
25D is a perspective sectional view including a cross section in the X14-X14 ′ line direction, FIG. 25E is a perspective sectional view including a cross section in the X15-X15 ′ line direction, and FIG. 25F is a X16-X16 ′ line direction. FIG. 6 is a perspective sectional view including a section of FIG. FIG. 26 (a) is shown in FIG.
26B is a perspective sectional view including a cross section in the X17-X17 'line direction, FIG. 26B is a perspective sectional view including a cross section in the X18-X18' line direction, and FIG. 26C is a cross section in the X19-X19 'line direction. FIG. 26D is a perspective cross-sectional view including X20-X2.
A perspective cross-sectional view including a cross section in the 0 ′ line direction, FIG.
FIG. 26 is a perspective cross-sectional view including a cross section taken along line 21-X21 ′ of FIG.
(F) is a perspective cross-sectional view including a cross section taken along line X22-X22 'of the inverter. FIG. 27 is an equivalent circuit diagram of the SRAM memory cell.

As shown in FIG. 27, the unit memory cell 70 of the SRAM has two SRAM blocks BLK1 and BLK.
Have two. SRAM block BLK1 is pMO
S transistor 57, nMOS transistors 58 and 59
In addition, the pMOS transistor 57 and the nMOS transistor 58 form an inverter 63. The SRAM block BLK2 includes a pMOS transistor 60 and nMOS transistors 61 and 62, and the pMOS transistor 60 and the nMOS transistor 61 constitute an inverter 64.
The output node N2 of the inverter 63 is connected to the input node of the inverter 64, and the output node N1 of the inverter 64 is connected to the input node of the inverter 63. Further, the output node N2 of the inverter 63 is an nMOS
Connected to the drain of transistor 59, inverter 6
The output node N1 of No. 4 is connected to the drain of the nMOS transistor 62. The gates of the nMOS transistors 59 and 62 are connected to the word line WL, and the sources of the nMOS transistors 59 and 62 are connected to the bit lines BL and BL '.

Transistors configuring the SRAM
Has the structure described in the first embodiment.
It is embedded in the control substrate 1. 24 and 25
As shown in (a) to (f) and FIGS. 26 (a) to (f).
As described above, the inverter 63 has been described in the second embodiment.
It is similar to the structure. In addition, nMOS transistors 59 and 6
The second structure also has the same structure as that described in the first embodiment.
Have Inverters 63 and 64 and nMOS transistor
Separation parts S1 and S4 and connection between the star 59 and 62.
Source regions adjacent to which parts J1 and J4 are provided
(N⁺Type semiconductor region) and well region (p type semiconductor region)
Region) while electrically separating the drain region (n ⁺Mold
Body area). In addition, nMOS transistor 5
Adjacent to 9, 62 are SRAM blocks BLK1, BL
Connection parts J2, J3 of nodes N1, N2 connecting K2
Are provided with the separating portions S2 and S3 interposed therebetween. SR
Element isolation region between AM blocks BLK1 and BLK2
And is embedded in the silicon substrate 1.
The insulating film 40 is formed.

Even when the SRAM is constructed by using the MOS transistor according to the first embodiment as in the present embodiment, it is possible to reduce the occupied area and wiring.

As described above, according to the semiconductor element and the semiconductor device according to the first to fourth embodiments of the present invention, the gate electrode can be easily processed, and the manufacturing process can be simplified and the manufacturing cost can be reduced. Becomes In addition, it becomes easier to control the characteristics of the MOS transistor, and even if miniaturization progresses,
It can maintain and improve its reliability. Furthermore, since the interlayer insulating film can be formed to have a necessary and sufficient ideal film thickness, it is possible to further simplify the manufacturing process and reduce the manufacturing cost, and to improve its performance and reliability. Contribute. At the same time, since it is not necessary to increase the thickness of the interlayer insulating film, the contact can be easily processed, and the manufacturing accuracy and reliability of the electrodes and wiring can be improved. Further, the area and wiring required for the circuit configuration can be reduced, and the manufacturing cost of the semiconductor element and the semiconductor device can be further reduced.

The structure of the MOS transistor according to the above embodiment is not limited to the structure shown in FIG. That is, in the structure in which the source / drain / well region and the gate electrode are embedded in the silicon substrate, it is sufficient that these electrodes can be taken out from the surface of the silicon substrate. As another structure different from FIG. 1, for example, FIG.
8 and the like. FIG. 28 is a perspective sectional view of a MOS transistor. In this structure, as shown in the figure, an insulating portion A3 and a contact portion A2 are sequentially arranged parallel to the channel length direction of the gate electrode 13. Even with such a structure, a potential can be applied from the surface of the silicon substrate 1 to all regions. Also, in the structure shown in FIG.
You may comprise one MOS transistor. 29 is M
FIG. 14 is a perspective sectional view of an OS transistor, and one MOS transistor is configured by combining the MOS transistors of the same conductivity type shown in FIG. 1 in the same manner as the inverter circuit of FIG. 13. According to this configuration, the same effect as that of effectively increasing the channel width can be obtained, so that the drive power amount of the MOS transistor can be increased.

Of course, the present invention is not applied only to the MOS transistor, and for example, SIT (Static Inducing)
tion Transistor), IGBT (Insulated Gate Bipola)
Needless to say, it can be applied to semiconductor devices such as r Transistor) or diodes. Further, although the MOS transistor using silicon as a semiconductor has been described as an example, the present invention can be applied to the case of using a compound semiconductor such as gallium arsenide or silicon carbide. Further, in the above-described embodiment, the case where the MOS transistor is embedded in the silicon substrate 1 by forming the source / drain / well regions by ion implantation has been described as an example. However, any or all of the above regions may be deposited and formed by, for example, an epitaxial growth method or the like. Even in the case of forming by ion implantation, the manufacturing method is not limited to the method described with reference to FIGS. 4A and 4B and FIGS. For example, in the process of FIG. 6, the n ⁺ type semiconductor region 10 may be formed until it reaches the surface of the silicon substrate 1. In this case, the p-type semiconductor region 11 is formed in the n ⁺ -type semiconductor region 10 by implanting the p-type impurity at a high concentration in the process of FIG. Of course, the p-type semiconductor region 11 may be formed up to the surface of the silicon substrate 1.

The invention of the present application is not limited to the above-mentioned embodiment, and can be variously modified at the stage of implementation without departing from the spirit of the invention. Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, the problems described in the section of the problem to be solved by the invention can be solved, and the effects described in the section of the effect of the invention When the above is obtained, the configuration in which this constituent element is deleted can be extracted as the invention.

[0081]

As described above, according to the present invention, it is possible to provide the semiconductor element and the semiconductor device which can simplify the characteristic control and the manufacturing process.

[Brief description of drawings]

FIG. 1 is a perspective sectional view of a MOS transistor according to a first embodiment of the present invention.

FIG. 2 shows a MOS transistor according to the first embodiment of the present invention, and FIG. 2 (a) shows X1-X in FIG.
1'line, (b) figure is a perspective sectional view including the section along the X2-X2 'line.

FIG. 3 is an equivalent circuit diagram of the structure shown in FIGS. 1 and 2.

4A and 4B show a first manufacturing process of the MOS transistor according to the first embodiment of the present invention, wherein FIG. 4A is a perspective sectional view and FIG. 4B is a sectional view taken along line X3-X3 'in FIG. 4A. FIG. 3 is a perspective sectional view including a section taken along a line.

FIG. 5 is a perspective sectional view showing a second manufacturing process of the MOS transistor according to the first embodiment of the present invention.

FIG. 6 is a perspective sectional view showing a third manufacturing process of the MOS transistor according to the first embodiment of the present invention.

FIG. 7 is a perspective sectional view showing a fourth manufacturing process of the MOS transistor according to the first embodiment of the present invention.

FIG. 8 is a perspective sectional view showing a fifth manufacturing process of the MOS transistor according to the first embodiment of the present invention.

FIG. 9 is a perspective sectional view showing a sixth manufacturing step of the MOS transistor according to the first embodiment of the present invention.

FIG. 10 is a perspective sectional view showing a seventh manufacturing step of the MOS transistor according to the first embodiment of the present invention.

FIG. 11 is a partial cross-sectional view of the MOS transistor according to the first embodiment of the present invention.

FIG. 12 is a sectional view of a MOS transistor according to the first embodiment of the present invention.

FIG. 13 is a perspective sectional view of an inverter circuit according to a second embodiment of the present invention.

FIG. 14 shows an inverter circuit according to a second embodiment of the present invention, and FIG. 14 (a) is a sectional view taken along line X4-X in FIG.
4'line, (b) figure is X5-X5 'line, (c) figure is X6-
FIG. 6 is a perspective cross-sectional view each including a cross section taken along line X6 ′.

FIG. 15 is an equivalent circuit diagram of the structure shown in FIGS.

FIG. 16 is a diagram showing a state relationship between input and output of an inverter circuit.

FIG. 17 is a perspective sectional view of an inverter circuit according to a second embodiment of the present invention.

FIG. 18 is a perspective sectional view of an inverter circuit using a conventional planar type MOS transistor.

FIG. 19 is a perspective cross-sectional view of an inverter circuit using a conventional MOS transistor having an SGT structure.

FIG. 20 is a perspective sectional view of a NOR circuit according to a third embodiment of the present invention.

FIG. 21 shows a NOR circuit according to a third embodiment of the present invention, and FIG. 21 (a) is a view taken along line X7-X7 ′ in FIG.
Line, (b) figure is X8-X8 'line, (c) figure is X9-X
9'and (d) are perspective sectional views each including a section taken along line X10-X10 '.

22 is an equivalent circuit diagram of the structure shown in FIGS. 20 and 21. FIG.

FIG. 23 is a diagram showing a relationship between inputs and outputs of a NOR circuit.

FIG. 24 is a perspective sectional view of an SRAM according to a fourth embodiment of the present invention.

FIG. 25 shows an SRAM according to a fourth embodiment of the present invention, and FIG. 25 (a) is a view taken along line X11-X1 in FIG.
1'line, (b) figure is X12-X12 'line, (c) figure is X
13-X13 'line, (d) X14-X14' line,
(E) figure is X15-X15 'line, (f) figure is X16-X
FIG. 16 is a perspective cross-sectional view including a cross section taken along line 16 ′.

FIG. 26 shows an SRAM according to a fourth embodiment of the present invention, and FIG. 26 (a) is a view taken along line X17-X1 in FIG.
7'line, (b) figure is X18-X18 'line, (c) figure is X
19-X19 'line, (d) Figure is X20-X20' line,
(E) figure is X21-X21 'line, (f) figure is X22-X
FIG. 22 is a perspective cross-sectional view including a cross section taken along line 22 ′.

FIG. 27 is a plan view of FIG. 24, FIG. 25 (a) to FIG.
The equivalent circuit diagram of the structure shown to (a) thru | or (f).

FIG. 28 is a perspective sectional view of a MOS transistor according to modifications of the first to fourth embodiments of the present invention.

FIG. 29 is a perspective sectional view of a MOS transistor according to modifications of the first to fourth embodiments of the present invention.

FIG. 30 is a sectional view of a conventional planar MOS transistor.

FIG. 31 is a diagram showing a manufacturing process of a conventional planar MOS transistor, and FIGS. 31A to 31E are cross-sectional views sequentially showing first to fifth manufacturing processes of a MOS transistor.

FIG. 32 is a sectional view of a conventional planar MOS transistor.

FIG. 33 is a sectional view of a conventional planar MOS transistor.

FIG. 34 is a perspective sectional view of a conventional MOS transistor having an SGT structure.

FIG. 35 is a sectional view of a conventional MOS transistor having an SGT structure.

[Explanation of symbols]

1 ... Silicon substrates 10, 10-1, 10-2, 12, 12-1 to 12-
4, 110-140 ... N ⁺ semiconductor regions 11, 11-1 to 11-4, 100, 230 ... P-type semiconductor regions 13, 13-1 to 13-4, 160 ... Gate electrodes 14, 14-1 to 14- 4, 150 ... Gate insulating films 15, 15-1, 15-2, 40, 170, 400 ... Insulating films 16, 17 ... Trench 18, 180 ... Interlayer insulating films 19, 220 ... Contact holes 20, 21-3, 190 , 200 ... Electrodes 21, 21-1 to 21-2, 210, 210-1 to 21
0-3 ... Metal wiring layers 30, 30-1, 30-2, 32, 32-1, 32-
2, 310, 320 ... p ⁺ type semiconductor regions 31, 31-1, 31-2, 300 ... N type semiconductor regions 50, 52, 54, 58, 59, 61, 62 ...
Transistors 51, 53, 55, 57, 60 ... pMOS transistors 56, 63, 64 ... Inverter 70 ... SRAM memory cell

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification symbol FI theme code (reference) H01L 27/11 H01L 27/10 381 29/43 29/62 G F term (reference) 4M104 AA01 BB01 CC05 DD26 DD43 FF01 FF27 FF31 GG09 GG10 GG16 HH12 HH14 5F048 AA01 AA07 AA09 AB01 AB04 AC03 BA01 BB05 BB19 BC03 BD07 BE03 BE09 BF16 BG14 5F083 BS03 BS04 BS15 BS16 BS27 BA06 A02 BA06 A02 PRA21 PRAPR PR03 JA21 PR36 PR03 PR01 NA36 PR03 PR01 BB04 BB06 BC06 BC12 BC15 BE07 BF01 BF04 BF43 BG28 BG40 BH05 BH06 BH25 BH30 BH43 BK13 BK17 CE07

Claims (9)

[Claims] 1. A first-conductivity-type first semiconductor region provided in the surface of a semiconductor substrate; a second-conductivity-type second semiconductor region provided in the surface of the first semiconductor region; 2. A third semiconductor region of the first conductivity type provided in the surface of the semiconductor region, and a surface of the semiconductor substrate with a gate insulating film interposed at a depth from the surface of the third semiconductor region to the first semiconductor region. A semiconductor device, comprising: a gate electrode embedded therein; and a part of the first and second semiconductor regions extended to the surface of the semiconductor substrate. 2. A first-conductivity-type first semiconductor region provided in a surface of a semiconductor substrate, a second-conductivity-type second semiconductor region provided in a surface of the first semiconductor region, and the first-conductivity-type second semiconductor region. Two
In the semiconductor substrate surface, the third semiconductor region of the first conductivity type provided in the surface of the semiconductor region, and the gate insulating film interposed between the third semiconductor region surface and the first semiconductor region. An element portion having a channel formed in the second semiconductor region in contact with the gate insulating film, the first and second semiconductor regions being drawn to the surface of the semiconductor substrate, A contact portion electrically isolated from each other by a first insulating film, the third semiconductor region and the gate electrode provided between the element portion and the contact portion, and the first portion in the contact portion, A semiconductor element, comprising: an insulating portion including a second insulating film that electrically isolates the second semiconductor region from the second semiconductor region. 3. The first and second electrodes respectively provided on the first and second semiconductor regions exposed on the surface of the semiconductor substrate in the contact part, and exposed on the surface of the semiconductor substrate in the element part. The semiconductor device according to claim 2, further comprising a third electrode provided on the third semiconductor region. 4. The second insulating film in the insulating portion,
A region of the element portion in contact with the gate electrode is provided so as to have a depth equal to or larger than the gate electrode, and the first semiconductor regions of the element portion and the contact portion are directly adjacent to each other in the region immediately below the second insulating film. The semiconductor element according to claim 2 or 3, wherein the second semiconductor regions are electrically connected to each other. 5. A first semiconductor region of a first conductivity type provided in the surface of a semiconductor substrate, and a second semiconductor region provided in a partial surface region of the first semiconductor region.
A conductive type second semiconductor region; and a first semiconductor provided in a partial surface region of the second semiconductor region.
A conductive third semiconductor region; a gate electrode embedded in the surface of the semiconductor substrate with a gate insulating film at a depth reaching from the surface of the third semiconductor region to the first semiconductor region; An insulating film provided between the first and second semiconductor regions adjacent to each other on the surface of the substrate, and between the third semiconductor region and the gate electrode and the first and second semiconductor regions. Semiconductor device. 6. An interlayer insulating film provided on the semiconductor substrate, and first to third metal wirings provided on the interlayer insulating film and electrically connected to the first to third semiconductor regions, respectively. The semiconductor device according to claim 1, further comprising a layer. 7. A plurality of semiconductor elements according to any one of claims 1 to 6, wherein adjacent semiconductor elements share the gate electrode or any one of the first to third semiconductor regions. Characteristic semiconductor device. 8. A semiconductor device comprising a plurality of semiconductor elements according to claim 1, wherein any one of the first to third semiconductor regions commonly connected between the semiconductor elements is provided adjacent to each other. A semiconductor device characterized by being provided. 9. The semiconductor device according to claim 1, comprising at least two semiconductor devices, wherein the semiconductor device shares the gate electrode, and the first to third semiconductor regions are provided with respect to the gate electrode. The semiconductor device is characterized in that either the second semiconductor region or the third semiconductor region, which are provided symmetrically to each other and are commonly connected to each other, are adjacent to each other in the contact portion.