JP2016048721A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent fluctuation in transistor characteristics due to a substrate floating effect which is caused when a width of a silicon pillar is reduced for improving controllability of a gate.SOLUTION: A semiconductor device 100 comprises: a semiconductor substrate 1; an active region on the semiconductor substrate 1, which is surrounded by an element isolation region 2; a silicon pillar 5 formed on the active region in a pillar shape; first diffusion layer regions 9A, 9B where one of a source and drain which covers at least a part of a bottom face of the pillar-shaped silicon pillar 5 in the active region is made; a second diffusion layer region 16 which covers at least a part of a top face of the pillar-shaped silicon pillar 5 and where the other of the source and drain is made; and a conductive film which covers at least one face of a plurality of lateral faces of the pillar-shaped silicon pillar 5 via the insulation film 10 and where a gate 11 is made. The pillar-shaped silicon pillar 5 includes a first portion 5A and a second portion 5B which are the same in height and different in width.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, vertical transistors have been proposed as transistor miniaturization techniques. A vertical transistor is a transistor that uses, as a channel, a semiconductor pillar extending in a direction perpendicular to the main surface of a semiconductor substrate. Specifically, in the vertical transistor, a semiconductor pillar (base pillar) is provided so as to rise from a semiconductor substrate, and a gate electrode is provided on a side surface of the semiconductor pillar via a gate insulating film.

  One of the source / drain regions is provided below the semiconductor pillar, and the other of the source / drain regions is provided above the semiconductor pillar. This vertical transistor has a smaller occupied area than a conventional planar transistor in which a channel is arranged in parallel with the substrate, and the occupied area of the transistor does not increase even if the channel length (gate length) is increased. Therefore, the short channel effect can be suppressed without increasing the area occupied by the transistor.

  Further, the channel can be completely depleted, and there is an advantage that a good S value (Subthreshold swing value) and a large drain current can be obtained. A vertical transistor has a gate electrode all around the channel, and can effectively control the channel potential with the gate electrode without being influenced by external factors other than the source and drain. it can.

JP 2009-88134 A

  The semiconductor device described in Patent Document 1 does not take into consideration the variation in transistor characteristics due to the floating substrate effect that occurs when the width of the semiconductor pillar (silicon pillar) is reduced in order to improve the controllability of the gate.

  The present invention provides a semiconductor device capable of preventing a change in transistor characteristics due to a substrate floating effect that occurs when the width of a silicon pillar is reduced in order to improve controllability of a gate, and a method for manufacturing the same.

A semiconductor device according to one embodiment of the present invention includes:
A semiconductor substrate;
An active region surrounded by an element isolation region on the semiconductor substrate;
A silicon pillar formed in a columnar shape on the active region and configured to include a channel portion of a transistor;
A first diffusion layer region that covers at least a part of the bottom surface of the pillar-shaped silicon pillar in the active region, and that constitutes one of a source and a drain of the transistor;
A second diffusion layer region covering at least a part of the upper surface of the pillar-shaped silicon pillar and constituting the other of the source and drain of the transistor;
A semiconductor device comprising: a conductive film that covers at least one of a plurality of side surfaces of the pillar-shaped silicon pillar via an insulating film, and constitutes a gate of the transistor;
The columnar silicon pillar includes first and second portions having the same height and different widths.

A method for manufacturing a semiconductor device according to one embodiment of the present invention includes:
Forming an active region surrounded by the element isolation region on the semiconductor substrate of the first conductivity type;
Forming a silicon pillar on the active region so that a part is thicker than the other part;
Forming a gate electrode covering a side surface of the silicon pillar via a gate insulating film;
Using the silicon pillar surrounded by the gate electrode as a mask, ion implantation is performed on the active region, leaving the first bottom surface portion of the silicon pillar corresponding to the portion, and the silicon pillar corresponding to the other portion. Covering the second bottom surface portion of the first conductive layer with a first diffusion layer region of the second conductivity type,
The upper surface of the silicon pillar is covered with a second diffusion layer region of the second conductivity type.

  According to the present invention, it is possible to prevent a change in transistor characteristics due to a substrate floating effect that occurs when the width of the silicon pillar is reduced in order to improve the controllability of the gate.

1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention. 1 is a schematic diagram showing a structure of a semiconductor device according to a first embodiment of the present invention. 1 is a schematic diagram showing a structure of a semiconductor device according to a first embodiment of the present invention. 1 is a schematic diagram showing a structure of a semiconductor device according to a first embodiment of the present invention. 1 is a schematic diagram showing a structure of a semiconductor device according to a first embodiment of the present invention. 1A and 1B are schematic views illustrating the structure of a semiconductor device according to a first embodiment of the present invention, where FIG. 1A is a plan view and FIG. 1B is a cross-sectional view. It is a top view which shows schematic structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a top view which shows schematic structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a top view which shows schematic structure of the semiconductor device which concerns on the 4th Embodiment of this invention. It is a top view which shows schematic structure of the semiconductor device which concerns on the 5th Embodiment of this invention. It is sectional drawing which shows schematic structure of the semiconductor device which concerns on the 6th Embodiment of this invention. It is sectional drawing which shows schematic structure of the semiconductor device which concerns on the 7th Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 2 is a plan view showing the structure of the semiconductor device according to the first embodiment of the present invention, and shows a layout corresponding to FIG. 1.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

(Related technology)
First, in order to clarify the features of the present invention, related techniques related to the present invention will be described.

  In recent years, vertical transistors that have been proposed use semiconductor pillars (silicon pillars) extending in a direction perpendicular to the main surface of a semiconductor substrate as channels. Specifically, in the vertical transistor, a semiconductor pillar is provided so as to rise from a semiconductor substrate, and a gate electrode is provided on a side surface of the semiconductor pillar via a gate insulating film. One of the source / drain regions is provided below the semiconductor pillar, and the other of the source / drain regions is provided above the semiconductor pillar.

  When the miniaturization of a semiconductor device using such a vertical transistor has progressed, the present inventor has found that a change in transistor characteristics due to a substrate floating effect cannot be avoided. This point will be described in detail below.

  Under the semiconductor pillar, one of the source / drain regions exists so as to sandwich the semiconductor pillar. These are partitioned by a semiconductor pillar and an element isolation region. These regions are defined as a first lower source / drain region and a second source / drain region, respectively. Here, as the microfabrication progresses and the width of the semiconductor pillar is reduced, the first lower source / drain region and the second lower source / drain region overlap each other so that the channel (substrate) region and the well are electrically connected. It will be separated. Various phenomena resulting from this are called substrate floating effects. Most of them are undesirable in terms of circuit operation. Therefore, a structure having no substrate floating effect is desired.

(First embodiment of the present invention)
The first embodiment of the present invention is characterized in that the semiconductor pillar (silicon pillar) is T-shaped in plan view. As a result, the lower diffusion layer is divided into three. Specifically, a well power supply region is arranged in addition to the first lower source / drain region and the second lower source / drain region. The substrate floating effect can be prevented by the configuration of the present invention. For this purpose, the width of the semiconductor pillar defining the well power feeding region is designed to be larger than the lateral extension of the lower diffusion layer (the first lower source / drain region and the second lower source / drain region). It is necessary. In this case, the electrical connection between the substrate and the channel region is maintained regardless of the width of the semiconductor pillar that defines the lower diffusion layer (the first lower source / drain region and the second lower source / drain region).

  The schematic configuration of the semiconductor device 100 according to the first embodiment of the present invention will be described below with reference to FIGS. 1 to 6.

  First, a circuit diagram of the semiconductor device 100 in FIG. 1 is referred to.

  This circuit is a so-called inverter circuit, but is characterized in that at least the transistor 50B has a structure as shown in FIG.

  Reference is now made to the structural diagrams of FIGS.

  The semiconductor device 50B according to the first embodiment is surrounded by an element isolation region (STI: Shallow Trench Isolation) 2 and an element isolation region 2 in a semiconductor substrate 1 (hereinafter referred to as a silicon substrate 1) made of silicon single crystal. And an active region made of the silicon substrate 1.

  The semiconductor device 50B constitutes a vertical transistor, and uses a columnar silicon pillar 5 extending in a direction perpendicular to a main surface of a semiconductor substrate (hereinafter referred to as a silicon substrate 1) as a channel. Specifically, a columnar silicon pillar 5 is provided so as to rise from the silicon substrate 1, and a gate electrode 11 is provided on a side surface of the silicon pillar 5 via a gate insulating film 10.

  Under the silicon pillar 5, a first lower diffusion layer 9A (first source / drain region) and a second lower diffusion layer 9B (second source / drain region) are provided. On the other hand, an upper diffusion layer 16 (source / drain region) is provided above the silicon pillar 5.

  In the silicon pillar 5, the silicon pillar 5 sandwiched between the upper diffusion layer 16, the first lower diffusion layer 9A, and the second lower diffusion layer 9B constitutes a channel region. Further, the silicon pillar 5 is configured to sandwich the gate insulating film 10 between the silicon pillar 5 and the gate electrode 11.

  Under such a configuration, as shown in FIG. 6, in the semiconductor device 100 according to the first embodiment, the silicon pillar 5 has the same height in the first direction indicated by AA ′ in the drawing. The first portion 5A and the second portion 5B are different from each other. Thus, as shown in FIG. 6A, the silicon pillar 5 is T-shaped in a plan view.

  As shown in FIGS. 6A and 6B, the width of the second portion 5B is larger than the width of the first portion 5A, and the bottom surface of the first portion 5A is the first lower diffusion layer 9A and the second lower portion. The diffusion layer 9B is completely covered. On the other hand, the bottom surface of the second portion 5B includes a region covered with the first lower diffusion layer 9A and the second lower diffusion layer 9B and a region not covered. Here, the region that is not covered by the first lower diffusion layer 9 </ b> A and the second lower diffusion layer 9 </ b> B corresponds to the well 60 formed on the semiconductor substrate 1. A well power supply region 61 for supplying power to the well is provided adjacent to the well 60.

  Thus, by providing the well 60 which is a region not completely covered by the first lower diffusion layer 9A and the second lower diffusion layer 9B, the first lower diffusion layer 9A and the second lower diffusion layer 9B are provided. By overlapping, the channel portion of the silicon pillar 5 and the well 60 are electrically separated to prevent the silicon pillar 5 from entering a floating state.

  As shown in FIG. 6B, there is no element isolation region between the well power supply region 61 and the silicon pillar 5 constituting the transistor. Further, as shown in FIG. 6A, a well power supply contact 62 is arranged in the well power supply region 61. Lower diffusion layer contacts 63 are disposed in the first lower diffusion layer 9A and the second lower diffusion layer 9B, respectively. An upper diffusion layer contact 64 is disposed in the upper diffusion layer 16. Further, a gate contact is disposed on the gate electrode 11.

  Here, as shown in FIG. 6A, the width of the second portion 5B of the silicon pillar 5 is larger than the lateral width of the first lower diffusion layer 9A and the second lower diffusion layer 9B. Thus, by setting the width of the second portion 5B to be larger than the lateral width of B of the first lower diffusion layer 9A and the second lower diffusion layer 9B, the channel portion and the well 60 of the silicon pillar 5 are formed. To maintain electrical connection with.

  As described above, in the semiconductor device 50B according to the first embodiment, the silicon pillar 5 can be prevented from being in a floating state, and the substrate floating effect can be prevented. For this purpose, the width of the silicon pillar 5 defining the well power supply region 61 is designed to be larger than the lateral extension of the first lower diffusion layer 9A and the second lower diffusion layer 9B, that is, the channel region. It is necessary that at least a part of the lower region of 5 is not covered by the lower diffusion layer region. In this case, even if the width of the silicon pillar 5A partitioning the first lower diffusion layer 9A and the second lower diffusion layer 9B is small and the region is covered with the diffusion layer region, in FIG. The electrical connection between the silicon substrate 1 and the channel portion of the silicon pillar 5 is maintained.

Here, the requirements for well power supply will be described.
(Requirements): The following (1) and (2) must be satisfied simultaneously.
(1) A neutral region exists in the silicon pillar 5B. Neutral region in the silicon pillar = width of the silicon pillar 5B− (well feeding side under-gate depletion layer width + lower diffusion layer side under-gate depletion layer width)> 0
(2) Lower neutral region exists Lower neutral region = width of silicon pillar 5B− (lower diffusion layer lateral extension + junction depletion layer width)> 0

Ｓ／Ｄ側ゲート下空乏層幅

・下部Ｓ／Ｄ空乏層幅

Here, the requirements for well power supply are described using NMOS as an example (in PMOS, the sign is reversed as appropriate).
Symbol Definition-V _Top Upper S / D Potential-V _Bottom Lower S / D Potential-V _Body Substrate Potential-Φ _Bottom Lower S / D Fermi Potential-Φ _Body Substrate Fermi Potential-N _Bottom Lower S / D Impurity Concentration-N _Body Substrate impurity concentration-Dielectric constant of ε _Si substrate-q Elementary charge (requirement for well power supply)
Depletion layer width under the gate of the well feeding side

Depletion layer width under S / D side gate

・ Lower S / D depletion layer width

More preferably, for example-neutral region in silicon pillar> silicon pillar width / 3
-Lower neutral region> Silicon pillar width / 2
And

  Here, in FIGS. 2 to 6, only the structure of the transistor 50B in FIG. 1 has been described, but in FIG. 29, the transistor 50A is further added. The structure of the transistor 50A is similar to that of the transistor 50B described above.

  Specifically, the transistor 50B is an NMOS transistor and is formed on the P well (or P sub). The body and source are connected to the GND terminal, the gate is connected to the input terminal, and the drain is connected to the output terminal. On the other hand, the transistor 50A is formed on an N well formed in the P sub. The body and source are connected to the power supply terminal, the gate is connected to the input terminal, and the drain is connected to the output terminal.

(Second embodiment of the present invention)
The schematic configuration of the semiconductor device 700 according to the second embodiment of the present invention will be described below with reference to FIG.

  In the first embodiment of the present invention, as shown in FIG. 6, the well power supply region 61 is disposed adjacent to the transistor. However, in the second embodiment of the present invention, the well power supply region 71 is disposed. Is arranged at a position away from the transistor.

  Specifically, in the second embodiment of the present invention, as shown in FIG. 7, the body feeding portion 70 required in the vertical structure MOS transistor is replaced with the body portion of the transistor and the gate oxide film and the gate surrounding it. It is characterized by being formed in a self-aligned manner by a pattern. Specifically, the condition is that the width of the region surrounded by the gate is a predetermined value or more.

(Third embodiment of the present invention)
The schematic configuration of the semiconductor device 800 according to the third embodiment of the present invention will be described below with reference to FIG.

  In the second embodiment of the present invention, as shown in FIG. 7, the body power feeding unit 70 is arranged at the end of the transistor. However, in the third embodiment of the present invention, as shown in FIG. The body power supply unit 70 is arranged at the center of the transistor.

  Thus, the body power feeding unit 70 does not have to be at the end, and may be arranged at the center. In this layout, the left and right gates may be two different transistors as separate signals with the body power feeding unit 70 interposed therebetween. Further, the well power supply unit 71 may be adjacent to the body power supply unit 70 in a range that does not short-circuit the diffusion layer 72.

(Fourth embodiment of the present invention)
The schematic configuration of a semiconductor device 900 according to the fourth embodiment of the present invention will be described below with reference to FIG.

  In the second embodiment of the present invention, as shown in FIG. 7, the lower diffusion layer of the transistor is arranged in two places. In the fourth embodiment of the present invention, as shown in FIG. One of the drains (substrate side) can be provided at one place. Further, the well power supply unit 71 may be adjacent to the body power supply unit 70 in a range that does not short-circuit the diffusion layer.

(Fifth embodiment of the present invention)
The schematic configuration of the semiconductor device 1000 according to the fifth embodiment of the present invention will be described below with reference to FIG.

  In the third embodiment of the present invention, as shown in FIG. 8, the body power feeding unit 70 is arranged at the center of the transistor. The body power feeding unit 70 does not need to be at the end, and may be disposed at the center.

  Unlike FIG. 8, the fifth embodiment of the present invention is applied to one transistor. In the fifth embodiment of the present invention, the width of the body power supply unit 70 is smaller than the width of the body power supply unit 70 shown in FIG.

(Sixth embodiment of the present invention)
In the first embodiment of the present invention, the case where the present invention is applied to a MOS transistor has been described. However, in the sixth embodiment of the present invention, the present invention is applied to a bipolar transistor.

  In the sixth embodiment of the present invention, as shown in FIG. 11, a junction bipolar transistor is formed on the same chip by separating a well (N-well) 81 from other transistors, and the junction bipolar transistor is formed. And a chip having both MOS transistors can be formed. Here, FIG. 11 corresponds to FIG.

  Specifically, as shown in FIG. 11, a semiconductor device 1100 includes a silicon substrate (p-substrate) 80, a well (N-well) 81, a collector (P + Collector) 82, a base (N-Base) 83, and a base contact. (N + Base Contact) 84 and emitter (P + Emitter) 85.

  Thus, in order to apply the present invention to a bipolar transistor, in the case of a PNP type bipolar transistor, it is formed in a well (N-well) 81 and formed simultaneously with a vertical MOS transistor. In this case, a dedicated process is not necessary.

  However, it is necessary to overlap the first lower diffusion layer 9A and the second lower diffusion layer 9B (the first lower S / D and the second lower S / D).

  According to the sixth embodiment of the present invention, characteristics as a bipolar transistor can be improved. This is because most of the minority carriers injected from the emitter 85 can reach the collector 82 and the base transport efficiency can be improved.

  The bipolar transistor shown in FIG. 11 is a PNP junction bipolar, but can also be an NPN type by inverting the polarity.

(Seventh embodiment of the present invention)
In the seventh embodiment of the present invention, the present invention is applied to a bipolar transistor as in the sixth embodiment.

  In the seventh embodiment of the present invention, as shown in FIG. 12, by separating the well (N-well) 91 from other transistors, a junction bipolar transistor is formed on the same chip, and the junction bipolar transistor is formed. And a chip having both MOS transistors can be formed. The depth of the well 91 does not matter. Here, FIG. 12 corresponds to FIG.

  Specifically, as shown in FIG. 12, the semiconductor device 1200 includes a silicon substrate (p-substrate) 90, a well (N-well) 91, a collector (P + Collector) 92, a base (N-Base) 93, and a base contact. (N + Base Contact) 94 and emitter (P + Emitter) 95.

  Moreover, although it is a PNP junction type bipolar shown in FIG. 12, it can also be made an NPN type by reversing the polarity. According to the seventh embodiment of the present invention, the base resistance can be reduced.

(Method for Manufacturing Semiconductor Device According to First Embodiment)
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described.

  In the method for manufacturing a semiconductor device according to the first embodiment of the present invention, the bottom surface of the silicon pillar of the vertical transistor is completely covered with the diffusion layer by ion implantation (and annealing) by pillar self-alignment when the bottom surface side diffusion layer is formed. In order to prevent the silicon pillar itself from floating completely, a feeding path for the body or channel is secured. As a means for that purpose, a silicon pillar having a width that does not completely cover the diffusion layer is formed.

  The method for manufacturing the semiconductor device 100 according to the first embodiment will be described in detail below with reference to FIGS.

  First, as shown in FIGS. 13 and 14, a groove 22 is formed in the silicon substrate 1 by using a photolithography method and a dry etching method. The depth of the groove 22 is, for example, 250 nm.

  Next, an insulating film 24 made of a silicon nitride film or a silicon oxide film is deposited on the entire surface of the silicon substrate 1 by a CVD (Chemical Vapor Deposition) method so as to fill the inside of the trench 22. Thereafter, the unnecessary insulating film 24 formed on the upper surface of the silicon substrate 1 is removed by a CMP (Chemical Mechanical Polishing) method, and the insulating film 24 is left only inside the trench 22, thereby forming the STI 2 serving as an element isolation region. Form. As a result, an active region 1a surrounded by STI2 is formed.

  Next, as shown in FIGS. 15 to 17, an insulating film 3 made of a silicon oxide film is formed to a thickness of 2 nm on the upper surface of the silicon substrate 1 by a CVD method, and then a mask film made of a silicon nitride film. 4 is formed to be 120 nm thick.

  Next, a photoresist mask 7 having a pattern of the pillar groove forming region A is formed on the upper surface of the mask film 4 by photolithography. The pillar groove formation region A is a region before the silicon pillar 5 is formed, but the region where the silicon pillar 5 is dug after the formation is also referred to in the same manner. The photoresist mask 7 may include a hard mask such as an amorphous carbon film.

  Next, the pattern is transferred to the mask film 4 and the insulating film 3 by anisotropic dry etching using the photoresist mask 7. As a result, the upper surface of the silicon substrate 1 and the upper surface of the STI 2 are exposed inside the patterned opening (corresponding to the pillar groove forming region A). Thereafter, the photoresist mask 7 is removed.

  Next, as shown in FIGS. 18 to 20, the exposed silicon substrate 1 and STI 2 are dug down to a depth of 150 nm by anisotropic dry etching using the mask film 4 as a mask. One silicon pillar 5 and two pillars 6 (6a, 6b) are formed.

  The silicon pillar 5 is formed so as to protrude upward from the upper surface of the dug down silicon substrate 1, and the pillar 6 is formed so as to protrude upward from the upper surface of the dug down STI 2. Thereby, the silicon pillar 5 is formed in a rectangle with a width in the X direction of 45 nm.

  As shown in FIG. 20, two pillars 6 are formed so as to come into contact with both side surfaces of the silicon pillar 5 in the Y direction.

  Next, as shown in FIGS. 21 to 23, an oxide film (not shown) having a thickness of 5 nm is formed on the side surface of the silicon pillar 5 by thermal oxidation. Further, a silicon nitride film is formed by CVD to a thickness of 20 nm, and then the entire surface is etched back to form a sidewall film (not shown) on the side surfaces of the silicon pillar 5, pillar 6, and mask film 4. Form.

  Next, an insulating film 8 made of a silicon oxide film having a thickness of 30 nm is formed in the active region 1a exposed around the silicon pillar 5 by thermal oxidation. At this time, the side surface of the silicon pillar 5 is not oxidized because it is covered with the sidewall film made of the silicon nitride film.

  Next, the lower diffusion layer 9 (9A, 9B) is formed below the insulating film 8 by ion implantation. Here, the first lower diffusion layer 9 </ b> A and the second lower diffusion layer 9 </ b> B are separated by the silicon pillar 5. In the ion implantation, N and P ions are implanted using a mask (resist) (not shown). As an impurity to be implanted, arsenic can be used if an N-type transistor is used.

  Next, the sidewall film and the oxide film formed on the side surfaces of the silicon pillar 5 and the pillar 6 are removed by a dry etching method or a wet etching method. Next, a gate insulating film 10 (10A, 10B) made of a 3 nm thick silicon oxide film is formed on the side surface of the silicon pillar 5 by thermal oxidation.

  Next, a 20 nm thick polysilicon film (polycrystalline silicon film) serving as a gate electrode is formed on the entire surface of the silicon substrate 1 by the CVD method, and then the entire surface is etched back. By this process, the gate electrode 11a (11aA, 11aB) is formed on the side surface of the silicon pillar 5, and the dummy gate electrode 11b is formed on the side surface of the pillar 6. Here, as shown in FIG. 19, the dummy gate electrode 11 b on the side surface of the pillar 6 is connected to the gate electrode 11 a on the side surface of the silicon pillar 5. When the gate electrode wiring 11 is formed on the side surfaces of the silicon pillar 5 and the pillar 6, the gate electrode wiring 11 (not shown) is also formed on the side surface of the STI 2.

  Next, as shown in FIGS. 24 to 26, a first interlayer insulating film 12 made of a silicon oxide film is formed by a CVD method so as to embed the silicon pillar 5 and the pillar 6. Next, the first interlayer insulating film 12 is planarized by the CMP method so that the mask film 4 is exposed, and then the mask film 13 made of a silicon oxide film is formed to a thickness of 50 nm by the CVD method.

  Next, a photoresist mask 26 is formed on the upper surface of the mask film 13 by photolithography. The photoresist mask 26 has an opening 28 exposing only the mask film 13 above the silicon pillar 5. The mask film 13 above the first active region 1 aA, the second active region 1 aB, and the STI 2. Is covered with a photoresist mask 26.

  Next, as shown in FIG. 27, the exposed mask film 13 is then removed using anisotropic dry etching. The mask film 4 above the silicon pillar 5 is exposed in the opening 14 from which the mask film 13 has been removed.

  Next, the exposed mask film 4 is removed by anisotropic dry etching, and further, the insulating film 3 which is the base of the removed mask film 4 is removed, so that an opening is formed above the silicon pillar 5. 15 is formed. The upper surface of the silicon pillar 5 is exposed at the bottom surface of the opening 15, and a part of the gate electrode 11 a is exposed at the side surface.

  Next, as shown in FIG. 28 (26), an insulating film (not shown) made of a silicon oxide film is formed on the inner wall of the opening 15 by thermal oxidation.

  Next, after forming a silicon nitride film having a thickness of 10 nm by CVD, etch back is performed to form a sidewall insulating film 18 made of a silicon nitride film on the inner wall of the opening 15. When the sidewall insulating film 18 is formed, an insulating film (not shown) formed on the upper surface of the silicon pillar 5 is removed to expose the upper surface of the silicon pillar 5. The sidewall insulating film 18 plays a role of ensuring insulation between the conductor layer to be formed later and the gate electrode 11a.

  Next, a conductor layer 16 made of silicon is grown on the upper surface of the silicon pillar 5 by using a selective epitaxial growth method. At this time, the position of the upper surface of the conductor layer 16 is set lower than the upper surface of the first interlayer insulating film 12. Thereafter, when an N-type transistor is formed, arsenic or the like is ion-implanted to make the conductor layer 16 electrically contact with the upper portion of the silicon pillar 5 as an n-type conductor. In this way, the semiconductor device 50B shown in FIG. 1 is completed.

  As described above, in the method for manufacturing the semiconductor device 100 according to the first embodiment of the present invention, the bottom surface of the silicon pillar of the vertical transistor is ion-implanted (and annealed) by pillar self-alignment when the bottom-side diffusion layer is formed. Thus, the body or channel feeding path is secured so that the silicon pillar itself is not completely floated by being completely covered by the diffusion layer. As a means for that purpose, a silicon pillar having a width that does not completely cover the diffusion layer is formed.

  More specifically, an active region surrounded by an element isolation region is formed on a semiconductor substrate of the first conductivity type, and a silicon pillar is formed on the active region so that a part is thicker than the other part. A gate electrode that covers a side surface of the pillar through a gate insulating film is formed, and the silicon pillar surrounded by the gate electrode is used as a mask to perform ion implantation on the active region, and the first bottom surface of the silicon pillar corresponding to a part thereof The second bottom surface portion of the silicon pillar corresponding to the other portion is covered with the first diffusion layer region of the second conductivity type, leaving the portion, and the upper surface of the silicon pillar is covered with the second diffusion layer region of the second conductivity type. It is characterized by covering. Here, the ion implantation is performed by a self-alignment method using a silicon pillar as a mask.

  The first bottom surface portion of the silicon pillar has a first width that is not completely covered by the first diffusion layer region, and the second bottom surface portion of the silicon pillar is completely formed by the first diffusion layer region. The second width is such that it is covered. Here, the first width is set larger than the second width. By having the first width such that the first bottom surface portion of the silicon pillar is not completely covered by the first diffusion layer region, the silicon pillar is prevented from being in a floating state.

  As described above, according to the embodiment of the present invention, the required area of the semiconductor device can be reduced and the substrate floating effect can be prevented.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in FIG. 3, the silicon pillar 5 is completely covered by the first lower diffusion layer 9A and the second lower diffusion layer 9B, but is not completely covered by the diffusion layer. However, there may be a case where power supply from the well is insufficient due to the depletion layers generated by the first lower diffusion layer 9A and the second lower diffusion layer 9B. Such a structure is also included in the present invention.

1 Silicon substrate 2 Element isolation region (STI)
1a active region 1aA first active region 1aB second active region 5 silicon pillar 6 pillar 8 insulating film 9A first lower diffusion layer 9B second lower diffusion layer 10A first gate insulating film 10B second gate insulating film 11a gate electrode 11b dummy Gate electrode 12 First interlayer insulating film 16 Upper diffusion layer 18 Side wall insulating film 50A First transistor 50B Second transistor 100 Semiconductor device

Claims (20)

A semiconductor substrate;
An active region surrounded by an element isolation region on the semiconductor substrate;
A silicon pillar formed in a columnar shape on the active region and configured to include a channel portion of a transistor;
A first diffusion layer region that covers at least a part of the bottom surface of the pillar-shaped silicon pillar in the active region, and that constitutes one of a source and a drain of the transistor;
A second diffusion layer region covering at least a part of the upper surface of the pillar-shaped silicon pillar and constituting the other of the source and drain of the transistor;
A semiconductor device comprising: a conductive film that covers at least one of a plurality of side surfaces of the pillar-shaped silicon pillar via an insulating film, and constitutes a gate of the transistor;
The columnar silicon pillar includes first and second portions having the same height and different widths.   The width of the second portion is larger than the width of the first portion, the bottom surface of the first portion is covered with the first diffusion layer region, and the bottom surface of the second portion is covered with the first diffusion layer region. The semiconductor device according to claim 1, further comprising a region and a region that is not covered.   3. The semiconductor device according to claim 2, wherein the region not covered with the first diffusion layer region corresponds to a well formed on the semiconductor substrate.   The semiconductor device according to claim 3, wherein a well power feeding region is provided adjacent to the well.   The semiconductor device according to claim 1, wherein the columnar silicon pillar has a T shape. The first diffusion layer region is partitioned into a first lower diffusion layer region and a second lower diffusion layer region,
The region that is not covered with the first diffusion layer region has the columnar shape because the channel portion and the well are electrically separated by overlapping the first lower diffusion layer region and the second lower diffusion layer region. 6. The semiconductor device according to claim 3, wherein the silicon pillar is prevented from entering a floating state.   7. The semiconductor device according to claim 4, wherein an element isolation region does not exist between the well power supply region and the transistor.   8. The semiconductor device according to claim 1, wherein a width of the second portion of the columnar silicon pillar is larger than a width in a lateral direction of the first diffusion layer region. 9.   9. The electrical connection between the channel portion and the well is maintained by setting the width of the second portion to be larger than the lateral width of the first diffusion layer region. Semiconductor device. Forming an active region surrounded by the element isolation region on the semiconductor substrate of the first conductivity type;
Forming a silicon pillar on the active region so that a part is thicker than the other part;
Forming a gate electrode covering a side surface of the silicon pillar via a gate insulating film;
Using the silicon pillar surrounded by the gate electrode as a mask, ion implantation is performed on the active region, leaving the first bottom surface portion of the silicon pillar corresponding to the portion, and the silicon pillar corresponding to the other portion. Covering the second bottom surface portion of the first conductive layer with a first diffusion layer region of the second conductivity type,
A method of manufacturing a semiconductor device, wherein an upper surface of the silicon pillar is covered with a second diffusion layer region of the second conductivity type.   The method of manufacturing a semiconductor device according to claim 10, wherein the ion implantation is performed by a self-alignment method using the silicon pillar as a mask. The first bottom surface portion of the silicon pillar has a first width that is not completely covered by the first diffusion layer region;
12. The method of manufacturing a semiconductor device according to claim 10, wherein the second bottom surface portion of the silicon pillar has a second width so as to be completely covered by the first diffusion layer region.   The method of manufacturing a semiconductor device according to claim 12, wherein the first width is larger than the second width.   Having the first width such that the first bottom surface portion of the silicon pillar is not completely covered by the first diffusion layer region prevents the silicon pillar from entering a floating state. A method for manufacturing a semiconductor device according to claim 11.   15. The method of manufacturing a semiconductor device according to claim 10, wherein a well on the semiconductor substrate is formed in the first bottom surface portion of the silicon pillar.   16. The method of manufacturing a semiconductor device according to claim 15, wherein a well power supply region is formed adjacent to the well.   17. The method of manufacturing a semiconductor device according to claim 16, wherein an element isolation region does not exist between the well power supply region and the silicon pillar.   The method of manufacturing a semiconductor device according to claim 10, wherein the silicon pillar is formed in a T shape in a plan view.   19. The method of manufacturing a semiconductor device according to claim 10, wherein the first width of the silicon pillar is larger than a lateral width of the first diffusion layer region.   The electrical connection between the silicon pillar and the well is maintained by setting the first width of the silicon pillar to be larger than a lateral width of the first diffusion layer region. Item 20. The method for manufacturing a semiconductor device according to any one of Items 15 to 19.

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