JP3957774B2 - Semiconductor device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor device, and more particularly to a highly reliable semiconductor device in which the influence of photons generated at the drains of MOS transistors on other MOS transistors is reduced as much as possible.
[0002]
[Prior art]
When a voltage is applied to the PN junction, photons are generated. In an integrated circuit in which a plurality of semiconductor elements are formed on the same semiconductor substrate surface, a structure such as LDD (Lightly Doped Drain) has been proposed to prevent the generated photons from affecting adjacent semiconductor elements as much as possible. That wasn't always enough. The generation of such photons leads to an increase in subthreshold current of surrounding MOS transistors. In particular, in a nonvolatile semiconductor memory device (for example, an EEPROM) having a ring oscillator and an internal booster circuit, a large amount of photons are generated in the ring oscillator or booster circuit, and this causes a through current when other peripheral circuits are not operating. It led to an increase.
[0003]
[Problems to be solved by the invention]
As described above, in the conventional semiconductor device, the generation of photons in the drain of the MOS transistor is inevitable, and the generated photons may adversely affect the surrounding semiconductor elements.
[0004]
The present invention has been made in consideration of the above circumstances, and its purpose is not to suppress the generation of photons, but rather to emit and block the generated photons to the back side of the substrate, thereby absorbing and shielding them. An object of the present invention is to provide a semiconductor device in which the influence of photons on adjacent semiconductor elements is reduced as much as possible.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, one embodiment of a semiconductor device of the present invention is a semiconductor device including a semiconductor element formed over a semiconductor substrate, wherein the semiconductor element is a partial region of a semiconductor pillar protruding from the semiconductor substrate. A drain is formed on the surface of the semiconductor substrate, a source is formed on the surface of the semiconductor substrate, a gate electrode is surrounded by an insulating film formed with a substantially constant thickness around the semiconductor pillar, and a photon is formed around the gate electrode. The shielding member is continuously arranged from the semiconductor column bottom position to the top position so as to surround the gate electrode.
One embodiment of the semiconductor device of the present invention is a semiconductor device including a semiconductor element formed over a semiconductor substrate, wherein the semiconductor element has a drain in a partial region of a semiconductor pillar protruding from the semiconductor substrate. A source is formed on the surface of the semiconductor substrate, a gate electrode is surrounded by an insulating film around the semiconductor pillar, and a member for shielding photons is disposed around the gate electrode. It is electrically connected and used as a lead-out electrode of the source.
[0010]
[Action]
According to the present invention, even when photons are generated in a semiconductor element, the photon shielding member disposed around the semiconductor element shields the photons. A low power consumption, highly integrated semiconductor integrated circuit can be formed.
[0011]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view of a vertical MOS transistor according to a first embodiment of the present invention. A vertical MOS transistor formed on a semiconductor substrate has an SGT (Surrounding Gate Transistor) structure. The P-type semiconductor substrate 30 made of silicon single crystal has a protruding portion 31 (silicon pillar) made of the same member, and the side wall of the protruding portion 31 is covered with a gate insulating film 32 made of an oxide film. Further, the protruding portion 31 is surrounded by a gate electrode 33 made of aluminum with a gate insulating film 31 interposed therebetween. An N-type impurity diffusion region (source) 34 is formed on the surface of the semiconductor substrate 31 near the lower portion of the protrusion 31, and an N-type impurity diffusion region (drain) 35 is formed on the upper portion of the protrusion 31. Yes.
[0012]
An example of a specific shape of the SGT is as follows. The protrusion has a width of 0.5 μm and a height of 1.0 μm, the gate insulating film 32 has a thickness of 10 nm, and the gate electrode has a thickness of 200 nm. In the semiconductor substrate, boron is diffused at a low concentration, and arsenic is diffused at a high concentration in the source 34 and the drain 35.
[0013]
When operating the MOS transistor configured as described above, a power supply voltage of, for example, about 5 V may be applied to the drain 35. At this time, photons are generated at the PN junction of the drain. The generated photons are emitted to the substrate 30 side through a path indicated by an arrow 37 while being reflected at the interface between the gate insulating film 32 and the protruding portion 31. As described above, the protruding portion 31 made of silicon and the insulating film 32 around it serve as a waveguide and propagate photons in the substrate direction (downward in the figure). As a result, the influence of photons on adjacent semiconductor elements is reduced to some extent. However, reflection at the interface between the silicon and the oxide film is not always sufficient, and photons may be transmitted depending on the incident angle of photons. Here, if the gate electrode 33 is made of polysilicon as in the prior art, this photon is easily transmitted, and it is not possible to prevent the photon from reaching an adjacent semiconductor element. In the present invention, since the gate electrode 33 is made of aluminum that absorbs and shields photons, the photons that have passed through the gate insulating film 32 are absorbed and shielded by, for example, the portions 38 and 39. As a result, it is possible to almost completely prevent the photons generated in the drain 35 from reaching the adjacent element.
[0014]
In the SGT structure as described above, the current / voltage characteristics are superior to that of the planar transistor. For example, FIG. 14 shows a subthreshold swing, but with SGT, a value that is almost ideally close to about 60 mV / decade is obtained, which is smaller than that of a normal planar transistor. VG represents the voltage applied to the gate, I represents the current flowing between the source and drain, and FIG. 14 represents the relationship between VG and I by a semilogarithmic graph. This is because, as shown in FIG. 15, the size of the SGT is reduced. For example, when the diameter of the silicon pillar is 1 μm or less, the inside of the silicon pillar is completely depleted by the depletion layer 95. As a result, the SGT has a sub-threshold swing smaller than that of the planar transistor, so that not only the cutoff characteristic is improved, but also the substrate bias effect is lost.
[0015]
The characteristics of this SGT are similar to the transistor characteristics of an SOI (Silicon-on-Insulator) structure. However, the SOI structure requires means for alleviating the body effect. That is, in the case of a body contact for absorbing holes generated by impact ionization, for example, an N-channel MOS transistor, a contact with a P-type high concentration region must be provided. This hindered miniaturization of the SOI structure transistor. However, in the SGT structure, the substrate serves as a body contact, and the generated holes are absorbed by the substrate. In other words, the SGT structure has characteristics of an SOI structure transistor, and at the same time does not require a body contact and is suitable for miniaturization.
[0016]
Such an SGT structure is more resistant to photons than SOI. In the SOI structure, the generated photons propagate laterally through the silicon film on the insulating film (insulator), and the photons generated from one transistor propagate to the surrounding transistors, affecting the current and voltage characteristics. This is because there is a problem similar to that of a normal planar transistor.
[0017]
In the above example, the gate electrode 33 is made of aluminum. However, a conductive material containing a metal such as tungsten, titanium, tungsten silicide, or titanium silicide, which is a member that absorbs photons, may be used.
[0018]
(Second embodiment)
FIG. 2 is a cross-sectional view of a vertical MOS transistor according to the second embodiment of the present invention. Similar to the first embodiment, the vertical MOS transistor formed on the semiconductor substrate has an SGT structure. The P-type semiconductor substrate 40 made of silicon single crystal has a protrusion 41 (silicon pillar) made of the same member, and the side wall of the protrusion 41 is covered with a gate insulating film 42 made of an oxide film. Further, the protruding portion 41 is surrounded by a gate electrode 43 made of polysilicon doped with an impurity at a high concentration via a gate insulating film 41. An N-type impurity diffusion region (source) 44 is formed on the surface of the semiconductor substrate 40 in the vicinity of the lower portion of the protrusion 41, and an N-type impurity diffusion region (drain) 45 is formed on the upper portion of the protrusion 41. Yes. Further, a photon absorption member 46 is formed so as to surround the drain electrode 43. As shown in FIG. 2, the member 46 is inserted between adjacent SGTs.
[0019]
When the MOS transistor configured as described above is operated, photons are generated at the PN junction of the drain. The generated photons are emitted to the substrate 40 side through a path indicated by an arrow 47 while being reflected at the interface between the gate insulating film 42 and the protruding portion 41. Thus, as in the first embodiment, the protrusion 41 made of silicon and the insulating film 42 around it serve as a waveguide to propagate photons in the substrate direction (downward in the figure). As a result, the influence of photons on adjacent semiconductor elements is reduced to some extent. Here, the reflection at the interface between the silicon and the oxide film is not always sufficient, and depending on the incident angle of the photon, the photon is transmitted, but the member 46 is made of aluminum that absorbs the photon. Photons that have passed through the gate insulating film 42 are absorbed by the member 46. As a result, the photons generated in the drain 45 can be almost completely prevented from reaching the adjacent elements.
[0020]
Further, in the second embodiment, the gate electrode 43 has an advantage that polysilicon can be used as usual.
In the above-described example, the shielding member 46 is made of aluminum. However, as in the first embodiment, a material such as tungsten or titanium that is a member that absorbs photons may be used.
[0021]
(Third embodiment)
FIG. 3 is a cross-sectional view of a vertical MOS transistor according to a third embodiment of the present invention. The same parts as those in the second embodiment are denoted by the same reference numerals, and detailed description of the structure is omitted. In the third embodiment, as described above, the photon shielding member 46 is made of a conductive member such as aluminum, tungsten, or titanium, and is electrically connected to the source 44. For this reason, the photon shielding member 46 can be used as a source lead-out electrode. This configuration has an effect of facilitating contact with the upper layer wiring.
[0022]
(Fourth embodiment)
4 to 8 show a fourth embodiment of the present invention. The fourth embodiment is an example in which a vertical CMOS inverter is formed.
[0023]
4 is a plan view of the CMOS inverter, FIG. 5 is a sectional view taken along the line 5a in FIG. 4, FIG. 6 is a sectional view taken along the line 5b in FIG. 4, and FIG. The P-type semiconductor substrate 1 is formed with a first protrusion 10 and a second protrusion 11 formed on a part of the first protrusion 10. A P-type high concentration diffusion region 2 is formed in the region corresponding to the “root” of the first protrusion 10 and the surface region of the substrate 1. The protrusion 10 is composed of a high-concentration P-type diffusion region, an N-type diffusion region 3, a high-concentration P-type diffusion region 4, and a high-concentration N-type diffusion region 5 in order from the bottom. The protrusion 11 is composed of a high concentration N-type diffusion region 5, a P-type diffusion region 6, and a high concentration N-type diffusion region 7 in order from the bottom. An aluminum gate electrode 91 is formed on the side wall of the first protrusion 10 via an insulating film 81, and an aluminum gate electrode 92 is formed on the side wall of the second protrusion 11 via an insulating film 82. An electrode 15 is formed in contact with the high-concentration N type diffusion region 5 in a region where the second protrusion 11 on the upper surface of the first protrusion 10 is not formed. Further, an electrode 17 is formed on the upper surface of the second protrusion 11 so as to be in contact with the high concentration diffusion region 7. The gate electrodes 92 and 91 are integrally formed and connected to the electrode 14 at a position away from the above structure. Similarly, the N-type high concentration diffusion region 2 is connected to the electrode 16 at a position away from the structure. The structure as described above is covered with an interlayer insulating film 12.
[0024]
FIG. 8 is an equivalent circuit of the above-mentioned concept or constitutes a CMOS inverter. P channel MOS transistor QP is formed in protruding portion 10, and N channel MOS transistor QN is formed in protruding portion 11.
[0025]
The junction between the P-channel MOS transistor and the N-channel MOS transistor is the interface between the above-described high-concentration diffusion regions 4 and 5, and this is an ohmic contact because of the high concentration.
[0026]
In this embodiment, the P-channel MOS transistor is formed in the lower part (and therefore larger), and the N-channel MOS transistor is formed in the upper part (and therefore smaller). Since the mobility of holes is generally lower than the mobility of electrons, the current drive capability of the P-channel MOS transistor is lower than that of the N-channel MOS transistor. Therefore, it is desirable to increase the channel width of the P channel MOS transistor, and it is preferable to form an N type on the upper side and a P type on the lower side.
[0027]
With the configuration as described above, a CMOS inverter can be formed in a small region, which is very suitable for high integration. Of course, the gate electrode has the effect of absorbing photons as shown in the first embodiment.
[0028]
In the fourth embodiment, the CMOS inverter has been described as an example. However, the present invention is not limited to this, and various circuits such as a NAND gate, a NOR gate, and a CMOS transfer gate can be configured.
[0029]
(Fifth embodiment)
9 to 11 show a fifth embodiment of the present invention. This is a memory cell array of a nonvolatile semiconductor memory in which a plurality of vertical MOS transistors having floating gates are arranged.
[0030]
FIG. 9 is a plan view of the present embodiment, and FIG. A plurality of protrusions 51 are formed in a matrix on the P-type semiconductor substrate 50. The protrusions are arranged closer to each other in the row direction than in the column direction. A floating gate 53 made of polysilicon is formed around the protruding portion 51 via an insulating film 52. The floating gate 53 is independent at each protrusion, and does not come into contact with adjacent protrusions. Further, a control gate 55 made of a member that shields photons such as aluminum and tungsten silicide is formed around the floating gate 53 with an insulating film 54 interposed therebetween. The control gate 55 is in contact with each protrusion 51 adjacent in the row direction, and constitutes a word line WL extending in the row direction. Further, a source 56 made of an N-type diffusion region is formed around the lower portion of the protrusion, and a drain 57 made of N-type diffusion or less is formed on the upper surface of the protrusion. When this drain 57 is connected to each protrusion arranged in the column direction, a bit line BL is formed.
[0031]
FIG. 11 shows an equivalent circuit of the memory cell array having the above structure.
As described above, a memory cell array in which a plurality of MOS transistors having floating gates are arranged is configured, and word lines extend in the row direction and bit lines extend in the column direction. The word line can be formed by self-alignment without a mask alignment process. In addition, memory cells can be arranged at a very high density. Further, as can be seen from FIG. 10, since the nonvolatile memory cell has an offset gate structure, there is no problem of over-erasing when used in a flash memory.
[0032]
Further, since the word line WL is made of aluminum or the like, it acts as a photon absorption or shielding film, and does not emit photons to adjacent memory cells or peripheral circuits. Therefore, it goes without saying that the same effects as those of the first embodiment can be obtained.
[0033]
(Sixth embodiment)
FIG. 12 shows a sixth embodiment of the present invention. In this method, element isolation of a semiconductor element such as a MOS transistor is performed by groove isolation (trench isolation), and a photon shielding member such as aluminum is embedded in the groove. N to P type wells 66 and 67 are formed in an element region of a P type semiconductor substrate 60 having a groove in the element isolation region, respectively, and a gate electrode 62 made of polysilicon is formed through a gate insulating film 61. P-type impurity regions 63 and 64 are a source and a drain, respectively. In this way, the P-type MOS transistor 71 and the N-type MOS transistor 72 are configured. A photon shielding member 75 such as aluminum surrounded by an insulating film 76 is embedded in the element isolation region.
[0034]
In this way, photons generated in a semiconductor element such as a MOS transistor are directed to an adjacent element by replacing a conventional oxide or polysilicon buried in trench isolation with a photon shielding member such as aluminum. Can be prevented.
[0035]
(Seventh embodiment)
FIG. 13 shows a seventh embodiment. This shows the entire circuit configuration of the EEPROM. That is, a memory cell array (for example, the nonvolatile memory cell array shown in FIG. 9) 81 composed of a plurality of memory cells, a row decode circuit 82 for selecting a word line WL, a sense amplifier circuit 85 for amplifying data on a bit line BL, A column gate circuit 83 for selectively connecting a bit line and a sense amplifier, a column decode circuit 84 for selecting a bit line to be connected, a ring oscillator circuit 86 for generating a clock, and a charge for generating a boosted voltage based on the generated clock The circuit includes a pump circuit 90, an output buffer circuit 87, an address input terminal 88, a data output terminal 89, and the like. In addition, various peripheral circuits or control circuits are added but omitted.
[0036]
Here, since the ring oscillator 86 and the charge pump 90 are operating constantly or intermittently, a large number of photons are generated. Therefore, in order to prevent these photons from flowing out to the external circuit, a photon absorbing member such as a groove separation shown in FIG. 12 is arranged around the circuit.
[0037]
Further, in order to prevent photons from entering the sense amplifier or the like, a photon shielding / absorbing member is also arranged around the circuit by groove separation as shown in FIG.
With the above configuration, the circuit itself is separated by a groove in which a photon absorbing member such as aluminum is embedded, so that the subthreshold current can be suppressed at the same time without reducing the margin of a high sensitivity element such as a sense amplifier. A semiconductor integrated circuit with low power consumption can be provided.
[0038]
Although various embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the spirit of the invention.
[0039]
【The invention's effect】
As described above, according to the present invention, photons generated in a semiconductor element can be prevented from affecting adjacent elements, and as a result, the reliability of the semiconductor integrated circuit is improved and the power consumption is reduced. However, high integration is possible.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention.
FIG. 4 is a plan view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 5 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 6 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 7 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 8 is an equivalent circuit diagram of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 9 is a plan view of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 10 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 11 is an equivalent circuit diagram of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 12 is a perspective view of a semiconductor device according to a sixth embodiment of the present invention.
FIG. 13 is a plan view of a semiconductor device according to a seventh embodiment of the present invention.
FIG. 14 is a current / voltage characteristic diagram showing the effect of the embodiment of the present invention.
FIG. 15 is a cross-sectional view of a semiconductor device according to an example of the present invention.
[Explanation of symbols]
30 P-type semiconductor substrate 31 Projection 32 Gate insulating film 33 Aluminum gate electrode 34 Source 35 Drain 37 Photon moving path 38, 39 Photon shielding part

Claims (3)

  In a semiconductor device comprising a semiconductor element formed on a semiconductor substrate, the semiconductor element is formed by forming a drain in a partial region of a semiconductor pillar protruding from the semiconductor substrate and a source on a surface of the semiconductor substrate, A gate electrode surrounds an insulating film formed with a substantially constant film thickness around the semiconductor pillar, and a member that shields photons around the gate electrode continuously from the semiconductor pillar bottom position to the top position, A semiconductor device is provided so as to surround the gate electrode.   In a semiconductor device comprising a semiconductor element formed on a semiconductor substrate, the semiconductor element is formed by forming a drain in a partial region of a semiconductor pillar protruding from the semiconductor substrate and a source on a surface of the semiconductor substrate, A gate electrode surrounds the semiconductor pillar via an insulating film, and a member for shielding photons is disposed around the gate electrode. The member is electrically connected to the source, and the source is led out. A semiconductor device which is used as an electrode. The semiconductor device according to any one of claims 1 to 2 members for shielding the photon is characterized in that it is composed of a layer containing a metal material.

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