JPH098295A - Semiconductor device - Google Patents

Abstract

PURPOSE: To reduce the influence to a semiconductor element adjacent with generated photons by forming a source on the surface of a semiconductor substrate, surrounding the periphery of a semiconductor post protruding from the substrate by a gate electrode via an insulating film, and so forming the gate electrode as to include a layer containing metal as the member for shielding the photon. CONSTITUTION: The P-type semiconductor substrate 30 made of a silicon single crystal has a protrusion 31 made of the same member, and the sidewall is covered with a gate insulating film 32 made of an oxide film. Further, it is surrounded by a gate electrode 33 made of aluminum via the gate insulating film 31. A source 34 is formed on the surface of the substrate 30 near the lower part of the protrusion 31, and a drain 35 is formed at the upper part of the protrusion 31. Accordingly, since the electrode 33 is formed of aluminum for absorbing and shielding photon, the photon permeated through the film 32 is absorbed and shielded at the sites 38, 39, and the arrival of the photon generated at the drain 35 at the adjacent element is substantially completely prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a highly reliable semiconductor device in which the influence of photons generated in the drain of a MOS transistor on other MOS transistors is minimized.

[0002]

2. Description of the Related Art Photons are generated when a voltage is applied to a PN junction. In an integrated circuit in which a plurality of semiconductor elements are formed on the same semiconductor substrate surface, in order to prevent the photons generated from affecting adjacent semiconductor elements as much as possible, LDD
Structures such as (Lightly Doped Drain) have been proposed, but they were not always sufficient. The generation of such photons leads to an increase in the subthreshold current of the surrounding MOS transistors. In particular, in a nonvolatile semiconductor memory device (eg, EEPROM) having a ring oscillator and an internal booster circuit, a large amount of photons are generated in this ring oscillator or booster circuit, which causes a penetration current when other peripheral circuits are not operating. It led to an increase.

[0003]

As described above, in the conventional semiconductor device, generation of photons in the drain of the MOS transistor is unavoidable, and the generated photons may adversely affect the surrounding semiconductor elements. .

The present invention has been made in view of the above circumstances, and its purpose is not to suppress the generation of photons, but rather to release the generated photons to the back side of the substrate and absorb / shield them. Accordingly, it is to provide a semiconductor device in which the influence of photons on an adjacent semiconductor element is reduced as much as possible.

[0005]

In order to solve the above problems, the semiconductor device of the present invention is characterized in that means for shielding photons is provided so as to surround the semiconductor element. In this semiconductor element, a drain is formed in a partial region of a semiconductor pillar protruding from a semiconductor substrate, and a source is formed on the surface of the semiconductor substrate. A gate electrode surrounds the semiconductor pillar through an insulating film, and the gate electrode is It is composed of a member that shields photons, for example, a layer containing a metal.
As a result, the photons are reflected and absorbed by the shielding member.

As another example, in the present invention, a drain is formed in a partial region of a semiconductor pillar protruding from a semiconductor substrate and a source is formed on the surface of the semiconductor substrate, and an insulating film is provided around the semiconductor pillar. The semiconductor device is characterized in that the gate electrode surrounds the gate electrode, and the above-mentioned means is a member arranged around the gate electrode to shield photons. This member is electrically connected to the source and is used as a lead electrode of the source.

Further, according to the present invention, as still another example, the semiconductor substrate and the first substrate formed on the surface of the semiconductor substrate.
Of the first protrusion, a second protrusion formed on the first protrusion, a first gate electrode formed around the first protrusion through a first insulating film, and a second protrusion. And a second gate electrode formed around the protruding portion of the first insulating film via a second insulating film. The first conductive type first vertical MOS is formed on the first protruding portion.
A transistor is formed, a second vertical MOS transistor of the second conductivity type is formed on the second protrusion, and the first and second vertical MOS transistors are the first protrusion and the second protrusion. Is electrically connected at the interface with
Alternatively, a semiconductor device is provided in which the second gate electrode is formed of a member that shields photons. The first MOS transistor is a P-type MOS transistor, and the second MOS transistor is an N-type MOS transistor.
It is a transistor.

In still another example of the present invention, a plurality of protrusions arranged adjacent to each other on a semiconductor substrate and the periphery of the protrusions are electrically surrounded by a first insulating film. Independently placed multiple floating gates,
A common control gate that surrounds a plurality of floating gates via a second insulating film and is arranged in electrical contact with each other, and the common control gate is composed of a member that shields photons. A characteristic semiconductor device is provided.

Further, according to the present invention, as still another example, in a semiconductor device in which a circuit block composed of a plurality of MOS transistors is formed on a semiconductor substrate, a groove is formed around the circuit block, and the groove is formed in the groove. Provided is a semiconductor device characterized in that a photon generated in a circuit block is prevented from leaking to the outside of the circuit block by embedding a member for shielding the photon therein. At the same time, in a semiconductor device in which a circuit block composed of a plurality of MOS transistors is formed on a semiconductor substrate, a groove is formed around the circuit block, and a member that shields photons is embedded in the groove so that the circuit block Provided is a semiconductor device, which is configured to prevent the photons generated in 1) from entering a circuit block.

[0010]

According to the present invention, even if a photon is generated in a semiconductor element, the photon shielding member provided around the element shields the photon, so that the adjacent semiconductor element is not affected. A highly reliable, low power consumption, highly integrated semiconductor integrated circuit can be configured.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a sectional view of a vertical MOS transistor according to the first embodiment of the present invention. A vertical MOS transistor formed on a semiconductor substrate is an SGT (Surr
oundingGate Transistor) structure. The P-type semiconductor substrate 30 made of silicon single crystal has a protrusion 31 (silicon pillar) made of the same member, and the side wall of the protrusion 31 is covered with a gate insulating film 32 made of an oxide film. Further, the protruding portion 31 is surrounded by the gate electrode 33 made of aluminum via the gate insulating film 31. An N-type impurity diffusion region (source) 34 is formed on the surface of the semiconductor substrate 31 in the vicinity of the lower portion of the protrusion 31, and an N-type impurity diffusion region (drain) is formed above the protrusion 31.
35 is formed.

An example of a specific shape of this SGT is as follows. Width of protrusion is 0.5μm, height is 1.0μ
m, the thickness of the gate insulating film 32 is 10 nm, and the thickness of the gate electrode is 200 nm. Boron is diffused at a low concentration in the semiconductor substrate, and arsenic is diffused at a high concentration in the source 34 and the drain 35.

When operating the MOS transistor configured as described above, a power supply voltage of, for example, about 5 V may be applied to the drain 35. At this time, photons are generated at the PN junction portion of the drain. The generated photons are reflected at the interface between the gate insulating film 32 and the projecting portion 31 and are emitted to the substrate 30 side along the path indicated by the arrow 37. In this way, the protruding portion 31 made of silicon and the insulating film 32 around it serve as a waveguide to propagate photons in the substrate direction (downward direction in the drawing). As a result, the influence of photons on adjacent semiconductor elements is reduced to some extent.
However, the reflection at the interface between silicon and the oxide film is not always sufficient, and the photon may be transmitted depending on the incident angle of the photon. Here, if the gate electrode 33 is made of polysilicon as in the conventional case, the photons are easily transmitted, and the photons cannot be prevented from reaching the adjacent semiconductor element. In the present invention, since the gate electrode 33 is made of aluminum that absorbs and shields photons, the photons transmitted through the gate insulating film 32 are, for example, the parts 38 and 3.
It is absorbed and shielded by 9 mag. As a result, it is possible to almost completely prevent the photons generated in the drain 35 from reaching the adjacent element.

In the SGT structure as described above, the current / voltage characteristic is superior to that of the planar transistor. For example, FIG. 14 shows a subthreshold swing, but in SGT, it is about 60 mV / d.
A value that is almost ideal to ecade is obtained, which is smaller than that of a normal planar transistor. VG is a voltage applied to the gate, I is a current flowing between the source and drain, and FIG. 14 is a semi-logarithmic graph showing the relationship between VG and I. This is because, as shown in FIG. 15, when the size of the SGT becomes small and the diameter of the silicon pillar becomes 1 μm or less, the inside of the silicon pillar is completely depleted by the depletion layer 95. As a result, the SGT has a smaller subthreshold swing than that of a planar transistor, so that not only the cutoff characteristic is improved, but also the substrate bias effect is lost.

The feature of this SGT is that SOI (Silicon-on-I)
nsulator) structure transistor characteristics are similar. However, the SOI structure needs a means for mitigating the body effect. That is, in the case of a body contact for absorbing holes generated by impact ionization, for example, in the case of an N-channel type MOS transistor, it is necessary to provide a contact with a P-type high concentration region. This is SOI
This has hindered the miniaturization of structural transistors. But S
In the GT structure, the substrate acts as a body contact, and the generated holes are absorbed by the substrate. That is, SG
The T structure has characteristics of a transistor having an SOI structure and at the same time does not require a body contact and is suitable for miniaturization.

Such an SGT structure is more resistant to photons than SOI. In the SOI structure, the generated photons propagate laterally through the silicon film on the insulator film (Insulator), and the photons generated from one transistor propagate to the peripheral transistors, affecting the current / voltage characteristics. This is because it has the same problem as that of a normal planar transistor in terms of the influence.

Although the gate electrode 33 is made of aluminum in the above-mentioned example, it is made of a conductive material containing a metal such as tungsten, titanium, tungsten silicide or titanium silicide which is a photon absorbing member. Good.

(Second Embodiment) FIG. 2 is a sectional view of a vertical MOS transistor according to a second embodiment of the present invention. Similar to the first embodiment, the vertical MOS transistor formed on the semiconductor substrate has the SGT structure. The P-type semiconductor substrate 40 made of silicon single crystal has a protrusion 41 (silicon pillar) made of the same member.
Is covered with a gate insulating film 42 made of an oxide film. Further, the protruding portion 41 is surrounded by a gate electrode 43 made of polysilicon doped with impurities at a high concentration via the gate insulating film 41. An N-type impurity diffusion region (source) 44 is formed on the surface of the semiconductor substrate 40 near the bottom of the protrusion 41, and an N-type impurity diffusion region (drain) 45 is formed on the protrusion 41. There is.
Further, a photon absorption member 46 is formed so as to surround the drain electrode 43. As shown in FIG. 2, the member 46 is inserted between the adjacent SGTs.

When the MOS transistor configured as described above is operated, photons are generated at the PN junction of the drain. The generated photons are reflected at the interface between the gate insulating film 42 and the projecting portion 41, and are emitted to the substrate 40 side through the path indicated by the arrow 47. As described above, similarly to the first embodiment, the protruding portion 41 made of silicon and the insulating film 42 around the protruding portion 41 function as a waveguide to propagate photons in the substrate direction (downward direction in the drawing). As a result, the influence of photons on adjacent semiconductor elements is reduced to some extent. Here, the reflection at the interface between the silicon and the oxide film is not always sufficient, and the photon is transmitted depending on the incident angle of the photon, but since the member 46 is made of aluminum that absorbs the photon, The photons transmitted through the gate insulating film 42 are absorbed by the member 46. As a result,
It is possible to almost completely prevent the photons generated in the drain 45 from reaching the adjacent element.

The second embodiment also has an advantage that polysilicon can be used for the gate electrode 43 as in the prior art. Although the shielding member 46 is made of aluminum in the above-mentioned example, the same material as that of the first embodiment may be formed of a material that absorbs photons, such as tungsten or titanium.

(Third Embodiment) FIG. 3 is a sectional view of a vertical MOS transistor according to a third embodiment of the present invention. Parts similar to those in the second embodiment are designated by similar drawing numbers,
A detailed description of the structure is omitted. In the third embodiment, as described above, the photon shielding member 46 is made of a conductive material such as aluminum, tungsten, titanium, etc., and is electrically connected to the source 44. Therefore, the photon shielding member 46 can be used as a lead electrode of the source. With this configuration,
This has the effect of facilitating contact with the upper wiring.

(Fourth Embodiment) FIGS. 4 to 8 show a fourth embodiment of the present invention. The fourth embodiment is a vertical CMOS
It is an example of forming an inverter.

FIG. 4 is a plan view of the CMOS inverter, FIG. 5 is a sectional view taken along line 5a of FIG. 4, FIG. 6 is a sectional view taken along line 5b of FIG. 4, and FIG. 7 is a sectional view taken along line 5c of FIG. . The P-type semiconductor substrate 1 has a first protrusion 10
Also, a second protrusion 11 formed on a part of the first protrusion 10 is formed. A P-type high-concentration diffusion region 2 is formed in the “root” region of the first protrusion 10 and the surface region of the substrate 1. The protrusion 10 is composed of a high-concentration P-type diffusion region, an N-type diffusion region 3, a high-concentration P-type diffusion region 4, and a high-concentration N-type diffusion region 5 in this order from the bottom. The protruding portion 11 is composed of a high concentration N type diffusion region 5, a P type diffusion region 6 and a high concentration N type diffusion region 7 in order from the bottom. The aluminum gate electrode 91 is provided on the side wall of the first protrusion 10 via the insulating film 81, and the insulating film 8 is provided on the side wall of the second protrusion 11.
Aluminum gate electrodes 92 are respectively formed through the two. The high-concentration N-type diffusion region 5 is formed in the region of the upper surface of the first protrusion 10 where the second protrusion 11 is not formed.
The electrode 15 is formed in contact with. Further, on the upper surface of the second protrusion 11, the electrode 17 is in contact with the high concentration diffusion region 7.
Are formed. The gate electrodes 92 and 91 are integrally formed and connected to the electrode 14 at a position apart from the above structure. Similarly, the N-type high-concentration diffusion region 2 is also connected to the electrode 16 at a position apart from the above structure. The structure described above is covered with the interlayer insulating film 12.

FIG. 8 is an equivalent circuit of the above concept body,
Configure a CMOS inverter. A P-channel MOS transistor QP is formed on the protruding portion 10, and an N-channel MOS transistor QN is formed on the protruding portion 11.

The junction between the P-channel MOS transistor and the N-channel MOS transistor is the interface between the above-mentioned high-concentration diffusion regions 4 and 5, which becomes an ohmic contact because of the high concentration.

In the present embodiment, the P-channel MOS transistor is formed in the lower portion (thus larger) and the N-channel MOS transistor is formed in the upper portion (thus smaller). In general, the mobility of holes is lower than the mobility of electrons, so the current drive capability of P-channel MOS transistors is N.
Lower than that of the channel MOS transistor. Therefore, it is desirable to increase the channel width of the P-channel MOS transistor, and it is preferable to form the N-type on the upper side and the P-type on the lower side.

With the above structure, it is possible to form a CMOS inverter in a small area, which is very suitable for high integration. Of course, the gate electrode has the effect of absorbing photons as shown in the first embodiment.

In the fourth embodiment, the CMOS inverter has been described as an example, but the present invention is not limited to this, and various circuits such as a NAND gate, a NOR gate and a CMOS transfer gate can be configured.

(Fifth Embodiment) FIGS. 9 to 11 show a fifth embodiment of the present invention. This is a memory cell array of a nonvolatile semiconductor memory in which a plurality of vertical MOS transistors having floating gates are arranged.

FIG. 9 is a plan view of this embodiment, and FIG. 10 is a sectional view taken along line 9a of FIG. A plurality of protrusions 51 are formed in a matrix on the P-type semiconductor substrate 50. The protrusions are arranged closer to each other in the row direction than in the column direction. Around the protrusion 51, a floating gate 53 made of polysilicon is formed via an insulating film 52. The floating gate 53 is independent at each protrusion, and does not come into contact with an adjacent protrusion. Further, around the floating gate 53, a control gate 55 made of a member that shields photons such as aluminum and tungsten silicide is formed via an insulating film 54. The control gate 55 is in contact with each of the protrusions 51 adjacent to each other in the row direction and forms a word line WL extending in the row direction.
Further, a source 56 made of an N-type diffusion region is formed around the lower portion of the protrusion, and a drain 57 made of N-type diffusion or less is formed on the upper surface of the protrusion. The drain 57 is connected to each of the protrusions arranged in the column direction to form the bit line BL.

FIG. 11 shows an equivalent circuit of the memory cell array having the above structure. As described above, a memory cell array in which a plurality of MOS transistors having floating gates are arranged is formed, and word lines extend in the row direction and bit lines extend in the column direction. Then, this word line can be formed by self-alignment without a mask alignment step. Also, the memory cells can be arranged in a very high density. Further, as can be seen from FIG. 10, since the non-volatile memory cell has an offset gate structure, the problem of excessive erasing when used in a flash memory does not occur.

Further, since the word line WL is made of aluminum or the like, it acts as a photon absorption or shielding film and does not emit photons to the adjacent memory cells or peripheral circuits. Therefore, it goes without saying that the same effect as that of the first embodiment can be obtained.

(Sixth Embodiment) FIG. 12 shows a sixth embodiment of the present invention. This is a device in which a semiconductor device such as a MOS transistor is isolated by trench isolation, and a photon shielding member such as aluminum is embedded in the trench. N-type or P-type wells 66 and 67 are formed in the element regions of the P-type semiconductor substrate 60 having a groove in the element isolation region, and a gate electrode 62 made of polysilicon is formed via a gate insulating film 61. The P-type impurity regions 63 and 64 are the source and
It is the drain. In this way, the P-type MOS transistor 71 and the N-type MOS transistor 72 are configured. A photon shielding member 75 such as aluminum surrounded by an insulating film 76 is embedded in the element isolation region.

As described above, the conventional oxide or polysilicon is buried in the trench isolation instead of the photon shielding member such as aluminum, so that the photons generated in the semiconductor element such as the MOS transistor are adjacent to each other. It is possible to prevent going to the element.

(Seventh Embodiment) FIG. 13 shows a seventh embodiment. This shows the entire circuit configuration of the EEPROM. That is, a memory cell array composed of a plurality of memory cells (for example, the nonvolatile memory cell array shown in FIG. 9) 81, a row decode circuit 82 that selects a word line WL, a sense amplifier circuit 85 that amplifies data on a bit line BL, A column gate circuit 83 that selectively connects the bit line and the sense amplifier, a column decode circuit 84 that selects the connected bit line, a ring oscillator circuit 86 that generates a clock, and a charge that generates a boosted voltage based on the generated clock. Pump circuit 90, output buffer circuit 87, address input terminal 88, data output terminal 89
Etc. Besides, various peripheral circuits and control circuits are added, but are omitted.

Since the ring oscillator 86 and the charge pump 90 operate steadily or intermittently,
Generates many photons. Therefore, in order to prevent these photons from flowing out to the external circuit, a photon absorption member such as the groove separation shown in FIG. 12 is arranged around the circuit.

Further, in order to prevent photons from entering the sense amplifier or the like, the photon shielding / absorbing member is similarly arranged around the circuit by groove separation as shown in FIG. With the above configuration, the circuit itself is separated by the groove in which the photon absorption member such as aluminum is embedded, so that the subthreshold current is suppressed at the same time without reducing the margin of the high-sensitivity element such as the sense amplifier. A semiconductor integrated circuit with low power consumption can be provided.

Although various embodiments of the present invention have been described above, it is needless to say that the present invention is not limited to the above embodiments and various modifications can be made without departing from the spirit of the invention. Yes.

[0039]

As described above, according to the present invention,
It is possible to prevent the photons generated in the semiconductor element from affecting the adjacent elements, and as a result, the reliability of the semiconductor integrated circuit is improved, the power consumption is reduced, and the high integration can be achieved.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a plan view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a plan view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 11 is an equivalent circuit diagram of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 12 is a perspective view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 13 is a plan view of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 14 is a current / voltage characteristic diagram showing the effect of the embodiment of the present invention.

FIG. 15 is a sectional view of a semiconductor device according to an example of the present invention.

[Explanation of symbols]

 30 P-type semiconductor substrate 31 Protruding part 32 Gate insulating film 33 Aluminum gate electrode 34 Source 35 Drain 37 Photon moving path 38, 39 Photon shielding site

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 21/8247 H01L 29/78 371 29/788/29/792

Claims (14)

[Claims] 1. A semiconductor device comprising a semiconductor element formed on a semiconductor substrate, wherein a means for shielding photons is provided so as to surround the semiconductor element. 2. The semiconductor device comprises a drain formed in a partial region of a semiconductor pillar protruding from the semiconductor substrate and a source formed on a surface of the semiconductor substrate, and the semiconductor pillar is surrounded by an insulating film. 2. The semiconductor device according to claim 1, wherein the semiconductor device is surrounded by a gate electrode, and the gate electrode is constituted by means for shielding photons. 3. The semiconductor device comprises a drain formed in a partial region of a semiconductor pillar projecting from the semiconductor substrate and a source formed on a surface of the semiconductor substrate, and an insulating film is formed around the semiconductor pillar. 2. The semiconductor device according to claim 1, wherein the semiconductor device is surrounded by a gate electrode, and the means is a member arranged around the gate electrode to shield photons. 4. The semiconductor device according to claim 3, wherein the member is electrically connected to the source and is used as a lead electrode of the source. 5. The photon shielding member is composed of a layer containing a metal material.
5. The semiconductor device according to any one of 4 to 4. 6. A semiconductor substrate, a first protrusion formed on the surface of the semiconductor substrate, a second protrusion formed on a part of the first protrusion, and the first protrusion. A first gate electrode formed on the periphery of the second portion via a first insulating film, and a second gate electrode formed on the periphery of the second protruding portion via a second insulating film. A first conductivity type first vertical MOS transistor is formed on the first protrusion, and a second conductivity type second vertical MOS transistor is formed on the second protrusion, The first and second vertical MOS transistors are electrically connected to each other at the interface between the first protrusion and the second protrusion, and the first and second gate electrodes shield photons. A semiconductor device comprising: 7. The first MOS transistor is a P-type M
7. The semiconductor device according to claim 6, wherein the semiconductor device is an OS transistor, and the second MOS transistor is an N-type MOS transistor. 8. The semiconductor device according to claim 6, wherein the first or second gate electrode is made of aluminum, tungsten, or titanium. 9. A plurality of protrusions arranged adjacent to each other on a semiconductor substrate, and a plurality of floating gates surrounding the protrusions with a first insulating film interposed therebetween and electrically independent of each other. And a common control gate that surrounds the plurality of floating gates via a second insulating film and is placed in electrical contact with each other. The common control gate is configured by a member that shields photons. A semiconductor device characterized in that. 10. The semiconductor device according to claim 9, wherein the common control gate is composed of a layer containing a metal material. 11. A semiconductor device having a circuit block composed of a plurality of MOS transistors formed on a semiconductor substrate, wherein a groove is formed around the circuit block, and a member for shielding photons is embedded in the groove. The semiconductor device is configured so that photons generated in the circuit block are not leaked to the outside of the circuit block. 12. The semiconductor device according to claim 11, wherein the circuit block is a clock generation circuit that generates a high voltage and a charge pump circuit. 13. A semiconductor device comprising a circuit block composed of a plurality of MOS transistors formed on a semiconductor substrate, wherein a groove is formed around the circuit block, and a member for shielding photons is embedded in the groove. The semiconductor device is configured so as to prevent photons generated outside the circuit block from entering the circuit block. 14. The semiconductor device according to claim 13, wherein the circuit block is a sense amplifier circuit.