US20160247691A1 - Etching method - Google Patents

Etching method Download PDF

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Publication number
US20160247691A1
US20160247691A1 US15/046,871 US201615046871A US2016247691A1 US 20160247691 A1 US20160247691 A1 US 20160247691A1 US 201615046871 A US201615046871 A US 201615046871A US 2016247691 A1 US2016247691 A1 US 2016247691A1
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Prior art keywords
gas
region
processing
plasma
fluorocarbon
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US15/046,871
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English (en)
Inventor
Hikaru Watanabe
Akihiro Tsuji
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Assigned to TOKYO ELECTRON LIMITED reassignment TOKYO ELECTRON LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TSUJI, AKIHIRO, WATANABE, HIKARU
Publication of US20160247691A1 publication Critical patent/US20160247691A1/en
Priority to US15/905,213 priority Critical patent/US11205577B2/en
Priority to US17/516,586 priority patent/US20220051904A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Definitions

  • the present disclosure relates to an etching method, and particularly to a method of selectively etching a first region formed of silicon oxide, with respect to a second region formed of silicon nitride by a plasma processing on an object to be processed (“workpiece”).
  • a processing of forming an opening such as a hole or a trench may be performed on a region formed of silicon oxide (SiO 2 ).
  • SiO 2 silicon oxide
  • a workpiece is exposed to plasma of a fluorocarbon gas so that the region is etched.
  • a technology of selectively etching a first region formed of silicon oxide with respect to a second region formed of silicon nitride has been known.
  • a self-aligned contact (SAC) technology has been known.
  • the SAC technology is described in Japanese Patent Laid-Open Publication No. 2000-307001.
  • a workpiece to be processed in the SAC technology includes a first region made of silicon oxide, a second region made of silicon nitride, and a mask.
  • the second region is formed to define a recess
  • the first region is formed to fill the recess and cover the second region
  • the mask is formed on the first region and provides an opening above the recess.
  • plasma of a processing gas containing a fluorocarbon gas, an oxygen gas, and a rare gas is used in order to etch the first region.
  • the first region is etched and an upper opening is formed in the portion exposed from the opening of the mask.
  • the portion surrounded by the second region, that is, the first region within the recess is etched in a self-aligned manner. Accordingly, a lower opening continuous to the upper opening is formed in a self-aligned manner.
  • the present disclosure provides a method of selectively etching a first region formed of silicon oxide with respect to a second region formed of silicon nitride using a plasma processing on a workpiece.
  • the workpiece includes the second region configured to define a recess, the first region formed to fill the recess and to cover the second region, and a mask formed on the first region, the mask providing an opening having a width wider than a width of the recess, above the recess.
  • the method includes a sequence that is performed one or more times to etch the first region in a period including a time of exposing the second region, and a process of etching the first region by plasma of a second processing gas containing a fluorocarbon gas generated within a processing container after the sequence is performed one or more times.
  • the sequence includes (a) a process of generating plasma of a first processing gas containing a fluorocarbon gas within the processing container that accommodates the workpiece in order to form deposits containing fluorocarbon on the workpiece, and (b) a process of etching the first region by radicals of the fluorocarbon included in the deposits.
  • the first region in the process of generating the plasma of the second processing gas, the first region may be continuously etched to a bottom of the recess.
  • FIG. 1 is a flow chart illustrating an etching method according to an exemplary embodiment.
  • FIG. 2 is a sectional view exemplifying a workpiece to which the etching method according to the exemplary embodiment is applied.
  • FIG. 3 is a view schematically illustrating an example of a plasma processing apparatus that may be used to carry out the method illustrated in FIG. 1 .
  • FIG. 4 is a sectional view illustrating the workpiece after each step of the method illustrated in FIG. 1 is performed.
  • FIG. 5 is a sectional view illustrating the workpiece after each step of the method illustrated in FIG. 1 is performed.
  • FIG. 6 is a sectional view illustrating the workpiece after each step of the method illustrated in FIG. 1 is performed.
  • FIG. 7 is a sectional view illustrating the workpiece after each step of the method illustrated in FIG. 1 is performed.
  • FIG. 8 is a sectional view illustrating the workpiece after each step of the method illustrated in FIG. 1 is performed.
  • FIG. 9 is a sectional view illustrating the workpiece after each step of the method illustrated in FIG. 1 is performed.
  • FIG. 10 is a sectional view illustrating the workpiece after each step of the method illustrated in FIG. 1 is performed.
  • FIG. 11 is a sectional view illustrating the workpiece after each step of the method illustrated in FIG. 1 is performed.
  • FIG. 12 is a flow chart illustrating an etching method according to another exemplary embodiment.
  • FIG. 13 is a sectional view illustrating the workpiece after a step ST 14 of the method illustrated in FIG. 12 is performed.
  • a state where a film for protecting the second region is not formed on the top surface of the second region may occur at a time of gradually etching the first region and exposing the second region.
  • the second region is scraped.
  • a method of selectively etching a first region formed of silicon oxide with respect to a second region formed of silicon nitride using a plasma processing on a workpiece includes the second region configured to define a recess, the first region formed to fill the recess and to cover the second region, and a mask formed on the first region, the mask providing an opening having a width wider than a width of the recess, above the recess.
  • the method includes a sequence that is performed one or more times to etch the first region in a period including a time of exposing the second region, and a process of etching the first region by plasma of a second processing gas containing a fluorocarbon gas generated within a processing container after the sequence is performed one or more times.
  • the sequence includes (a) a process of generating plasma of a first processing gas containing a fluorocarbon gas within the processing container that accommodates the workpiece in order to form deposits containing fluorocarbon on the workpiece, and (b) a process of etching the first region by radicals of the fluorocarbon included in the deposits.
  • the first region in the process of generating the plasma of the second processing gas, the first region may be continuously etched to a bottom of the recess.
  • deposits of fluorocarbon are formed on the workpiece when the second region is exposed, and then the first region is etched by the radicals in the deposits.
  • the sequence SQ although the etching rate is low, the first region is etched, and the second region is suppressed from being scraped when the second region is exposed.
  • the first region in a state where the second region is protected by the deposits formed by carrying out the sequence, the first region is further etched by the plasma of the fluorocarbon gas.
  • the etching rate of the first region etched by the plasma of fluorocarbon after the sequence is performed is higher than the etching rate of the first region in the sequence. Accordingly, according to the method, it is possible to achieve both a scraping suppression of the second region, and a decrease of a processing time required for etching the first region.
  • each time of the sequence may further include a process of generating plasma of a third processing gas containing an oxygen-containing gas and an inert gas within the processing container that accommodates the workpiece.
  • the amount of the deposits formed on the workpiece may be properly reduced by the active species of oxygen. Accordingly, it is possible to suppress an opening of the mask, and an opening formed by etching from being clogged.
  • the oxygen-containing gas in the processing gas, is diluted with the inert gas, and thus it is possible to suppress the deposits from being excessively removed.
  • a process of generating the plasma of the third processing gas is performed between the process of generating the plasma of the first processing gas, and the process of etching the first region by the radicals of the fluorocarbon.
  • Each time of the sequence may further include a process of generating the plasma of the third processing gas within the processing container that accommodates the workpiece after the process of etching the first region by the radicals of the fluorocarbon is performed.
  • the deposits may clog the openings.
  • the workpiece is exposed to active species of oxygen.
  • the deposits which narrow the widths of the openings may be reduced so that the openings may be more reliably prevented from being clogged.
  • FIG. 1 is a flow chart illustrating an etching method according to an exemplary embodiment.
  • the method MT illustrated in FIG. 1 is a method of selectively etching a first region formed of silicon oxide with respect to a second region formed of silicon nitride by a plasma processing on a workpiece.
  • FIG. 2 is a sectional view exemplifying a workpiece to which the etching method according to the exemplary embodiment is applied.
  • a workpiece that is, a wafer W
  • a wafer W includes a substrate SB, a first region R 1 , a second region R 2 , and an organic layer OL constituting a mark later.
  • the wafer W is obtained in the course of manufacturing a fin field effect transistor and includes a raised area RA, a silicon-containing anti-reflection layer AL, and a resist mask RM.
  • the raised area RA is formed to be raised from the substrate SB.
  • the raised area RA may constitute, for example, a gate region.
  • the second region R 2 is formed of silicon nitride (Si 3 N 4 ), and is formed on the top surface of the raised area RA and the top surface of the substrate SB.
  • the second region R 2 as illustrated in FIG. 2 , extends to define a recess.
  • the depth of the recess is about 150 nm, and the width of the recess is about 20 nm.
  • the first region R 1 is formed of silicon oxide (SiO 2 ) and is formed on the second region R 2 . Specifically, the first region R 1 is formed to fill the recess defined by the second region R 2 and to cover the second region R 2 .
  • the organic layer OL is formed on the first region R 1 .
  • the organic layer OL may be formed of an organic material, for example, an amorphous carbon.
  • the anti-reflection layer AL is formed on the organic layer OL.
  • the resist mask RM is formed on the anti-reflection layer AL.
  • the resist mask RM provides an opening having a width wider than a width of the recess, above the recess defined by the second region R 2 .
  • the width of the opening of the resist mask RM is, for example, 60 nm.
  • the pattern of the resist mask RM is formed by a photolithography technology.
  • FIG. 3 is a view schematically illustrating an example of a plasma processing apparatus that may be used to carry out the method illustrated in FIG. 1 .
  • a plasma processing illustrated in FIG. 3 is a capacitively-coupled plasma etching apparatus, and includes a substantially cylindrical processing container 12 .
  • An inner wall surface of the processing container 12 is made of, for example, anodized aluminum.
  • the processing container 12 is frame-grounded.
  • a substantially cylindrical support unit 14 is provided on a bottom portion of the processing container 12 .
  • the support unit 14 is made of, for example, an insulating material.
  • the support unit 14 vertically extends from the bottom portion of the processing container 12 within the processing container 12 .
  • a placing table PD is provided within the processing container 12 .
  • the placing table PD is supported by the support unit 14 .
  • the placing table PD holds the wafer W on the top surface thereof.
  • the placing table PD includes a lower electrode LE and an electrostatic chuck ESC.
  • the lower electrode LE includes a first plate 18 a and a second plate 18 b .
  • Each of the first plate 18 a and the second plate 18 b is made of a metal such as, for example, aluminum, and has substantially a disk shape.
  • the second plate 18 b is provided on the first plate 18 a , and is electrically connected to the first plate 18 a.
  • the electrostatic chuck ESC has a structure where an electrode serving as a conductive film is disposed between a pair of insulating layers or insulating sheets.
  • a DC power supply 22 is electrically connected to the electrode of the electrostatic chuck ESC via a switch 23 .
  • the electrostatic chuck ESC attracts the wafer W by an electrostatic force such as a coulomb force generated by a DC voltage from the DC power supply 22 . Accordingly, the electrostatic chuck ESC may hold the wafer W thereon.
  • a focus ring FR is disposed to surround the edge of the wafer W and the electrostatic chuck ESC.
  • the focus ring FR is provided to improve the uniformity of the etching.
  • the focus ring FR is formed of a material appropriately selected depending on a material of a film to be etched, and may be made of, for example, quartz.
  • a coolant flow path 24 is formed within the second plate 18 b .
  • the coolant flow path 24 constitutes a temperature control mechanism.
  • a coolant is supplied to the coolant flow path 24 from a chiller unit provided outside the processing container 12 through a pipe 26 a .
  • the coolant supplied to the coolant flow path 24 is returned to the chiller unit through a pipe 26 b . In this manner, between the coolant flow path 24 and the chiller unit, the coolant is circulated.
  • the temperature of the wafer W supported by the electrostatic chuck ESC is controlled.
  • a gas supply line 28 is formed in the plasma processing apparatus 10 .
  • the gas supply line 28 supplies a heat transfer gas such as, for example, a He gas, from a heat transfer gas supply mechanism to a gap between the top surface of the electrostatic chuck ESC and the rear surface of the wafer W.
  • a heat transfer gas such as, for example, a He gas
  • the plasma processing apparatus 10 includes an upper electrode 30 .
  • the upper electrode 30 is disposed to face the placing table PD above the placing table PD.
  • the lower electrode LE and the upper electrode 30 are provided substantially parallel to each other. Between the upper electrode 30 and the lower electrode LE, a processing space S is provided to perform a plasma processing on the wafer W.
  • the upper electrode 30 is supported at the top portion of the processing container 12 through an insulating shielding member 32 .
  • the upper electrode 30 may be configured such that a distance from the top surface of the placing table PD, that is, the wafer placing surface, in a vertical direction is variable.
  • the upper electrode 30 may include an electrode plate 34 and an electrode support 36 .
  • the electrode plate 34 faces the processing space S, and a plurality of gas ejecting holes 34 a are formed in the electrode plate 34 .
  • the electrode plate 34 is made of silicon in the exemplary embodiment.
  • the electrode support 36 is configured to detachably support the electrode plate 34 and may be made of, for example, a conductive material such as aluminum.
  • the electrode support 36 may have a water-cooling structure.
  • a gas diffusion chamber 36 a is formed within the electrode support 36 .
  • a plurality of gas flow holes 36 b extend downwards from the gas diffusion chamber 36 a to communicate with the gas ejecting holes 34 a .
  • a gas inlet port 36 c is formed in the electrode support 36 to guide a processing gas into the gas diffusion chamber 36 a .
  • a gas supply pipe 38 is connected to the gas inlet port 36 c.
  • a gas source group 40 is connected to the gas supply pipe 38 through a valve group 42 and a flow rate controller group 44 .
  • the gas source group 40 includes a plurality of gas sources.
  • the gas source group 40 includes one or more sources of a fluorocarbon gas, a source of a rare gas, a source of a nitrogen gas (N 2 gas), a source of a hydrogen gas (H 2 gas), and a source of an oxygen-containing gas.
  • One or more sources of the fluorocarbon gas in an example, may include a source of C 4 F 8 gas, a source of CF 4 gas, and a source of C 4 F 6 gas.
  • the source of the rare gas may be a source of any rare gas such as He gas, Ne gas, Ar gas, Kr gas, or Xe gas, and may be, in an example, a source of Ar gas.
  • the source of the oxygen-containing gas may be, in an example, a source of oxygen gas (O 2 gas).
  • the oxygen-containing gas may be any gas containing oxygen, and may be, for example, a carbon oxide gas such as CO gas or CO 2 gas.
  • the valve group 42 includes a plurality of valves
  • the flow rate controller group 44 includes a plurality of flow rate controllers such as, for example, a mass flow controller.
  • the plurality of gas sources of the gas source group 40 are connected to the gas supply pipe 38 through respective corresponding valves of the valve group 42 , and respective corresponding flow controllers of the flow rate controller group 44 .
  • a deposition shield 46 is detachably provided along the inner wall of the processing container 12 .
  • the deposition shield 46 is also provided on the outer periphery of the support unit 14 .
  • the deposition shield 46 is configured to suppress etching by-products (deposits) from being attached to the processing container 12 , and may be formed by coating a ceramic such as, for example, Y 2 O 3 on an aluminum material.
  • An exhaust plate 48 is provided on the bottom side of the processing container 12 between the support unit 14 and the side wall of the processing container 12 .
  • the exhaust plate 48 may be formed by coating a ceramic such as, for example, Y 2 O 3 on an aluminum material.
  • An exhaust port 12 e is formed below the exhaust plate 48 in the processing container 12 .
  • An exhaust device 50 is connected to the exhaust port 12 e through an exhaust pipe 52 .
  • the exhaust device 50 includes a vacuum pump such as, for example, a turbo molecular pump and may decompress the space within the processing container 12 to a desired degree of vacuum.
  • a carry-in/out port 12 g of the wafer W is formed in the side wall of the processing container 12 .
  • the carry-in/out port 12 g is configured to be capable of being opened/closed by a gate valve 54 .
  • the plasma processing apparatus 10 further includes a first high frequency power supply 62 and a second high frequency power supply 64 .
  • the first high frequency power supply 62 is a power supply which generates a high frequency power for generating plasma and generates a high frequency power of a frequency ranging from, for example, 27 MHz to 100 MHz.
  • the first high frequency power supply 62 is connected to the lower electrode LE through a matching unit 66 .
  • the matching unit 66 is a circuit configured to match an output impedance of the first high frequency power supply 62 to an input impedance of a load side (a lower electrode LE side).
  • the first high frequency power supply 62 may be connected to the upper electrode 30 through the matching unit 66 .
  • the second high frequency power supply 64 is a power supply which generates a high frequency bias power for drawing ions into the wafer W, and generates a high frequency bias power of a frequency ranging from, for example, 400 kHz to 13.56 MHz.
  • the second high frequency power supply 64 is connected to the lower electrode LE through a matching unit 68 .
  • the matching unit 68 is a circuit configured to match an output impedance of the second high frequency power supply 64 to an input impedance of a load side (a lower electrode LE side).
  • the plasma processing apparatus 10 further includes a power supply 70 .
  • the power supply 70 is connected to the upper electrode 30 .
  • the power supply 70 applies a voltage for drawing positive ions present within the processing space S to the electrode plate 34 , to the upper electrode 30 .
  • the power supply 70 is a DC power supply for generating a negative DC voltage.
  • the power supply 70 may be an AC power supply for generating an AC voltage of a relatively low frequency.
  • the voltage applied to the upper electrode from the power supply 70 may be a voltage of ⁇ 150 V or less. That is, the voltage applied to the upper electrode 30 by the power supply 70 may be a negative voltage having an absolute value of 150 V or more.
  • the plasma processing apparatus 10 may further include a controller Cnt.
  • the controller Cnt is a computer provided with, for example, a processor, a storage unit, an input device, and a display device, and controls respective units of the plasma processing apparatus 10 .
  • the controller Cnt allows an operator to perform, for example, the input operation of a command through the input device in order to manage the plasma processing apparatus 10 , and allows the display device to visually display the driving situation of the plasma processing apparatus 10 .
  • the storage unit of the controller Cnt stores a control program which controls the processor to execute various processings in the plasma processing apparatus 10 , or a program which causes respective units of the plasma processing apparatus 10 to execute the processings according to processing conditions, i.e., a processing recipe.
  • FIGS. 4 to 11 are sectional views illustrating the workpiece after each step of the method MT is performed. Meanwhile, the following descriptions will be made on an example of a processing of the wafer W illustrated in FIG. 2 , using one plasma processing apparatus 10 illustrated in FIG. 3 in the method MT.
  • the wafer W illustrated in FIG. 2 is carried into the plasma processing apparatus 10 , placed on the placing table PD, and held by the placing table PD.
  • step ST 1 is performed.
  • step ST 1 the anti-reflection layer AL is etched.
  • a processing gas is supplied into the processing container 12 from a gas source selected from the plurality of gas sources of the gas source group 40 .
  • the processing gas contains a fluorocarbon gas.
  • the fluorocarbon gas may contain, for example, at least one kind of C 4 F 8 gas and CF 4 gas.
  • the processing gas may further contain a rare gas, for example, Ar gas.
  • the exhaust device 50 is operated such that the pressure within the processing container 12 is set to a predetermined pressure.
  • the high frequency power is supplied from the first high frequency power supply 62 to the lower electrode LE, and the high frequency bias power is supplied from the second high frequency power supply 64 to the lower electrode LE.
  • step ST 1 various conditions in step ST 1 will be exemplified.
  • step ST 1 the plasma of the processing gas is generated, and the anti-reflection layer AL is etched at the portion exposed from the opening of the resist mask RM by the active species of the fluorocarbon.
  • the portion exposed from the opening of the resist mask RM is removed. That is, a pattern of the resist mask RM is transferred to the anti-reflection layer AL so that a pattern for providing an opening in the anti-reflection layer AL is formed.
  • the above described operations of the respective units of the plasma processing apparatus 10 in step ST 1 , may be controlled by the controller Cnt.
  • step ST 2 the organic layer OL is etched.
  • a processing gas is supplied into the processing container 12 from a gas source selected from the plurality of gas sources of the gas source group 40 .
  • the processing gas may further contain a hydrogen gas and a nitrogen gas.
  • the processing gas used in step ST 2 may be any processing gas containing another gas such as, for example, an oxygen gas as long as it can etch the organic layer.
  • the exhaust device 50 is operated such that the pressure within the processing container 12 is set to a predetermined pressure.
  • the high frequency power is supplied from the first high frequency power supply 62 to the lower electrode LE, and the high frequency bias power is supplied from the second high frequency power supply 64 to the lower electrode LE.
  • step ST 2 various conditions in step ST 2 will be exemplified.
  • step ST 2 the plasma of the processing gas is generated, and the organic layer OL is etched at the portion exposed from the opening of the anti-reflection layer AL. Also, the resist mask RM is etched. As a result, as illustrated in FIG. 5 , the resist mask RM is removed, and among the whole area of the organic layer OL, the portion exposed from the opening of the anti-reflection layer AL is removed. That is, a pattern of the anti-reflection layer AL is transferred to the organic layer OL so that a pattern for providing an opening MO in the organic layer OL is formed, and a mask MK is generated from the organic layer OL. Meanwhile, the above described operations of the respective units of the plasma processing apparatus 10 , in step ST 2 , may be controlled by the controller Cnt.
  • step ST 3 is performed.
  • the first region R 1 is etched until just before the second region R 2 is exposed. That is, the first region R 1 is etched until the first region R 1 is slightly left on the second region R 2 .
  • a processing gas is supplied into the processing container 12 from a gas source selected from the plurality of gas sources of the gas source group 40 .
  • the processing gas contains a fluorocarbon gas.
  • the processing gas may further contain a rare gas, for example, Ar gas.
  • the processing gas may further contain an oxygen gas.
  • the exhaust device 50 is operated such that the pressure within the processing container 12 is set to a predetermined pressure.
  • the high frequency power is supplied from the first high frequency power supply 62 to the lower electrode LE, and the high frequency bias power is supplied from the second high frequency power supply 64 to the lower electrode LE.
  • step ST 3 the plasma of the processing gas is generated, and the first region R 1 is etched at the portion exposed from the opening of the mask MK by the active species of the fluorocarbon.
  • the processing time in step ST 3 is set such that at the end of step ST 3 , the first region R 1 is left to a predetermined film thickness on the second region R 2 .
  • an upper opening UO is partially formed.
  • the above described operations of the respective units of the plasma processing apparatus 10 in step ST 3 , may be controlled by the controller Cnt.
  • step ST 11 a condition for a mode in which formation of deposits containing fluorocarbon on the top surface of the wafer W including the first region R 1 is dominant instead of etching of the first region R 1 , that is, a condition for a deposition mode is selected.
  • step ST 3 a condition for a mode in which etching of the first region R 1 is dominant instead of formation of deposits, that is a condition for an etching mode is selected.
  • the fluorocarbon gas used in step ST 3 may contain at least one kind of C 4 F 8 gas and CF 4 gas.
  • the fluorocarbon gas in this example is a fluorocarbon gas having a higher ratio of the number of fluorine atoms to the number of carbon atoms (that is, number of fluorine atoms/number of carbon atoms), than a ratio of the number of fluorine atoms to the number of carbon atoms (that is, number of fluorine atoms/number of carbon atoms) of the fluorocarbon gas used in step ST 11 .
  • the high frequency power for generating plasma used in step ST 3 may be set to be higher than the high frequency power for generating plasma used in step ST 11 . According to these examples, it is possible to realize the etching mode.
  • the high frequency bias power used in step ST 3 may also be set to be higher than the high frequency bias power used in step ST 11 .
  • the energy of ions to be drawn to the wafer W may be increased so that the first region R 1 may be etched at a high speed.
  • step ST 3 various conditions in step ST 3 will be exemplified.
  • step ST 4 is performed.
  • the plasma of a processing gas containing an oxygen-containing gas is generated within the processing container 12 .
  • a processing gas is supplied into the processing container 12 from a gas source selected from the plurality of gas sources of the gas source group 40 .
  • the processing gas in an example, may contain an oxygen gas as an oxygen-containing gas.
  • the processing gas may further contain an inert gas such as a rare gas (e.g., Ar gas) or a nitrogen gas.
  • the exhaust device 50 is operated such that the pressure within the processing container 12 is set to a predetermined pressure.
  • the high frequency power is supplied from the first high frequency power supply 62 to the lower electrode LE.
  • the high frequency bias power may not be supplied from the second high frequency power supply 64 to the lower electrode LE.
  • step ST 4 the active species of oxygen is generated and the opening MO of the mask MK is widened at its upper end portion by the active species of the oxygen. Specifically, as illustrated in FIG. 7 , the upper shoulder portion of the mask MK which defines the upper end portion of the opening MO is etched to exhibit a tapered shape. Accordingly, even when deposits produced in the subsequent steps are attached to the surface of the mask MK defining the opening MO, the reduction amount of the width of the opening MO may be reduced. Meanwhile, the above described operations of the respective units of the plasma processing apparatus 10 , in step ST 4 , may be controlled by the controller Cnt.
  • step ST 12 to be described below is to reduce a trace quantity of deposits formed during a sequence SQ, and it is required to suppress an excessive decrease of the deposits.
  • step ST 4 is performed to widen the width of the upper end portion of the opening MO of the mask MK, and its processing time is required to be short.
  • step ST 4 various conditions in step ST 4 will be exemplified.
  • step ST 11 the plasma of the processing gas (a first processing gas) is generated within the processing container 12 accommodating the wafer W.
  • a processing gas is supplied into the processing container 12 from a gas source selected from the plurality of gas sources of the gas source group 40 .
  • the processing gas contains a fluorocarbon gas.
  • the processing gas may further contain a rare gas, for example, Ar gas.
  • the exhaust device 50 is operated such that the pressure within the processing container 12 is set to a predetermined pressure.
  • the high frequency power is supplied from the first high frequency power supply 62 to the lower electrode LE.
  • step ST 11 the plasma of a processing gas containing a fluorocarbon gas is generated, and the dissociated fluorocarbon is deposited on the top surface of the wafer W to form deposits DP (see, e.g., FIG. 8 ).
  • the above described operations of the respective units of the plasma processing apparatus 10 , in step ST 11 may be controlled by the controller Cnt.
  • step ST 11 a condition for a deposition mode is selected.
  • C 4 F 6 gas is used as the fluorocarbon gas.
  • step ST 11 various conditions in step ST 11 will be exemplified.
  • step ST 12 the plasma of a processing gas (a third processing gas) containing an oxygen-containing gas and an inert gas is generated within the processing container 12 .
  • a processing gas is supplied into the processing container 12 from a gas source selected from the plurality of gas sources of the gas source group 40 .
  • the processing gas contains an oxygen gas as the oxygen-containing gas.
  • the processing gas contains a rare gas such as Ar gas, as an inert gas.
  • the inert gas may be a nitrogen gas.
  • the exhaust device 50 is operated such that the pressure within the processing container 12 is set to a predetermined pressure.
  • the high frequency power is supplied from the first high frequency power supply 62 to the lower electrode LE.
  • the high frequency bias power may not be supplied from the second high frequency power supply 64 to the lower electrode LE.
  • step ST 12 the active species of oxygen is generated, and the amount of the deposits DP on the wafer W is properly reduced by the active species of oxygen (see, e.g., FIG. 9 ). As a result, the opening MO and the upper opening UO are suppressed from being clogged by excessive deposits DP.
  • the oxygen gas is diluted with the inert gas, and thus it is possible to suppress the deposits DP from being excessively removed.
  • the above described operations of the respective units of the plasma processing apparatus 10 , in step ST 12 may be controlled by the controller Cnt.
  • step ST 12 various conditions in step ST 12 will be exemplified.
  • step ST 12 of the sequence SQ of each time is performed for 2 sec or more, and the deposits DP may be etched at a rate of 1 nm/sec or less in step ST 12 .
  • a time is required to switch gases for transition between respective steps ST 11 , ST 12 , and ST 13 . Accordingly, in consideration of a time required for stabilizing a discharge, step ST 12 needs to be performed at least 2 sec.
  • deposits for protecting the second region R 2 may be excessively removed.
  • step ST 12 the deposits DP are etched at a rate of 1 nm/sec or less. Accordingly, it is possible to properly adjust the amount of the deposits DP formed on the wafer W. Meanwhile, the rate of 1 nm/sec or less in the etching of the deposits DP in step ST 12 may be achieved by selecting a pressure within a processing container, the oxygen dilution degree with a rare gas in the processing gas, that is, an oxygen concentration, and a high frequency power for generating plasma from the above described conditions.
  • step ST 13 is performed.
  • the first region R 1 is etched.
  • a processing gas is supplied into the processing container 12 from a gas source selected from the plurality of gas sources of the gas source group 40 .
  • the processing gas contains an inert gas.
  • the inert gas in an example, may be a rare gas such as, for example, Ar gas. Otherwise, the inert gas may be a nitrogen gas.
  • the exhaust device 50 is operated such that the pressure within the processing container 12 is set to a predetermined pressure.
  • the high frequency power is supplied from the first high frequency power supply 62 to the lower electrode LE.
  • the high frequency bias power is supplied from the second high frequency power supply 64 to the lower electrode LE.
  • step ST 13 various conditions in step ST 13 will be exemplified.
  • step ST 13 the plasma of the inert gas is generated, and ions are drawn into the wafer W.
  • the first region R 1 is etched by radicals of fluorocarbon included in the deposits DP (see, e.g., FIG. 10 ).
  • the above described operations of the respective units of the plasma processing apparatus 10 in step ST 13 , may be controlled by the controller Cnt.
  • the sequence SQ is carried out in a period including the time of exposing the second region R 2 .
  • step ST 11 of the sequence SQ as illustrated in FIG. 8 , the deposits DP are formed on the wafer W.
  • FIG. 8 illustrates a state where the first region R 1 is gradually etched, the second region R 2 is exposed, and deposits DP are formed on the second region R 2 .
  • the deposits DP protect the second region R 2 .
  • step ST 12 of the sequence SQ as illustrated in FIG. 9 , the amount of the deposits DP formed in step ST 11 is decreased.
  • step ST 13 of the sequence SQ the first region R 1 is etched by radicals of fluorocarbon included in the deposits DP.
  • the second region R 2 is exposed, and then the second region R 2 is protected by the deposits DP and the first region R 1 within the recess provided by the second region R 2 is slightly etched. Accordingly, as illustrated in FIG. 10 , a lower opening LO is gradually formed.
  • step STJ After step ST 13 is performed, it is determined whether a stop condition is satisfied in step STJ.
  • the stop condition is determined to be satisfied when the sequence SQ has been carried out a predetermined number of times.
  • step STJ when it is determined that the stop condition is not satisfied, the sequence SQ is carried out from step ST 11 .
  • step STJ when it is determined that a stop condition is satisfied, subsequently, step ST 5 is performed.
  • step ST 5 the first region R 1 is further etched.
  • a processing gas (a second processing gas) is supplied into the processing container 12 from a gas source selected from the plurality of gas sources of the gas source group 40 .
  • the processing gas contains a fluorocarbon gas.
  • the processing gas may further contain a rare gas, for example, Ar gas.
  • the processing gas may further contain an oxygen gas.
  • the exhaust device 50 is operated such that the pressure within the processing container 12 is set to a predetermined pressure.
  • the high frequency power is supplied from the first high frequency power supply 62 to the lower electrode LE, and the high frequency bias power is supplied from the second high frequency power supply 64 to the lower electrode LE. Meanwhile, in step ST 5 , a voltage having a negative voltage value may be applied to the upper electrode 30 from the power supply 70 .
  • step ST 5 the plasma of the processing gas is generated, and the first region R 1 within the recess is etched by the active species of fluorocarbon.
  • step ST 5 in the exemplary embodiment, as illustrated in FIG. 11 , the first region R 1 is etched until the bottom of the recess is exposed. That is, in step ST 5 , the plasma of the processing gas is continuously generated so that etching of the first region R 1 is continued to the bottom of the recess.
  • step ST 5 a condition for a mode in which etching of the first region R 1 by the active species of fluorocarbon is dominant, instead of formation of deposits of fluorocarbon, that is, a condition for an etching mode is selected.
  • the fluorocarbon gas used in step ST 5 is C 4 F 6 gas.
  • the fluorocarbon gas used in step ST 5 may contain at least one kind of C 4 F 8 gas and CF 4 gas.
  • the high frequency power for generating plasma used in step ST 5 may be set to be higher than the high frequency power for generating plasma used in step ST 11 . According to these examples, it is possible to realize the etching mode.
  • the high frequency bias power used in step ST 5 may also be set to be higher than the high frequency bias power used in step ST 11 .
  • the energy of ions to be drawn to the wafer W may be increased so that the first region R 1 may be etched at a high speed.
  • step ST 5 various conditions in step ST 5 will be exemplified.
  • step ST 5 is performed in a state where the second region R 2 is protected by the deposits DP formed by carrying out the sequence SQ.
  • step ST 5 the first region is further etched by the plasma of the fluorocarbon gas.
  • the etching rate of the first region R 1 in step ST 5 is higher than the etching rate of the first region R 1 in the sequence SQ. Accordingly, as compared to a processing time when the first region R 1 is etched to the bottom of the recess by repeatedly carrying out the sequence SQ, the processing time of the method MT is largely shortened. Thus, according to the method MT, it is possible to achieve both a scraping suppression of the second region R 2 , and a decrease of a processing time required for etching the first region R 1 .
  • FIG. 12 is a flow chart illustrating an etching method according to another exemplary embodiment.
  • FIG. 13 is a sectional view illustrating the workpiece after step ST 14 of the method illustrated in FIG. 12 is performed.
  • the method MT 2 illustrated in FIG. 12 is different from the method MT in that the sequence SQ further includes step ST 14 performed after step ST 13 is performed.
  • Step ST 14 is the same step as step ST 12 .
  • the conditions described in the processing in step ST 12 may be employed.
  • step ST 13 ions are drawn into the wafer W. Accordingly, substances constituting the deposits DP are released from the wafer W, and the substances are attached again to the wafer W so that, as illustrated in FIG. 10 , the deposits DP are formed to narrow the width of the opening MO and the lower opening LO.
  • the deposits DP in some cases, may clog the opening MO and the lower opening LO.
  • step ST 14 when step ST 14 is performed, the wafer W illustrated in FIG. 10 is exposed to active species of oxygen in the same manner as in step ST 12 . Accordingly, as illustrated in FIG. 13 , the deposits DP which narrow the width of the opening MO and the lower opening LO may be reduced so that the opening MO and the lower opening LO may be more reliably prevented from being clogged.
  • a high frequency power for generating plasma is supplied to the lower electrode LE, but the high frequency power may be supplied to the upper electrode 30 .
  • a plasma processing apparatus other than the plasma processing apparatus 10 may be used.
  • the method MT and the method MT 2 may be carried out using any plasma processing apparatus such as an inductively coupled plasma processing apparatus or a plasma processing apparatus for generating the plasma using surface waves such as microwaves.
  • step ST 11 the execution order of steps ST 11 , ST 12 , and ST 13 may be changed.
  • step ST 12 may be performed.

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KR102487054B1 (ko) * 2017-11-28 2023-01-13 삼성전자주식회사 식각 방법 및 반도체 장치의 제조 방법
TWI828187B (zh) 2021-06-22 2024-01-01 日商東京威力科創股份有限公司 蝕刻方法及電漿處理裝置
JP2023050972A (ja) 2021-09-30 2023-04-11 東京エレクトロン株式会社 エッチング方法及びプラズマ処理装置
JP2024033846A (ja) 2022-08-31 2024-03-13 東京エレクトロン株式会社 基板処理方法及びプラズマ処理装置

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