US20130228797A1 - Silicon carbide substrate and semiconductor device - Google Patents

Silicon carbide substrate and semiconductor device Download PDF

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US20130228797A1
US20130228797A1 US13/885,573 US201113885573A US2013228797A1 US 20130228797 A1 US20130228797 A1 US 20130228797A1 US 201113885573 A US201113885573 A US 201113885573A US 2013228797 A1 US2013228797 A1 US 2013228797A1
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silicon carbide
substrate
encapsulated
carbide substrate
stacking faults
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Hiroyuki Nagasawa
Takamitsu Kawahara
Kuniaki Yagi
Naoki Hatta
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Hoya Corp
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Hoya Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02447—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H01L21/0265—Pendeoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to a silicon carbide substrate used for a high performance semiconductor device.
  • a silicon carbide substrate which has an extremely low planar defects density on a specific crystal surface, and which can be preferably utilized as a material of a power semiconductor device having high efficiency and high breakdown voltage.
  • Silicon carbide has been used as a compound semiconductor material for high performance semiconductor device. However, in some cases, silicon carbide substrate includes high density of crystal defects.
  • a performance of the semiconductor device is significantly affected by such crystal defects included in the silicon carbide substrate.
  • the representative planar defects such as an anti-phase boundary and a stacking fault, cause a current leak or dielectric breakdown and remarkably reduce the performance of a power semiconductor device. Therefore, reduction of such planar defects is the main issue for silicon carbide substrate applicable to the device use.
  • the anti-phase boundaries disappear by controlling an orientation of a polar face.
  • atomic-level steps are introduced at equal intervals in one direction, and therefore propagation of the planar defects in a direction vertical to the introduced steps (in a direction crossing the steps) can be prevented by the step-flow during the silicon carbide hetero-epitaxial growth.
  • stacking faults density can be reduced with increasing the silicon carbide growth thickness.
  • the stacking faults density also can be reduced.
  • the stacking faults existed on the cubic silicon carbide (001) face are classified into two types by the difference of the polar face exposed on (001) surface. One is a stacking fault exposing a C-polar face on (001) surface and the other is exposing a Si-polar face.
  • the stacking fault exposing the C-polar face its surface energy is relatively lower than that of (001) surface. Therefore, the stacking fault exposing C-polar face is instable on (001) surface and tends to be self-vanished during the silicon carbide epitaxial growth.
  • FIG. 10 shows an enlarged ( ⁇ 110) cross-sectional image of the undulation formed on a Si(001) substrate.
  • the stacking faults 103 keep a mirror symmetrical relation each other. Consequently, stacking faults are continuously annihilated without allowing anisotropy of the propagating direction of the stacking faults described in silicon carbide epitaxial growth on the misoriented-Si(001) substrate.
  • the stacking faults exposing the Si-polar face are still remained in spite of working the above-mentioned annihilation mechanism. This is because the stacking faults exposing the Si-polar face are continuously occurred due to a lattice strain generated during the crystal growth.
  • the silicon carbide epitaxial growth two kinds of the lattice strain are mainly generated. One is caused by a temperature distribution in a substrate, and the other is caused by a lattice miss-matching due to annihilation of the stacking faults.
  • SBE Switch-Back-Epitaxy
  • FIG. 11 shows a lattice model of the staking fault exposing Si-polar face on a surface.
  • the stacking fault 112 included in the silicon carbide crystal 111 exposes Si-polar face 113 on a front surface, and C-polar face 114 on a back surface of the substrate. This fact indicates that an exposed surface of the stacking faults can be converted from Si-polar face to C-polar face by turning the substrate upside down. Since the C-polar face is instable and tends to be self-vanished during the crystal growth, the residual stacking faults exposing Si-polar face can be completely eliminated in principle by homoepitaxial growth of the cubic silicon carbide on the back surface of the substrate.
  • the stacking faults density is actually reduced by using SBE technique, however, complete elimination of the stacking faults is not achieved. This is because the additional stacking faults occurrence during a SBE growth process, which is mainly caused by the strains existing in the cubic silicon carbide substrate and a homo-epitaxial layer. Similarly to the silicon carbide epitaxial growth on the undulant-Si(001) substrate, two kinds of the strains, caused by the temperature distribution in the substrate surface and the lattice miss-matching due to annihilation of the stacking faults, are also generated during SBE growth. Hence, new stacking faults are continuously occurred in the silicon carbide layer to release such strains. Namely, it is quite difficult to fabricate the cubic silicon carbide substrate having extremely low stacking faults density, which is suitable for manufacture of the high performance device, without controlling the lattice strain generated during the crystal growth.
  • the undulations are formed not only in one direction but also in a direction orthogonal thereto on Si (001) substrate.
  • a smooth surface is obtained because the surface roughing due to the step-bunching oriented in one direction is avoidable by step-flow growth on the two directional steps formed at the slope of two orthogonal undulations.
  • the off-angle is also introduced not only in one direction but also in a direction orthogonal thereto, control of the orientation of the polar-face shown in the aforementioned non-patent document 2 is deteriorated and hence elimination of the anti-phase boundaries is not achieved.
  • the defect reducing technique for GaN epilayer is described.
  • the trigonal pyramid-like GaN domains are formed by GaN epitaxial growth through the equilateral triangular windows formed on SiO2 masked GaN seed layer on a sapphire substrate. The sides of these triangular windows correspond to three equivalent (11-20) planes.
  • lateral crystal growth is performed on the trigonal pyramid-like GaN domains.
  • many dislocations are vertically extended from a GaN seed layer to the pyramid-like domains.
  • the dislocations which reach the slope of the pyramid-like GaN domains can be eliminate due to changing their extending direction from vertical to lateral direction. Consequently, reduction of dislocation density in the additional GaN epilayer is achieved.
  • the adjoining pyramid-like GaN domains are merged each other, the dislocations extending to lateral direction are changed their extending direction to vertical again. Consequently, high dislocation density region are formed on the surface of the additional GaN epilayer.
  • the planar defect such as stacking fault and anti-phase boundaries, propagate in parallel to a specific orientation and their propagation directions are independent of growth direction. Therefore, the propagation direction of the planar defects cannot be controlled through the growth direction.
  • Patent Document 1
  • Patent Document 2
  • Patent Document 3
  • Patent Document 4
  • Non-Patent Document 1
  • Non-Patent Document 2
  • Non-Patent Document 3
  • the object of the present invention is to provide a silicon carbide substrate with low planar defects density for a high performance semiconductor device use. This object is achieved by reducing planar defects density without allowing anisotropy of propagating direction of the stacking faults, and blocking propagation of the stacking faults caused by a lattice strain and a thermal strain during crystal growth.
  • the present invention proposes the following matters.
  • the present invention provides a silicon carbide substrate (corresponding to a silicon carbide substrate 1 of FIG. 1 ) having at least one or more main surfaces (corresponding to main surfaces 12 of FIG. 1 for example), comprising:
  • step of performing homo-epitaxial growth includes the step of satisfying formula (2) described below:
  • r g[001] represents a growth rate in [001] direction
  • r g[110] represents a growth rate in [110] direction
  • the annihilation process between the counter-propagated stacking faults has been utilized.
  • the probability of occurrence of the annihilation is proportional to the residual stacking faults density, and therefore as the number of residual stacking faults is reduced, a defect reduction effect (decreasing rate of stacking faults density per unit thickness) is also reduced, and is finally lost.
  • encapsulated regions are introduced in a silicon carbide substrate to reduce the stacking faults density without depending on the above-mentioned annihilation process.
  • the encapsulated regions can act as obstacles and inhibit the propagation of the stacking faults.
  • the stacking faults can be propagated to a specific direction only in a single crystal.
  • the Young modulus of the encapsulated regions is less than that of the silicon carbide, a thermal strain or a lattice strain generated during the crystal growth can be absorbed by the encapsulated regions. Even if the stacking faults are generated, their propagation is prevented at the interface as above described. Thus, by using the present invention, effective reduction of the stacking faults is achieved without affection of some lattice strains generated during the crystal growth.
  • each encapsulated region is constituted including at least one of the silicon, carbon, nitrogen, hydrogen, helium, neon, argon, krypton, and xenon.
  • the hollow region also includes a vacuum state.
  • FIG. 1 is a cross-sectional view of a silicon carbide substrate according to the present invention.
  • FIG. 2 is a plane-view of a front surface of a cubic silicon carbide substrate covered with the lattice-shaped SiO 2 mask according to a second embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of the cubic silicon carbide substrate.
  • FIG. 4 is a cross-sectional view of the cubic silicon carbide substrate.
  • FIG. 5 is a cross-sectional view of the cubic silicon carbide substrate.
  • FIG. 6 is a cross-sectional view of a cubic silicon carbide substrate according to a third embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of the cubic silicon carbide substrate.
  • FIG. 8 is a cross-sectional view of the cubic silicon carbide substrate.
  • FIG. 9 is an overview of a Si substrate with undulations having ridges formed in parallel to [ ⁇ 110] direction, according to a conventional example.
  • FIG. 10 is a cross-sectional view of the stacking faults distribution in the silicon carbide epilayer grown on the Si substrate with undulations.
  • FIG. 11 is a lattice image of the stacking fault in the cubic silicon carbide.
  • FIG. 12 is a schematic image for describing the mechanism of reducing the stacking faults density.
  • FIG. 13 is a schematic image for describing the mechanism of reducing the stacking faults density.
  • FIG. 1 is a cross-sectional view of a silicon carbide substrate according to the present invention.
  • a main surface 12 being a largest portion of the exposed surfaces of the silicon carbide substrate 1 , is formed in parallel to (001) face.
  • the silicon carbide substrate 1 is a plate-shaped crystal with a back surface in parallel to the main surface 12 .
  • Encapsulated regions 13 are distributed in an approximately parallel with the main surface 12 and preferably the plurality of encapsulated regions 13 exist uniformly inside of a cubic silicon carbide 11 , which is a component of the silicon carbide substrate 1 . Furthermore, a plurality of encapsulated regions 13 are distributed uniformly within 100 ⁇ m, preferably within 50 ⁇ m, and further preferably within 20 ⁇ m below the main surface 12 . Preferably, each encapsulated region 13 is constituted including at least one of silicon, carbon, nitrogen, hydrogen, helium, neon, argon, krypton, and xenon, or is formed as a hollow region (such as vacuum space). Furthermore, a layer in which the encapsulated regions 13 are distributed is approximately parallel to the main surface 12 . The side walls of the encapsulated regions 13 , those who are defined as the surfaces not approximately parallel to the main surface 12 , are approximately parallel to ⁇ 110 ⁇ planes.
  • the stacking faults density can be effectively reduced if a closest-packed plane to which the stacking faults 14 are propagated and the sidewall of encapsulated regions 13 are not parallel to each other, and the interior angle ⁇ between the stacking faults 14 and the encapsulated regions 13 is larger than 0 degree and less than 90 degrees.
  • the main surface 12 is parallel to (001) face, and the side walls of the encapsulated region 13 are approximately parallel to ⁇ 110 ⁇ planes.
  • the stacking faults 14 included in the cubic silicon carbide 11 are propagated in parallel to ⁇ 111 ⁇ planes corresponding to the closest-packed plane. Therefore, the interior angle ⁇ between the stacking faults 14 and the encapsulated regions 13 will be 35.3 degrees.
  • each of the dimensions concerning the encapsulated region 13 is desirable to be satisfy the following conditions, respectively.
  • the interval W it is desirable to be 100 nm or more and 100 ⁇ m or less, preferably 1 ⁇ m or more and 50 ⁇ m or less, and further preferably 2 ⁇ m or more and 20 ⁇ m or less in length. This is because when interval W is extremely small, processing of formation of the encapsulated regions 13 becomes to be difficult. Furthermore, a substrate resistance increases due to increasing of the volume occupancy of the encapsulated regions 13 in the substrate. When interval W is extremely large, the height H is also required to be extremely large value to satisfy the formula (1). Consequently, the thermal strain can't be completely absorbed due to decreasing of the volume occupancy of the encapsulated regions 13 in the substrate.
  • the height H its value is given by the interval W and formula (1).
  • the thermal strain can't be completely absorbed due to decreasing of the volume occupancy of the encapsulated regions 13 in the substrate.
  • the height H is extremely large (for example, when height H is 100 ⁇ m or more), processing of formation of the encapsulated regions 13 becomes difficult.
  • a substrate resistance increases due to increasing of the volume occupancy of the encapsulated regions 13 in the substrate.
  • the width S when the width S is extremely small, processing of formation of the encapsulated regions 13 becomes difficult. Furthermore, the thermal strain can't be completely absorbed due to decreasing of the volume occupancy of the encapsulated regions 13 in the substrate.
  • the width S is also desirable to be 100 nm or more and 100 ⁇ m or less, preferably 1 ⁇ m or more and 50 ⁇ m or less, and further preferably 2 ⁇ m or more and 20 ⁇ m or less in length.
  • a depth from the main surface 12 to the encapsulated regions 13 (distance from the main surface to top of the encapsulated region 13 ), represented by T, also has desired value.
  • T depth from the main surface 12 to the encapsulated regions 13
  • the encapsulated regions 13 are possibly exposed on the main surface 12 due to the damage of the top layer caused by their poor mechanical strength.
  • an activating region of semiconductor device is formed on the extremely thin top layer on the encapsulated regions 13 , a uniform current flow through the substrate may be disturbed and it can cause local overheat or breakdown.
  • depth T is desirable to be 100 nm or more and 100 ⁇ m or less, preferably 1 ⁇ m or more and 50 ⁇ m or less, and further preferably 10 ⁇ m or more and 30 ⁇ m or less in depth.
  • the height H is desirable to be five times or more larger than the width S and the plane area of the encapsulated region 13 parallel to the main surface 12 is desirable to be 1/10 or less of the entire area of the main surface 12 .
  • the side wall being a part of the encapsulated region, takes a major role for reducing stacking faults density, whole shape of the encapsulated regions has a lot of flexibility in the design as long as satisfying the aforementioned condition for the side wall and each dimension indicated in FIG. 1 .
  • the encapsulated regions having a cross-sectional structure shown in FIG. 1 both of a line-space structure and a mesa structure are applicable, furthermore, each encapsulated region may also be connected inside the substrate without isolation.
  • the following method is available for example.
  • Undulation slopes parallel in [ ⁇ 110] direction are formed on Si(001) substrate as shown in the aforementioned patent document 2 and non-patent document 2.
  • a maximum angle of this slope is desirable to be 2 degrees or more and 90 degrees or less. This is because, when the maximum angle is less than 2 degrees, an area of the polar face exposed at the edge of atomic steps becomes negligibly small compared with the area of non-polar (001) surface. Consequently, the defect reducing mechanism for anti-phase boundaries described in the silicon carbide epitaxial growth on the misoriented-Si(001) substrate does not work well. Meanwhile, when the maximum angle exceeds 90 degrees, the step-flow epitaxial growth is inhibited on the reverse tapered slopes.
  • slopes of the adjacent undulations are continuously connected like a sinusoidal wave. Namely, the inclination angles of bottom and top of the undulations are 0 degree, and the inclination angle of the slope between bottom and top of the undulation is continuously varied from 0 degree to the maximum angle.
  • the cubic silicon carbide is grown on the aforementioned substrate.
  • CVD, MBE, and LPE, etc. are available for cubic silicon carbide growth
  • the flow rate of Si-source and C-source are desirable to be individually adjustable in any case.
  • supply ratios of the Si-source and C-source are preferably adjustable by precisely adjusting gas flow rates.
  • a specific crystal face is oriented in a specific orientation. In the case of Si-polar face, it is oriented to (111) plane or ( ⁇ 1-11) plane, and the C-polar face oriented to ( ⁇ 111) plane or (1-11) plane.
  • the anti-phase boundary can be eliminated.
  • the stacking faults are remained on the substrate. All of them are distributed in ⁇ 111 ⁇ planes, corresponding to the closest-packed plane, and intersect with the main surface (001) surface at an angle of 54.7 degrees.
  • a material and a thickness of the mask are suitably selected in consideration of a stopping power against ion implantation, so that implanted ions are not passed through the mask pattern as described later.
  • ions of any one of hydrogen, helium, neon, argon, krypton, and xenon are implanted.
  • Acceleration energy for implantation is suitably calculated so that a penetration depth of the ions is set to 1 ⁇ m or more and 20 ⁇ m or less.
  • the implantation dose of the ions is determined so as to exceed a solubility limit in the cubic silicon carbide, and is preferably determined to obtain a density of 10 21 /cm 3 .
  • the implantation doze of the ion is determined to be 10 17 /cm 2 when the penetration depth of the ion is 10 ⁇ m.
  • cubic silicon carbide is grown on the main surface with similar condition of the aforementioned one.
  • the growth thickness of the cubic silicon carbide is determined so as to ensure the desirable value of depth T, which is the distance from the main surface to top of the encapsulated region shown in FIG. 1 .
  • the growth thickness is given by the subtraction from the desirable depth T to a minimum penetration depth in the ion implantation corresponding to the top position of the encapsulated region. For example, when the desirable depth T is 10 ⁇ m and the minimum penetration depth in the ion implantation is 1 ⁇ m, the grown thickness will be 9 ⁇ m.
  • the encapsulated regions are formed by the education of the ion species implanted over the solubility limit in the cubic silicon carbide.
  • Such encapsulated regions have the shape based on the aforementioned mask pattern, the height H determined by the penetration depth in the ion implantation and the side walls approximately parallel to ⁇ 110 ⁇ plane.
  • the polishing scratches were introduced on the surface of 4-inch Si(001) substrate by rubbing with the abrasive grains in one direction.
  • Diamond slurry with a grain size of about 9 ⁇ m was used as the abrasive grains for introducing the polishing scratches.
  • a commercially available polishing cloth (EngisM414) soaked with this diamond slurry, innumerable polishing scratches which are approximately parallel with each other, were formed.
  • a pressure for rubbing the surface of the substrate in a prescribed direction was set to 0.2 kg/cm 2 , and the polishing cloth was reciprocally moved about 300 times in one direction to introduce the polishing scratches.
  • the following substrate cleaning was performed. After ultrasonic cleaning with pure water, the processed substrate was dipped in a mixed solution of a hydrogen peroxide solution and a sulfuric acid at a ratio of 1:1, and then a hydrofluoric acid solution. Then, a thermal oxide layer with a thickness of about 0.5 ⁇ m was formed on the processed substrate by sacrificial thermal oxidation, and thereafter the thermal oxide layer was removed by dilute hydrofluoric acid.
  • the undulations which are continuous wavy shape parallel to [ ⁇ 110] direction shown in FIG. 9 , with a depth of a groove being 30 to 50 nm, a width of being 1 to 2 ⁇ m, and a gradient of being 3 to 5 degrees were obtained.
  • the undulant-Si(001) substrate was heated up from room temperature to 1350 degree C. in a CVD apparatus. During heating up process, a mixed gas of C 2 H 2 and H 2 was continuously supplied to form an ultrathin initial silicon carbide layer. The flow rates of C 2 H 2 and H 2 and the growth pressure are shown in table 1.
  • the silicon carbide growth was performed for 8 hours under the growth conditions shown in Table 2 to grow 450- ⁇ m-thick cubic silicon carbide on the undulant-Si(001) substrate. Subsequently, wet etching of the undulant-Si(001) substrate with a mixed acid of hydrofluoric acid and nitric acid was performed to obtain free-standing 450- ⁇ m-thick single crystal cubic silicon carbide substrate.
  • the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 2 ⁇ 10 5 /cm 2 and no anti-phase boundaries were observed on the entire main surface of the cubic silicon carbide substrate.
  • each side of an individual square pattern was aligned to be parallel to ⁇ 110> orientation of the cubic silicon carbide substrate.
  • a width of each side of the individual square pattern (corresponding to the interval W between the adjoining encapsulated regions 13 in FIG. 1 ) is 5 ⁇ m, and its interval (corresponding to the width S of the encapsulated region 13 in FIG. 1 ) is 2 ⁇ m, respectively.
  • the dry etching of the Ni layer with a patterned photoresist mask was performed by F-plasma of 100 W. After that, the photoresist mask was completely removed by oxygen plasma. Finally, the lattice-shaped Ni mask with 5 ⁇ m square apertures aligned with keeping an interval of 2 ⁇ m was obtained. Next, proton ions were implanted vertically to the main surface. Wherein, the acceleration energy of protons is varied in a range of 10 keV to 400 keV, and their doses were determined by multiplying a target concentration 10 21 /cm 3 by the penetration depth of the protons.
  • the proton irradiation regions (encapsulated regions) with a concentration of 10 21 /cm 3 extending by 5 to 20 ⁇ m from the main surface were obtained.
  • height H of the encapsulated region was 15 ⁇ m, and the side walls of them were approximately parallel to ⁇ 110 ⁇ planes.
  • 5- ⁇ m-thick cubic silicon carbide layer was homo-epitaxially grown on the proton implanted substrate for 5 minutes under the growth conditions shown in Table 2. During this growth process, hydrogen was precipitated in the encapsulated regions at a depth of 10 to 25 ⁇ m from the surface.
  • the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 2 ⁇ 10 2 /cm 2 was observed. In this embodiment, the stacking faults density could be reduced by 3 orders of magnitude by introducing the encapsulated regions. Furthermore, it was clearly observed that the propagation of the stacking faults induced by lattice strains is inhibited at the sidewalk of encapsulated regions.
  • the undulations were formed on Si (001) substrate by rubbing with diamond slurry in one direction.
  • the present invention is not limited thereto.
  • the combination of a lithography process and etching process could provide similar effects if the undulations have the same cross-sectional shape and arrangements as the first embodiment.
  • SiH 2 Cl 2 and C 2 H 2 were used as source gases for cubic silicon carbide growth.
  • the present invention is not limited thereto.
  • SiH 4 , SiCl 4 , and SiHCl 3 , etc. can be used as a source gas of silicon
  • CH 4 , C 2 H 4 , C 2 H 6 , and C 3 H 8 , etc. can be used as the source gas of carbon.
  • the cubic silicon carbide (001) face is used as the main surface of the silicon carbide substrate.
  • the present invention is not limited thereto.
  • ⁇ 111 ⁇ face, ⁇ 110 ⁇ face, or ⁇ 211 ⁇ face are applicable to the side wails of the encapsulated regions.
  • a hexagonal silicon carbide ⁇ 0001 ⁇ face is used as the main surface, ⁇ 11-20 ⁇ face or ⁇ 1100 ⁇ face are applicable to the side walls of the encapsulated regions.
  • the closest-packed plane to which the stacking faults are propagated is corresponded to (0001) face, hence the stacking faults intersect with the main surface at an angle in the range of 30-60 degrees. Therefore, by executing the aforementioned each processes of this embodiment, similar effects as this embodiment can be obtained.
  • protons are used as the implantation ions.
  • the present invention is not limited thereto.
  • implantation of the other ion species, such as He, Ne, Ar, Kr, Xe, and N, or a combination of them provides the similar effect as this embodiment if their penetration depth can satisfy a target depth (corresponding to height H of the encapsulated region 13 in FIG. 1 ).
  • the undulations were formed on the entire surface of 4-inch Si(001) substrate by rubbing with the abrasive grains in [ ⁇ 110] direction. Subsequently, the residual abrasive grains on the processed surface were cleaned off by the same cleaning process described in the first embodiment. Then, 0.5- ⁇ m-thick thermal oxide layer was formed on the undulant Si (001) substrate by sacrificial thermal oxidation and thereafter the thermal oxide layer was removed by a dilute hydrofluoric acid.
  • the undulations which are continuous wavy shape parallel to [ ⁇ 110] direction shown in FIG. 9 , with a depth of a groove being 30-50 nm, a width of being 1-2 ⁇ m, and a gradient of being 3-5 degrees were obtained.
  • an ultrathin initial silicon carbide layer was grown under the growth condition in Table 1 described in the first embodiment.
  • 113-um-thick cubic silicon carbide layer indicated by part 31 in FIG. 3 , was grown for 2 hours under the growth conditions in Table 2.
  • the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 8 ⁇ 10 5 /cm 2 and no anti-phase boundaries were observed on entire main surface.
  • thermal SiO 2 mask for selective-silicon carbide growth
  • 100-nm-thick thermal SiO 2 layer was formed on entire main surface by dry oxidation at 1100 degree C. for 30 minutes.
  • the positive photoresist layer of 2 ⁇ m in thickness was coated on the surface of the thermal SiO 2 layer, and a square array pattern was formed by exposure to ultraviolet ray (g-line of mercury) using a photomask.
  • each side of an individual square pattern was aligned to be parallel to ⁇ 110> orientation of the cubic silicon carbide substrate.
  • a width of each side of the individual square pattern (corresponding to the width S of the encapsulated region 13 in FIG. 1 ) is 2 ⁇ m, and its interval (corresponding to the interval W between the adjoining encapsulated regions 13 in FIG. 1 ) is 5 ⁇ m, respectively.
  • the dry etching of the thermal oxide layer with a patterned photoresist mask was performed by F-plasma of 100 W. After that, the photoresist mask was completely removed by oxygen plasma. Finally, the lattice-shaped thermal SiO 2 mask, shown in FIG. 2 , with a plurality of square apertures 22 aligned with keeping constant interval 21 were obtained.
  • FIG. 3 shows a cross-sectional view of the cubic silicon carbide substrate after this growth process.
  • the silicon carbide homo-epitaxial layer 33 was selectively grown on a silicon carbide layer 31 through the apertures of the lattice-shaped SiO 2 mask 32 .
  • the substrate through the above described processes was dipped into a mixed acid of hydrofluoric acid and nitric acid to remove both of the thermal SiO 2 mask on surface and Si(001) layer on backside of the substrate. Consequently, as shown in FIG. 4 , a plurality of isolated regions of single crystal silicon carbide 33 with a height of 10 ⁇ m, width of 2 ⁇ m, and interval of 5 ⁇ m were obtained on the 113- ⁇ m-thick silicon carbide layer 31 .
  • FIG. 5 shows the cross-sectional image of the cubic silicon carbide substrate after this additional growth.
  • 10- ⁇ m-thick silicon carbide layer 41 was homo-epitaxially grown on the isolated regions 33 and bridged among them. Consequently, the encapsulated regions 42 with a width of 2 ⁇ m, an interval of 5 ⁇ m, and a height of 10 ⁇ m were obtained at 10 ⁇ m below the main surface.
  • the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy.
  • the stacking faults density 2 ⁇ 10 2 /cm 2 was observed on entire main surface.
  • the stacking faults density could be reduced by about 3 orders of magnitude by introducing the encapsulated regions.
  • the propagation of the stacking faults induced by lattice strains is inhibited at the sidewalls of encapsulated regions, and also observed that the encapsulated regions are formed while disappearing the stacking faults.
  • the cubic silicon carbide (001) face is used as the main surface of the silicon carbide substrate.
  • the present invention is not limited thereto.
  • the hexagonal silicon carbide can also be used with ⁇ 11-20 ⁇ plane and ⁇ 03-38 ⁇ plane as the main surfaces.
  • the closest-packed plane to which the stacking faults are propagated is corresponded to (0001) face, hence the stacking faults intersect the main surface at an angle in the range of 30-60 degrees. Therefore, by executing the aforementioned each processes of this embodiment, similar effects as this embodiment can be obtained.
  • the encapsulated regions were formed at 10 ⁇ m below the main surface by the additional homo-epitaxial growth for 60 minutes under the condition shown in Table 3.
  • the location of the encapsulated regions depends on the thickness of the additional growth layer 41 and its location was closely related with the effect of reducing the stacking fault density on the main surface.
  • Table 4 shows the relationship between the location of the encapsulated regions (depth of the encapsulated region) and the stacking faults density remaining on the main surface. It was found that an effect of reducing the stacking faults density becomes stronger with decreasing the depth of encapsulated region, especially 100 ⁇ m or below.
  • Al ions were implanted to an entire surface of the homo-epitaxial layer to form p-n junction.
  • An implantation depth is 1 ⁇ m, and an acceleration energy is adjusted in a range of 30-700 keV to obtain the constant doping profile of 1 ⁇ 10 18 /cm 3 in a depth direction.
  • activation annealing was applied to the surface at 1600 degree C. for 10 minutes in Ar atmosphere.
  • an array of Ni circular masks with a diameter of 100 ⁇ m was fabricated on the surface by a photolithography technique, and then rf-RIE was applied thereto for 5 minutes at 200 W with supplying a gas of CF 4 (100 sec)+O 2 (20 sccm).
  • Table 6 shows the leakage current density at reverse voltage of 600V for mesa-type p-n diodes fabricated on the substrates listed in Table 4. Reduction of a leakage current density was clearly demonstrated at a depth of the encapsulated region of 100 ⁇ m or below, particularly 50 ⁇ m.
  • cubic silicon carbide is used as the substrate in this embodiment, however, similar effects as this embodiment can be provided to the hexagonal silicon carbide substrate.
  • a mechanism of reducing the stacking faults density on the surface of the substrate according to the second embodiment will be described.
  • the mechanism of reducing the stacking faults in this embodiment was consisted of the following two manufacturing processes.
  • FIG. 12 shows the cross-sectional image of isolated regions 210 formed on the (001) surface of cubic silicon carbide substrate 200 .
  • isolated regions 210 are the elevated regions bounded by sidewalls of ⁇ 110 ⁇ planes. It is significantly preferable for the isolated regions 210 to have a side wall of ⁇ 110 ⁇ plane in the case of using the cubic silicon carbide (001) substrate. If the above condition is satisfied, there is no other condition with respect to the structure of the isolated regions 210 . For example, a line-space structure or simple mesa-structure is applicable.
  • Such isolated regions 210 can be fabricated through selective-growth or selective-etching process on mask-patterned silicon carbide substrate 200 . Hereafter, it will be mainly explained in the case of the isolated regions 210 fabricated through selective-etching process on the cubic silicon carbide (001) substrate.
  • FIG. 13 shows schematic diagram of reduction of the stacking faults density by homo-epitaxial growth.
  • the stacking faults in the cubic silicon carbide (001) substrate 200 propagate at an angle of 54.7 degrees to the surface during the homo-epitaxial growth.
  • the stacking faults density can be significantly reduced by the following two mechanisms, named as mechanism M 1 and mechanism M 2 .
  • the mechanism M 1 will be described. As shown in FIG. 13 , when the silicon carbide is homo-epitaxially-grown on the SiC substrate 200 , stacking fault SF 1 , which is initially exposed on the surface without the isolated regions 210 , is propagated into the homo-epitaxial layer. However, when the homo-epitaxial layer is grown up to the surface indicated by the dashed line 201 , the stacking fault SF 1 is inhibited its propagation into the isolated region 211 by the side walls. Such a reducing method of the stacking faults density is called as a mechanism M 1 . Note that when SiC is selectively grown on the mask-patterned substrate, as shown in the second embodiment, propagation of SF 1 is inhibited by the mask on the surface.
  • the mechanism M 2 will be described. As shown in FIG. 13 , the silicon carbide is homo-epitaxially grown on the SiC substrate 200 , the stacking fault SF 2 , which is initially exposed on the surface within the isolated regions 210 , is propagated into the homo-epitaxial layer.
  • the position of the stacking fault SF 2 becomes closer to an edge of the isolated domain 211 than before. This is because the stacking fault SF 2 moves toward the edge during the growth.
  • the stacking fault SF 2 reaches the side wall of the isolated domain 212 (i.e., SF 2 reaches the encapsulated region) and being terminated there.
  • Such a reducing method of the stacking faults density is called as the mechanism M 2 .
  • the propagation rate of the stacking fault SF 2 toward the edge of the isolated region should be faster than the growth rate of sidewalls in the ⁇ 110> direction.
  • This condition is expressed by the following formula (2), wherein r g[001] indicates a growth rate in [001] direction and r g[110] indicates a growth rate in ⁇ 110> direction, respectively.
  • the ratio of a growth rate to satisfy the aforementioned formula can be controlled by adjusting a growth temperature, a supply ratio of a source gas, and a growth pressure.
  • the undulations were formed on the entire surface of 4-inch Si(001) substrate by rubbing with the abrasive grains in [ ⁇ 110] direction. Subsequently, the residual abrasive grains on the processed surface were cleaned off by the same cleaning process described in the first embodiment. Then, 0.5- ⁇ m-thick thermal oxide layer was formed on the undulant Si (001) substrate by sacrificial thermal oxidation and thereafter the thermal oxide layer was removed by a dilute hydrofluoric acid.
  • the undulations which are continuous wavy shape parallel to [ ⁇ 110] direction shown in FIG. 9 , with a depth of a groove being 30-50 nm, a width of being 1-2 ⁇ m, and a gradient of being 3-5 degrees were obtained,
  • an ultrathin initial silicon carbide layer was grown under the growth condition in Table 1 described in the first embodiment.
  • 113-um-thick cubic silicon carbide layer indicated by part 31 in FIG. 3 , was grown for 2 hours under the growth conditions in Table 2.
  • the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 8 ⁇ 10 5 /cm 2 and no anti-phase boundaries were observed on entire main surface,
  • thermal SiO 2 mask for selective-silicon carbide growth
  • 100-nm-thick thermal SiO 2 layer was formed on entire main surface by dry oxidation at 1100 degree C. for 30 minutes.
  • the positive photoresist layer of 2 ⁇ m in thickness was coated on the surface of the thermal SiO 2 layer, and a square array pattern was formed by exposure to ultraviolet ray (g-line of mercury) using a photomask.
  • each side of an individual square pattern was aligned to be parallel to ⁇ 110> orientation of the cubic silicon carbide substrate.
  • a width of each side of the individual square pattern (corresponding to the width S of the encapsulated region 13 in FIG. 1 ) is 2 ⁇ m, and its interval (corresponding to the interval W between the adjoining encapsulated regions 13 in FIG. 1 ) is 5 ⁇ m, respectively.
  • the dry etching of the thermal oxide layer with a patterned photoresist mask was performed by F-plasma of 100 W. After that, the photoresist mask was completely removed by oxygen plasma. Finally, the lattice-shaped thermal SiO 2 mask, shown in FIG. 2 , with a plurality of square apertures 22 aligned with keeping constant interval 21 were obtained.
  • the substrate through the above described processes was dipped into a mixed acid of hydrofluoric acid and nitric acid to remove both of the thermal SiO 2 mask on surface and Si(001) layer on backside of the substrate. Consequently, as shown in FIG. 4 , a plurality of isolated regions of single crystal silicon carbide with a height of 10 ⁇ m, width of 2 ⁇ m, and interval of 5 ⁇ m were obtained on the 113- ⁇ m-thick silicon carbide layer.
  • FIG. 6 shows the cross-sectional image of the cubic silicon carbide substrate after this polycrystalline silicon growth.
  • 20- ⁇ m-thick polycrystalline silicon layer 53 was grown on both of surfaces of the isolated regions 52 and the valley between them.
  • FIG. 7 shows the cross-sectional image of the cubic silicon carbide substrate after this polishing process.
  • FIG. 8 shows the cross-sectional image of the cubic silicon carbide substrate after this homo-epitaxial growth.
  • 10- ⁇ m-thick silicon carbide layer 54 was homo-epitaxially grown on the isolated regions 52 and covered over the polycrystalline layer 53 . Consequently, the encapsulated regions 53 made of the polycrystalline silicon with a width of 2 ⁇ m, an interval of 5 ⁇ m, and a height of 10 ⁇ m were obtained at 10 ⁇ m below the main surface.
  • the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy.
  • the stacking faults density 2 ⁇ 10 2 /cm 2 was observed on entire main surface.
  • the stacking faults density could be reduced by about 3 orders of magnitude by introducing the encapsulated regions.
  • the propagation of the stacking faults induced by lattice strains is inhibited at the sidewalls of encapsulated regions, and also observed that the encapsulated regions are formed while disappearing the stacking faults.
  • the encapsulated region consists of polycrystalline silicon.
  • the present invention is not limited thereto.
  • the other materials such as single crystal silicon, graphite, diamond-like carbon or silicon nitride provides the similar effect as this embodiment.
  • the cubic silicon carbide (001) face is used as the main surface of the silicon carbide substrate.
  • the present invention is not limited thereto.
  • the hexagonal silicon carbide can also be used with ⁇ 11-20 ⁇ plane and ⁇ 03-38 ⁇ plane as the main surfaces.
  • the closest-packed plane to which the stacking faults are propagated is corresponded to (0001) face, hence the stacking faults intersect the main surface at an angle in the range of 30-60 degrees. Therefore, by executing the aforementioned each processes of this embodiment, similar effects as this embodiment can be obtained.
  • the undulations were formed on the entire surface of 4-inch Si(001) substrate by rubbing with the abrasive grains in [ ⁇ 110] direction. Subsequently, the residual abrasive grains on the processed surface were cleaned off through the following substrate cleaning. After ultrasonic cleaning with pure water, the processed substrate was dipped into a mixed solution of a hydrogen peroxide solution and a sulfuric acid at a ratio of 1:1, and then a hydrofluoric acid solution
  • a thermal oxide layer with a thickness of about 0.5 ⁇ m was formed on the processed substrate by sacrificial thermal oxidation, and thereafter the thermal oxide layer was removed by dilute hydrofluoric acid.
  • the undulations which are continuous wavy shape parallel to [ ⁇ 110] direction shown in FIG. 9 , with a depth of a groove being 30 to 50 nm, a width of being 1 to 2 ⁇ m, and a gradient of being 3 to 5 degrees were obtained.
  • an ultrathin initial silicon carbide layer was grown under the growth condition in Table 1 described in the first embodiment.
  • the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 8 ⁇ 10 5 /cm 2 and no anti-phase boundaries were observed on entire main surface.
  • 500-nm-thick alumina layer was deposited on entire main surface of the silicon carbide substrate by RF-sputtering at room temperature.
  • Polycrystalline alumina was used as a target and argon gas was used as a sputtering gas.
  • applied RF power was 150 W and argon pressure was kept at 4 ⁇ 10 ⁇ 3 Torr.
  • each side of an individual square pattern was aligned to be parallel to ⁇ 110> orientation of the cubic silicon carbide substrate.
  • a width of each side of the individual square pattern (corresponding to the width S of the encapsulated region 13 in FIG. 1 ) is 2 ⁇ m, and its interval (corresponding to the interval W between the adjoining encapsulated regions 13 in FIG. 1 ) is 5 ⁇ m, respectively.
  • the dry etching of the alumina layer with a patterned photoresist mask was performed by F-plasma of 100 W. After that, the photoresist mask was completely removed by oxygen plasma. Subsequently, the anodization was applied to the silicon carbide surface through the apertures of the alumina mask. Through the anodization under the condition in Table. 8, a plurality of porous silicon carbide regions having a width of 2 ⁇ m, an interval of 5 ⁇ m, and a depth of 10 ⁇ m were obtained. Wherein, the obtained porous silicon carbide had average porosity of 30%, and its depth was controlled by adjusting an applied voltage.
  • 10- ⁇ m-thick cubic silicon carbide layer was homo-epitaxially grown under the growth conditions shown in the aforementioned Table 2. Consequently, the encapsulated region made of a porous silicon carbide layer was formed at a depth of 10 to 20 ⁇ m from the main surface.
  • the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy.
  • the stacking faults density 2.5 ⁇ 10 2 /cm 2 was observed on entire main surface.
  • the stacking faults density could be reduced by about 3 orders of magnitude by introducing the encapsulated regions. Furthermore, it was clearly observed that the propagation of the stacking faults induced by lattice strains is inhibited at the sidewalls of encapsulated regions.
  • the silicon carbide substrate that can be preferably used as the substrate for the semiconductor device, by introducing the encapsulated regions in a suitable depth from the main surface, with their desired width, height, and interval, thereby blocking the stacking faults propagation in parallel to the closest-packed plane.

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