WO2012067105A1 - 炭化珪素基板、半導体素子ならびに炭化珪素基板の製造方法 - Google Patents
炭化珪素基板、半導体素子ならびに炭化珪素基板の製造方法 Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/36—Carbides
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
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- H01L21/02381—Silicon, silicon germanium, germanium
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
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- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H01L21/02447—Silicon carbide
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02612—Formation types
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Definitions
- the present invention relates to a silicon carbide substrate used for a high-performance semiconductor element.
- the present invention provides a silicon carbide substrate that can be preferably used as a material for a power semiconductor element having a remarkably low surface defect density on a specific surface of a crystal and having a high efficiency and a high breakdown voltage.
- Silicon carbide has begun to be used as compound semiconductor crystals that serve as substrates for high-performance semiconductor elements.
- the silicon carbide substrate which is a substrate using silicon carbide, may include lattice defects.
- Lattice defects contained in the silicon carbide substrate greatly affect the performance of the semiconductor element. For example, surface defects such as anti-phase region boundaries and stacking faults cause current leakage and dielectric breakdown, and significantly reduce the performance of power semiconductor elements. For this reason, reduction of the surface defect density is desired for the silicon carbide substrate.
- a method for reducing surface defects when forming a silicon carbide substrate will be described.
- a defect density reducing method when heteroepitaxially growing silicon carbide on a Si substrate for example, a method of controlling the thickness of silicon carbide shown in Patent Document 1 or Si Patent shown in Non-Patent Document 1
- Non-Patent Document 1 a so-called off-substrate having an angle (off-angle) of about several degrees in the [011] direction of the Si (100) substrate is used.
- the orientation direction is controlled to eliminate the antiphase region boundary surface. According to this, since the atomic level steps are introduced at equal intervals in one direction by giving a slight tilt to the substrate, the direction perpendicular to the introduced steps (direction crossing the steps) during epitaxial growth by the step flow ) Can suppress the propagation of surface defects.
- the stacking fault propagates in the direction parallel to the equivalent ⁇ 111 ⁇ plane in four directions with the growth, but the stacking faults facing each other are associated with the growth. At that time, one continues to propagate and the other disappears. By repeating this phenomenon, the stacking fault density decreases with growth.
- the stacking fault propagating parallel to the (111) plane is blocked by the step, and the stacking fault propagation direction is the ( ⁇ 1-11) plane.
- the direction is limited to the direction parallel to.
- Patent Document 2 As a method of solving the above-mentioned problem and effectively reducing both the antiphase region boundary surface and the stacking fault that are surface defects in silicon carbide, as shown in Patent Document 2 and Non-Patent Document 2, A technique for growing silicon carbide on a Si substrate having undulations having a ridge parallel to one direction has been developed. A defect elimination mechanism using this technique will be described below.
- the stacking fault density is reduced by the following stacking fault mechanism.
- stacking faults on the cubic silicon carbide (001) plane One is a stacking fault that exposes the Si polar face on the (001) plane, and the other is a stacking fault that exposes the C polar face.
- the stacking fault that exposes the C polar face self-extinguishes by reducing the surface area because the surface energy of the C polar face is relatively lower than the surface energy of the (001) face.
- the stacking fault that exposes the Si polar face is stable because the surface energy of the Si polar face is relatively higher than the surface energy of the (001) face. For this reason, the Si polar face continues to be exposed on the outermost surface and remains on the surface.
- the stacking fault exposing the Si polar face as shown in FIG. 10, the stacking fault 103 generated on the opposed slope of the substrate 101 is aligned in a mirror-facing positional relationship inside the silicon carbide layer 102, The association disappears with the growth of silicon.
- Non-Patent Document 3 As a means for eliminating such stacking faults that expose the Si polar face, SBE (Switch Back Epitaxy) technology as shown in Non-Patent Document 3 has been developed. This SBE technique will be described below.
- the stacking fault polar surface 113 of the stacking fault 112 included in the silicon carbide crystal 111 becomes a C polar plane 114 on the back side of the substrate. That is, by turning the substrate over, the exposed surface of the remaining stacking faults can be converted to a C polarity surface. Since the C-polar plane self-extinguishes by growth, by carrying out homoepitaxial growth of cubic silicon carbide on this back side, in principle, the remaining stacking faults disappear and the stacking faults are completely eliminated.
- the stacking fault density is significantly reduced, but the stacking fault is not completely eliminated.
- the remaining stacking faults are newly generated in the SBE growth process.
- a factor leading to the occurrence of a new stacking fault is a strain existing in the cubic silicon carbide substrate and the homoepitaxial layer, or in the homoepitaxial layer. Similar to the growth of silicon carbide on a Si substrate having undulations parallel to one direction, during SBE growth, it is also possible to achieve lattice matching when thermal strain or stacking faults due to temperature distribution in the substrate surface are associated and extinguished. Accompanying distortion occurs. In order to alleviate this strain, a stacking fault is newly generated inside the silicon carbide crystal.
- a GaN layer is provided on a sapphire substrate, and GaN is grown by creating equilateral triangle openings in three ⁇ 11-20> directions equivalent to SiO 2 thereon, A triangular pyramid GaN growth layer is formed.
- lateral growth is promoted and flattened so as to fill the triangular pyramid.
- dislocations extending vertically from the substrate interface do not reach the curved surface when reaching the inclined surface of the cone structure, and a low dislocation density is realized.
- the dislocations extending vertically from the substrate interface are once bent and then gathered in the crystal region on SiO 2 and extend upward again, high-density dislocations and defect regions are formed on the surface.
- the propagation direction of the defects does not change, even if any opening formation or lateral growth is used.
- a low dislocation density region cannot be formed.
- the present invention has been made in view of the above-described problems, and reduces the density of the structural lattice defects without causing anisotropy in the stretching direction, and any stacking fault caused by lattice strain.
- An object of the present invention is to provide a silicon carbide substrate having a surface with a low defect density capable of realizing a high-performance semiconductor element by preventing the propagation of.
- the present invention proposes the following items in order to solve the above-described problems.
- the first aspect of the present invention is: In a silicon carbide substrate having at least a stacking fault inside, An inclusion region forming an inconsistent interface at the interface with the silicon carbide inside the substrate;
- the silicon carbide substrate is characterized in that propagation of stacking faults in silicon carbide is blocked at the mismatch interface.
- the second aspect of the present invention is:
- the inclusion region includes at least one of silicon, carbon, nitrogen, hydrogen, helium, neon, argon, krypton, and xenon.
- the third aspect of the present invention is:
- the inclusion region is a silicon carbide substrate according to the first aspect, wherein the inclusion region is a space.
- the fourth aspect of the present invention is:
- the silicon carbide substrate has two planes having substantially parallel and different stacking fault densities, Propagation of stacking faults from a plane side having a high stacking fault density to a plane having a low stacking fault density in the plane is blocked at the mismatch interface between the silicon carbide and the inclusion region.
- the silicon carbide substrate according to any one of the third to third aspects.
- the inclusion region has a width S, a center-to-center distance between adjacent inclusion regions, and a stacking fault and the mismatch, where H is a height parallel to the thickness direction of the silicon carbide substrate. If the angle formed with the interface (side wall of the inclusion region) is ⁇ , The silicon carbide substrate according to any one of the first to fourth aspects, wherein H ⁇ (PS) / tan ⁇ is satisfied.
- a sixth aspect of the present invention is a silicon carbide substrate having at least a stacking fault inside and having at least one main surface, It has a plurality of inclusion areas inside, The plurality of inclusion regions are distributed substantially parallel to one of the main surfaces; Propagation of the stacking fault is blocked at the side wall of the inclusion region, which is an interface with the inclusion region, The inclusion region has a width S, a center distance between adjacent inclusion regions, P, a stacking fault and the side wall, where H is a height parallel to the thickness direction of the silicon carbide substrate. If the angle formed by is ⁇ , A silicon carbide substrate characterized by satisfying H ⁇ (PS) / tan ⁇ .
- the seventh aspect of the present invention is The first to sixth aspects, wherein the silicon carbide substrate is cubic silicon carbide, a main surface is a ⁇ 001 ⁇ plane, and the mismatch interface is parallel to a ⁇ 110 ⁇ plane.
- the eighth aspect of the present invention is The silicon carbide substrate is cubic silicon carbide, the main surface is a ⁇ 111 ⁇ plane, The silicon carbide substrate according to any one of the first to sixth aspects, wherein the mismatch interface is parallel to any of a ⁇ 111 ⁇ plane, a ⁇ 110 ⁇ plane, and a ⁇ 211 ⁇ plane. It is.
- the ninth aspect of the present invention provides The silicon carbide substrate is hexagonal silicon carbide, the main surface is a ⁇ 0001 ⁇ plane, The silicon carbide substrate according to any one of the first to sixth aspects, wherein the mismatch interface is parallel to a ⁇ 11-20 ⁇ plane or a ⁇ -1100 ⁇ plane.
- the tenth aspect of the present invention provides A semiconductor element formed using the silicon carbide substrate according to any one of the first to ninth aspects, A silicon carbide layer having the same crystal structure as that of silicon carbide forming the silicon carbide substrate is formed on the surface of the silicon carbide substrate, In the semiconductor element, an internal electric field is formed in the silicon carbide layer.
- the eleventh aspect of the present invention is Forming a plurality of discrete regions having a ⁇ 110 ⁇ plane as a sidewall on a silicon carbide substrate having a (001) plane as a surface; And homoepitaxial growth on the silicon carbide substrate,
- the step of homoepitaxial growth includes a step of growing so as to satisfy the following expression (2).
- rg [001] ⁇ tan 35.3 ° -r g [110] > 0
- rg [001] is the crystal growth rate in the [001] direction
- rg [110] is the crystal growth rate in the [110] direction.
- the twelfth aspect of the present invention provides The step of homoepitaxially growing on the silicon carbide substrate comprises the step of laterally growing the upper ends of the plurality of discrete regions and connecting them to each other. It is a manufacturing method.
- the present invention by reducing the density without causing anisotropy in the extending direction of structural lattice defects, and by preventing the propagation of any stacking faults due to lattice strain, It is possible to provide a silicon carbide substrate having a surface with a low defect density capable of realizing a simple semiconductor element. This is because by utilizing the property that the stacking fault propagates in a specific direction because it is in a single crystal, an inclusion region is provided so that the stacking fault contacts the “mismatched interface” where there is no crystal continuity. It is possible to prevent the propagation of defects. Therefore, the stacking fault density can be reduced regardless of the presence or absence of distortion.
- the inclusion region by providing the inclusion region inside, it is possible to suppress the occurrence of stacking faults due to lattice strain generated in the silicon carbide crystal lattice. This is because even if a stacking fault occurs, the inclusion region prevents its propagation. Moreover, since the Young's modulus of the inclusion region is equal to or lower than the Young's modulus of silicon carbide, it is considered that the inclusion region absorbs strain and suppresses the generation itself.
- FIG. 1 is a cross-sectional view of a silicon carbide substrate 1 according to the present invention.
- Main surface 12 which is the most exposed part of the surface of silicon carbide substrate 1, is parallel to (001) plane, and silicon carbide substrate 1 is a plate having a back surface parallel to main surface 12. Crystal.
- the cubic silicon carbide 11 forming the silicon carbide substrate 1 has a plurality of inclusion regions 13 within 100 ⁇ m, preferably within 50 ⁇ m, more preferably within 20 ⁇ m from the main surface 12 toward the inside of the silicon carbide substrate 1. Exist evenly. These inclusion regions 13 form mismatched interfaces at the interface with silicon carbide.
- the cubic silicon carbide 11 and the inclusion region 13 are not continuous and need only be mismatched. Note that the mismatch interface means an interface that is not lattice-matched.
- the silicon carbide substrate of the present invention is substantially made of single crystal silicon carbide. “Substantially” means that it is not a complete single crystal silicon carbide because it has an inclusion region with a mismatch interface inside the substrate and a defect inside the substrate.
- the silicon carbide substrate of the present invention contains a stacking fault and an inclusion region inside, but the ratio of the inclusion region and the defect to the entire substrate is very small, and is substantially single crystal silicon carbide.
- the inclusion region 13 may contain at least one of silicon, carbon, nitrogen, hydrogen, helium, neon, argon, krypton, and xenon, or may be a space (including a vacuum). In other words, the inclusion region 13 is formed of a single crystal (when it has a mismatched interface because the crystallinity and orientation of the substrate itself are different), polycrystalline, or amorphous silicon carbide, a material other than silicon carbide, or a space. Yes.
- the layer in which the inclusion region 13 is distributed is substantially parallel to the main surface 12, and the side wall of the inclusion region 13 (the wall surface that is not substantially parallel to the main surface among the wall surfaces constituting the inclusion region) is ⁇ 110 ⁇ . It is substantially parallel to the surface.
- the densest surface through which the stacking fault 14 propagates and the inclusion region 13 are not parallel, and the inner angle ⁇ between the stacking fault 14 and the sidewall of the inclusion region 13 is larger than 0 degrees. If it is less than 90 degree
- the silicon carbide substrate 1 including the inclusion region satisfying the above formula (1) and the later-described formula (7) has different stacking fault densities on the main surface 12 and the back surface thereof. Since the propagation of the stacking fault that propagates from the side with the high stacking fault density (back surface) to the side with the low stacking fault density (main surface 12) is blocked at the side wall (mismatch interface) of the inclusion region, Is realized.
- main surface 12 is parallel to the (001) plane, and the side wall of inclusion region 13 is approximately parallel to the ⁇ 110 ⁇ plane.
- the stacking fault 14 contained in the cubic silicon carbide 11 propagates in parallel with the ⁇ 111 ⁇ plane which is the most dense surface. For this reason, from the above formula (1), the internal angle ⁇ between the stacking fault 14 and the side wall of the inclusion region 13 is 35.3 degrees.
- the interval W between the inclusion regions 13 is not necessarily the same. Is about 100 nm to 100 ⁇ m, preferably 1 ⁇ m to 50 ⁇ m, and more preferably 2 ⁇ m to 20 ⁇ m. This is because, as the interval W between the inclusion regions 13 becomes narrower, the processing of the inclusion region 13 becomes difficult, and the volume occupancy of the inclusion region 13 increases and the substrate resistance when operating as a semiconductor device increases. It is because it ends up. Further, as the interval W between the inclusion regions 13 increases, the height H of the inclusion region 13 needs to be naturally increased, and the volume occupancy of the inclusion region 13 decreases, and the strain may not be absorbed. Because it comes in.
- the height H of the inclusion region 13 can be obtained using the interval W of the inclusion region 13 and the equation (1).
- the height H of the inclusion region 13 decreases, not only the processing of the inclusion region 13 becomes difficult, but also the volume occupancy of the inclusion region 13 decreases, and there is a possibility that the strain cannot be absorbed.
- the height H of the inclusion region 13 increases (for example, 100 ⁇ m or more), not only the processing of the inclusion region 13 becomes difficult, but the volume occupancy of the inclusion region 13 increases, and the semiconductor device operates as a semiconductor device. In this case, the substrate resistance increases.
- the width S of the inclusion region 13 becomes narrower, not only the processing of the inclusion region 13 becomes difficult, but the volume occupancy of the inclusion region 13 decreases, and there is a possibility that the strain cannot be absorbed.
- the width S of the inclusion region 13 increases, the volume occupation ratio of the inclusion region 13 increases, the substrate resistance when operating as a semiconductor device increases, and the interval W between the inclusion regions 13 is desirable. It becomes difficult to set the value.
- the width S of the inclusion region 13 is preferably 100 nm to 100 ⁇ m, preferably 1 ⁇ m to 50 ⁇ m, and more preferably 2 ⁇ m to 20 ⁇ m.
- the layer of the cubic silicon carbide 11 on the inclusion region 13 is mechanical. And the inclusion region 13 may be exposed on the main surface 12.
- an active layer is provided as an upper layer as a semiconductor device, if the depth T from the main surface 12 to the layer of the inclusion region 13 is small, the current distribution becomes non-uniform and local overheating and destruction occur. There is a fear.
- the depth T from the main surface 12 to the layer of the inclusion region 13 is extremely large, the strain of the layer between the inclusion region 13 and the main surface 12 cannot be absorbed. It becomes difficult to reduce the stacking fault density.
- the depth T from the main surface 12 to the layer of the inclusion region 13 is preferably 100 nm or more and 100 ⁇ m or less, preferably 1 ⁇ m or more and 50 ⁇ m or less, and more preferably 10 ⁇ m or more and 30 ⁇ m or less.
- the width H of the inclusion region 13 with respect to the direction perpendicular to the main surface 12 is at least five times the width S with respect to the direction parallel to the main surface 12, and the inclusion region 13 regarded as the direction parallel to the main surface 12.
- the area of the section is preferably 1/10 or less of the area of the main surface 12.
- the inclusion region leads to a reduction in stacking fault density at the side wall, the inclusion regions may be connected without being isolated as long as the side wall has such an effect.
- the cross section of the substrate may have a form as shown in FIG. 1 and the inside of the substrate may have a form as shown in FIG. 2 in a plane parallel to the main surface of the substrate.
- the cross section of the substrate may be in the form as shown in FIG. 1 and in the form of lines and spaces in a plane parallel to the main surface of the substrate.
- Cubic silicon carbide is grown on the above substrate.
- CVD, MBE, LPE, etc. can be used, but in any case, it is desirable that the supply amounts of Si source and C source can be adjusted individually, and further, the flow rate is precise as gas. It is desirable to adjust the supply ratio of the Si source and the C source as appropriate.
- a specific crystal plane is oriented in a specific orientation.
- the (111) plane, the ( ⁇ 1-11) plane, and the C plane are oriented to the ( ⁇ 111) plane and the (1-11) plane.
- the antiphase region boundary surface which is a kind of surface defect, disappears.
- stacking faults remain on the substrate, but all are distributed in the ⁇ 111 ⁇ plane, which is the most dense surface, and intersect with the main surface (001) at an angle of 54.7 degrees.
- the stacking fault density can be reduced on the surface of the substrate by executing the following manufacturing procedures (I) to (III).
- a process of forming a desired silicon carbide substrate made of silicon carbide will be described while explaining this mechanism in detail.
- II Formation of discrete regions
- III Reduction of stacking fault density by homoepitaxial growth
- Expansion of low stacking fault regions by connection of discrete regions (I) to (III) are described in detail below.
- the side wall of the ⁇ 110 ⁇ plane on the (001) plane of a cubic silicon carbide substrate (hereinafter also simply referred to as SiC substrate 200) that is 3C—SiC.
- a protrusion shape (hereinafter referred to as a discrete region 210) is formed.
- the discrete area 210 may be a so-called line & space, or a simple unevenness.
- Such discrete regions 210 can be formed by applying a mask to a part of the SiC substrate 200 and etching the SiC substrate itself, or the surface of the SiC substrate 200 as in a second embodiment to be described later.
- a mask may be formed on a part of the film, and SiC may be formed on a part other than the mask.
- FIG. 14 shows a 3C-SiC substrate patterned by a photolithography process, which is processed by reactive ion etching (RIE) using a Ni film (film thickness: 0.5 ⁇ m) formed by plating as a mask.
- RIE reactive ion etching
- FIG. 14B is a diagram showing a cross section of the discrete region.
- C-SF the stacking fault that exposes the carbon surface on the substrate surface
- SiC substrate 200 having discrete regions 210 has an angle of (4.7) and 54.7 degrees, in other words, ⁇ 110 ⁇ plane and 35.3 °.
- the stacking fault forming an angle remains.
- the density of the remaining stacking faults can be greatly reduced by the two mechanisms, the mechanism M1 and the mechanism M2.
- Mechanism M1 First, the mechanism M1 will be described. As shown in FIG. 13, when silicon carbide is further homoepitaxially grown on SiC substrate 200, stacking fault SF1 originally present in SiC substrate 200 also propagates into new silicon carbide. However, when the stacking fault SF1 grows along with the homoepitaxial growth up to the dotted line 201 in FIG. Such a technique for reducing the stacking fault density is referred to as mechanism M1. When SiC is homoepitaxially grown after masking a part of the surface of SiC substrate 200 as in the second embodiment to be described later, penetration of SF1 into the region is prevented by the presence of the mask. become.
- the mechanism M2 As shown in the mechanism M2, as a condition for causing the stacking fault SF2 exposed on the surface of the discrete region 210 before the growth to escape to the side wall of the discrete region 212 after the growth, it is exposed on the surface of the discrete region 210.
- the speed at which the stacking fault SF2 that has been displaced in the direction toward the side wall of the discrete region 212, that is, the ⁇ 110> direction accompanying the homoepitaxial growth may exceed the growth rate in the ⁇ 110> direction of the side wall of the discrete region 212.
- the following expression (3) is given as “a condition for discharging all stacking faults existing on one discrete region to the side wall”.
- W L the width of one discrete region W L, [001] growth thickness in the direction Delta] t [001], which represents the growth thickness of the [110] direction in Delta] t [110].
- discrete regions are not formed as a single unit, but a plurality of discrete regions are arranged at certain intervals. Therefore, it is necessary to consider the existence of another adjacent discrete region.
- Such growth of silicon carbide can be realized by controlling the crystal growth direction by changing the raw material supply ratio and the film formation temperature under the growth conditions shown in Table 2 of the second embodiment described later.
- FIG. 17 shows a state where a cross section when a discrete region is actually grown is photographed with an optical microscope.
- FIG. 18 shows a transmission polarization image showing a state where a cross section when a discrete region is actually grown is photographed with a polarization type transmission microscope.
- the stacking fault appears as a bright line in the polarization image.
- the stacking faults existing in the discrete regions are discharged to the side walls of the discrete regions, and as a result, the vicinity of the upper end of the discrete regions has a dark contrast indicating a low stacking fault density. This proves that stacking faults in the discrete region can be discharged to the side wall.
- FIG. 16 is a diagram schematically showing a state in which discrete regions are grown in the lateral direction and connected.
- it is important to connect the discrete regions while maintaining the side wall from which the stacking fault has been discharged as it is. For example, if the sidewalls from which stacking faults have been discharged are connected without being maintained, the stacking faults that have been discharged once in (II) propagate through the crystal again due to the absence of the side walls. It will end up. If it connects in such a state, a stacking fault will reach the substrate surface, and will deviate from the original purpose.
- FIG. 19 shows a state in which a cross section when discrete regions are connected under such conditions is photographed with an optical microscope.
- the occurrence of an abnormal bonding interface as a result of crystallinity mismatch is not observed at the connecting portion between the discrete regions.
- no matter what part of the grown substrate is verified, the occurrence of an abnormal bonding interface is not seen as in the connection portion.
- FIG. 20 shows a state in which a cross section of the substrate in which discrete regions are connected is photographed with an optical microscope.
- FIG. 20A is a cross-sectional shape image
- FIG. 20B is a transmitted polarization image at the same location.
- the stacking faults identified as bright lines in the polarization image of (b) are blocked from propagating on the side wall of the inclusion region, and they reach the substrate surface including the connected portion of the discrete region. It can be confirmed over a wide range in the figure. In this way, the low stacking fault density can be increased while maintaining the blocking of stacking fault propagation by connecting the upper part of the process by lateral growth while maintaining the side wall of the discrete area, in the process of (III). Is possible.
- the silicon carbide substrate formed through the above steps is in a substantially parallel plane state, where the surface that is one main surface has a low stacking fault density and the back surface that is the other main surface has a high stacking fault density. Moreover, the surface of a main surface is a ⁇ 001 ⁇ surface, respectively.
- the silicon carbide substrate formed in the first embodiment discharges stacking faults while growing silicon carbide from a discrete region of lines and spaces. This is the final substrate. Therefore, using this first embodiment as an example, a relationship that defines the relationship between the inclusion region 13 and the stacking fault in the silicon carbide substrate while using parameters that define the discrete region before the finally obtained silicon carbide substrate is grown. It will be shown below that the expression (1) is derived from the expression.
- a substrate on which a discrete region before growth is formed will be described as a line (hereinafter also referred to as a discrete region) & space for explanation, but it may be in a state like the SiC substrate 200 shown in FIG.
- any substrate may be used as described in (I).
- the silicon carbide substrate formed in the first embodiment can block propagation of stacking faults by the inclusion region 13, but the stacking faults propagating in the silicon carbide substrate are shown in FIG.
- the stacking fault (SF3) propagating from the line (discrete region) and the stacking fault (SF4) propagating from the space as shown in FIG. 22 can be roughly classified.
- relational expressions defining the relationship between the inclusion region 13 and the stacking fault in each case are derived.
- each parameter related to the inclusion region 13 to be formed after growth and each parameter on the substrate before growth is defined as follows.
- L + C is the center-to-center distance P between the adjacent inclusion regions 13 and can therefore be converted as in the following equation (7).
- each parameter in the substrate before growth and each parameter related to the inclusion region 13 are defined as follows.
- L + C is the center-to-center distance P between the adjacent inclusion regions 13 and therefore satisfies the above-described equation (7).
- the manufacturing procedure described in (I) to (III) is executed, thereby having an inclusion region that forms an inconsistent interface at the interface with silicon carbide. Accordingly, propagation of stacking faults in silicon carbide can be blocked at the mismatched interface, so that the surface of the silicon carbide substrate can have a low stacking fault density. Thereby, it becomes a silicon carbide substrate preferable as a substrate for semiconductor devices.
- cubic silicon carbide having the (001) plane as the main surface is used as the substrate, but a cubic silicon carbide substrate having the (111) plane as the main surface may be used.
- the side wall of the inclusion region is parallel to any of the ⁇ 111 ⁇ plane, ⁇ 110 ⁇ plane, or ⁇ 211 ⁇ plane.
- hexagonal silicon carbide having a ⁇ 11-20 ⁇ plane or a ⁇ 03-38 ⁇ plane as a main surface can be used.
- the most dense surface through which the stacking fault propagates is the (0001) plane, and the stacking fault intersects the main surface at an angle of 30 to 60 degrees. Therefore, by performing the above-described steps in the present embodiment, The same effect as the embodiment can be obtained.
- hexagonal silicon carbide having a ⁇ 0001 ⁇ plane as the main surface is used, the side wall of the inclusion region is made parallel to the ⁇ 11-20 ⁇ plane or the ⁇ 1100 ⁇ plane.
- the most dense surface through which the stacking fault propagates is the (0001) plane, and the stacking fault intersects the main surface at an angle of 30 to 60 degrees. Therefore, by performing the above-described steps in the present embodiment, The same effect as the embodiment can be obtained.
- the silicon carbide substrate formed in this embodiment can also block the propagation of stacking faults that occur secondarily (later) after the substrate is formed.
- an undulation substrate parallel to the [ ⁇ 110] direction was fabricated on the entire surface by rubbing abrasive grains on the surface of the Si (001) substrate having a diameter of 4 inches in parallel to the [ ⁇ 110] direction (one direction). Polishing scratches introduced).
- the abrasive used for introducing the unidirectional polishing scratches is a diamond slurry having a particle size of about 9 ⁇ m, and is rubbed against the surface of the Si (001) substrate in a predetermined direction while penetrating into a commercially available polishing cloth (Engis M414). Innumerable polishing flaws were formed that were substantially parallel.
- the pressure when rubbing against the surface of the Si (001) substrate in a predetermined direction was 0.2 kg / cm 2 , and the polishing cloth was reciprocated about 300 times for one polishing scratch introduction (unidirectional polishing treatment).
- the undulating Si (001) substrate produced by the above steps was heated to 1350 degrees in a mixed atmosphere of C 2 H 2 and H 2 in a CVD apparatus to form an ultrathin silicon carbide layer.
- the source gas C 2 H 2 and the carrier gas H 2 were supplied to the substrate surface from room temperature.
- the supply amount and pressure of C 2 H 2 and H 2 are shown in Table 1.
- silicon carbide was grown by supplying SiH 2 Cl 2 , C 2 H 2 and H 2 at a temperature of 1350 degrees.
- the growth conditions when silicon carbide was grown are as shown in Table 2, and the pressure during growth was adjusted with a pressure adjusting valve installed between the reaction chamber and the pump.
- Silicon carbide was grown for 8 hours under the growth conditions shown in Table 2, and 450 ⁇ m cubic silicon carbide was grown on the Si (001) substrate. Next, the Si (001) substrate was etched with a mixed acid of hydrofluoric acid and nitric acid to produce a single cubic silicon carbide substrate.
- the cubic silicon carbide substrate produced by the above steps was immersed in 500 degree molten KOH for 5 minutes to reveal the defects. Thereafter, when this cubic silicon carbide substrate was observed with an optical microscope, it was found that the defect density on the surface was 8 ⁇ 10 5 / cm 2 , and no antiphase region boundary surface was observed on the main surface. It was.
- the resist was developed to provide an opening in the exposed area, and exposed to 100 W of F plasma to remove the oxide film under the opening.
- the oxide film is selectively removed on the surface of the cubic silicon carbide substrate, and the portion 21 covered with the oxide film and the opening 22 without the oxide film are formed. Will be formed.
- silicon carbide was grown for 10 minutes under the growth conditions shown in Table 2 above, and 10 ⁇ m cubic silicon carbide was grown on the silicon carbide grown on the Si (001) substrate. According to this, as shown in FIG. 3, silicon carbide 33 is selectively grown on silicon carbide layer 31 grown on silicon substrate 34 except for the surface covered with oxide film 32. Become.
- the Si (001) substrate was immersed in a mixed acid of hydrofluoric acid and nitric acid, and the silicon substrate 34 was extinguished by dissolution.
- the oxide film 32 disappears due to dissolution as in the case of the silicon substrate 34.
- discrete single-crystal silicon carbide (width 2 ⁇ m, interval 5 ⁇ m) 33 having a height of 10 ⁇ m is formed on the 113 ⁇ m silicon carbide layer 31.
- silicon carbide was grown for 60 minutes under the growth conditions shown in Table 3 to grow 10 ⁇ m cubic silicon carbide 41.
- the upper part of the discrete silicon carbide 33 is connected by the cubic silicon carbide 41, and the inclusion region having a width of 2 ⁇ m, a distance of 5 ⁇ m and a height of 10 ⁇ m at a depth of 10 ⁇ m on the lower part of the main surface 42 will be formed.
- the cubic silicon carbide substrate produced by the above steps was immersed in 500 ° C. molten KOH for 5 minutes to reveal defects. Thereafter, was subjected to a light microscopy with respect to the main surface of the cubic silicon carbide substrate, defects in the surface density was found to be 2 ⁇ 10 2 / cm 2.
- the stacking fault density can be reduced by three orders of magnitude by providing the inclusion region.
- cubic silicon carbide having the (001) plane as the main surface is used as the substrate.
- the present invention is not limited to this.
- the ⁇ 11-20 ⁇ plane or ⁇ 03-38 ⁇ plane is the main surface.
- hexagonal silicon carbide the most dense surface through which the stacking fault propagates is the (0001) plane, and the stacking fault intersects the main surface at an angle of 30 to 60 degrees. Therefore, by performing the above-described steps in the present embodiment, The same effect as the embodiment can be obtained.
- the growth of silicon carbide under the growth conditions shown in Table 3 was performed for 60 minutes, but this time was adjusted between 300 and 1200 minutes to allow discrete and selective growth.
- the film thickness of the cubic silicon carbide 41 grown on the silicon carbide 33 can be changed.
- the depth of the inclusion region as viewed from the main surface changes between 50 and 200 ⁇ m.
- the defect density on the surface changed as shown in Table 4. According to Table 4, it can be seen that the effect of reducing the stacking fault density according to the present embodiment is manifested at the depth of the inclusion region of 100 ⁇ m or less.
- a 3C—SiC layer having a thickness of 10 ⁇ m is formed by homoepitaxial growth on each substrate manufactured by changing the depth of the inclusion region as shown in Table 4 under the growth conditions shown in Table 5. . Then, although no intentional impurity addition is performed, the homoepitaxial layer exhibits n-type conduction, and its carrier concentration is 5 ⁇ 10 15 / cm 3 .
- Al ions are implanted into the entire surface of the homoepitaxial layer.
- the implantation depth is 1 ⁇ m, and the acceleration energy is changed between 30 and 700 keV so that the Al concentration is constant at 1 ⁇ 10 18 / cm 3 in the depth direction.
- activation annealing is performed at 1600 degrees for 10 minutes in an Ar atmosphere to form a p-conducting layer on the outermost surface.
- an Ni mask region having a diameter of 100 ⁇ m is provided on the surface by photolithography, and rf-RIE at 200 W is performed for 5 minutes while introducing a gas of CF 4 (100 sec) + O 2 (20 sccm), and the surface layer is deepened.
- a pn diode having a mesa structure with a thickness of 0.2 ⁇ m is formed.
- a voltage of 600 V is applied so that the front surface side (p conductive layer side) of the mesa diode is negative and the back surface of the substrate is positive, thereby extending the internal electric field region width of the pn junction to 8 ⁇ m on the n layer side And measure the leakage current.
- Table 6 it is clearly confirmed that the leakage current density is reduced at an inclusion region depth of 100 ⁇ m or less, particularly 50 ⁇ m.
- a silicon carbide layer (homoepitaxial growth layer) having the same structure is formed on a silicon carbide substrate including an inclusion region having a depth of 100 ⁇ m or less, and a semiconductor element for extending an internal electric field is provided on the silicon carbide layer
- the leakage current due to the stacking fault is significantly reduced. That is, in this embodiment, a pn diode is formed using a silicon carbide substrate having an inclusion region.
- a semiconductor element such as a MOSFET can be similarly produced, and in this case, leakage current due to stacking faults is significantly reduced.
- the manufactured semiconductor device can be manufactured.
- cubic silicon carbide is used as the substrate.
- the same effect as in this embodiment can be obtained even if a hexagonal silicon carbide substrate is used. be able to.
- the thus formed silicon carbide substrate is in a substantially parallel plane state, and the surface which is one main surface has a low stacking fault density and the back surface which is the other main surface has a high stacking fault density. Moreover, the surface of a main surface is a ⁇ 001 ⁇ surface, respectively.
- the silicon carbide substrate formed in this embodiment can also block the propagation of stacking faults that occur secondarily (later) after the substrate is formed.
- the abrasive grains are rubbed against the surface of a Si (001) substrate having a diameter of 4 inches in parallel to the [ ⁇ 110] direction, thereby being parallel to the [ ⁇ 110] direction.
- a relief forming substrate was produced on the entire surface.
- cleaning was performed with a solution obtained by mixing a hydrogen peroxide solution and a sulfuric acid mixed solution at a ratio of 1: 1, and an HF solution.
- a thermal oxide film having a film thickness of about 0.5 ⁇ m is formed on the relief processing substrate using a heat treatment apparatus, and then the formed thermal oxide film is And removed with dilute hydrofluoric acid.
- the cross section of the undulation formation region has a continuous wave shape, and is always in a continuous state of undulations parallel to the [ ⁇ 110] direction.
- the depth of the groove was 30 to 50 nm, the width was 1 to 2 ⁇ m, and the inclination was 3 to 5 degrees.
- silicon carbide was grown for 2 hours under the growth conditions shown in Table 2 above, and 113 ⁇ m cubic silicon carbide was grown on the Si (001) substrate.
- the cubic silicon carbide substrate produced by the above steps was immersed in 500 degree molten KOH for 5 minutes to reveal the defects. Thereafter, when this cubic silicon carbide substrate was observed with an optical microscope, it was found that the defect density on the surface was 8 ⁇ 10 5 / cm 2 , and no antiphase region boundary surface was observed on the main surface. It was.
- the resist was developed to provide an opening in the exposed area, and exposed to 100 W of F plasma to remove the oxide film under the opening.
- silicon carbide was grown for 10 minutes under the growth conditions shown in Table 2 above, and 10 ⁇ m cubic silicon carbide was grown on the silicon carbide grown on the Si (001) substrate. According to this, similarly to the second embodiment, silicon carbide does not grow in the portion covered with the oxide film, and single crystal silicon carbide grows in the opening of the oxide film.
- the Si (001) substrate was immersed in a mixed acid of hydrofluoric acid and nitric acid, and the silicon substrate was extinguished by dissolution. As a result, the oxide film disappears due to dissolution as well as the silicon substrate. According to this, as shown in FIG. 4, discrete single crystal silicon carbide (width 2 ⁇ m, interval 5 ⁇ m) having a height of 10 ⁇ m is formed on the 113 ⁇ m silicon carbide layer.
- silicon carbide layer 51 having the surface of discrete silicon carbide 52 is covered with polycrystalline silicon 53 having a thickness of 20 ⁇ m.
- a polishing process was performed using 0.5 ⁇ m diamond abrasive grains and 0.1 ⁇ m diamond abrasive grains, and a planarization process was performed by removing 20 ⁇ m of the surface layer. According to this, as shown in FIG. 7, the tops of discrete silicon carbide 52 are exposed on the surface, and the gaps are filled with polycrystalline silicon 53.
- silicon carbide was grown for 10 minutes under the growth conditions shown in Table 3 to grow 10 ⁇ m cubic silicon carbide. Since this condition is that polycrystalline silicon is easily etched, silicon carbide grows only on discrete silicon carbide, and each is connected, that is, as shown in FIG. A continuous silicon carbide layer 54 is grown on top of the polycrystalline silicon 53, and an inclusion region filled with polycrystalline silicon having a width of 2 ⁇ m, a spacing of 5 ⁇ m, and a height of 10 ⁇ m is formed at a depth of 10 ⁇ m at the bottom of the main surface. Will be formed.
- the silicon carbide substrate was immersed in molten KOH at 500 degrees for 5 minutes to reveal defects. Thereafter, was subjected to a light microscopy to the main surface of the silicon carbide substrate, defects in the surface density was found to be 2 ⁇ 10 2 / cm 2.
- the stacking fault density can be reduced by three orders of magnitude by providing the inclusion region.
- the inclusion region is made of polycrystalline silicon.
- the present invention is not limited to this.
- the inclusion region is made of single crystal silicon, graphite, diamond-like carbon, silicon nitride, or the like, An effect can be obtained.
- cubic silicon carbide having a (001) plane as the main surface is used as the substrate.
- the present invention is not limited to this.
- the ⁇ 11-20 ⁇ plane or the ⁇ 03-38 ⁇ plane is the main surface.
- hexagonal silicon carbide is also possible.
- the most dense surface on which the stacking fault propagates is the (0001) plane, and the stacking fault intersects with the main surface at an angle of 30 to 60 degrees. The same effect as the embodiment can be obtained.
- the silicon carbide substrate thus formed is in a substantially parallel plane state, and the surface that is one main surface has a low stacking fault density and the back surface that is the other main surface has a high stacking fault density. Moreover, the surface of a main surface is a ⁇ 001 ⁇ surface, respectively.
- the silicon carbide substrate formed in this embodiment can also block the propagation of stacking faults that occur secondarily (later) after the substrate is formed.
- the present invention prevents stacking faults propagating in parallel to the densest surface by providing an inclusion region by controlling the width, height, and spacing in a region at an appropriate depth from the main surface.
- a silicon carbide substrate that can be preferably used as a substrate for a semiconductor device can be obtained.
- the silicon carbide substrate of the present invention includes an inclusion region or a space (including a vacuum) containing at least one of silicon, carbon, nitrogen, hydrogen, helium, neon, argon, krypton, and xenon. Has a region.
- a mismatch interface that is an interface that is not lattice-matched is formed at the interface between silicon carbide and the inclusion region, so that propagation of stacking faults in silicon carbide can be blocked. Therefore, the surface of the silicon carbide substrate can have a low stacking fault density. That is, it becomes a silicon carbide substrate preferable as a substrate for a semiconductor device.
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Abstract
Description
少なくとも内部に積層欠陥を有する炭化珪素基板において、
前記基板の内部に前記炭化珪素との界面に不整合界面を形成する内包領域を有し、
前記不整合界面において、炭化珪素内の積層欠陥の伝搬が遮断されていること
を特徴とする炭化珪素基板である。
前記内包領域は、珪素、炭素、窒素、水素、ヘリウム、ネオン、アルゴン、クリプトン、キセノンのうち少なくとも1つを含んでいること
を特徴とする上記第1の態様に記載の炭化珪素基板である。
前記内包領域は、空間であることを特徴とする上記第1の態様に記載の炭化珪素基板である。
当該炭化珪素基板は、略平行かつ異なる積層欠陥密度を有する二つの平面を有し、
前記炭化珪素と内包領域との不整合界面において、前記平面のうち積層欠陥密度の高い面側から積層欠陥密度の低い面への積層欠陥の伝搬が遮断されていること
を特徴とする上記第1乃至第3の態様のいずれか1態様に記載の炭化珪素基板である。
前記内包領域は、当該炭化珪素基板の厚さ方向と平行な方向である高さをHとした場合に、幅S、互いに隣り合う内包領域との中心間距離をP、積層欠陥と前記不整合界面(内包領域の側壁)とのなす角をθとすると、
H≧(P-S)/tanθを満たすこと
を特徴とする上記第1乃至第4の態様いずれか1態様に記載の炭化珪素基板である。
内部に複数の内包領域を備え、
前記複数の内包領域は、前記主表面の1つにほぼ平行に分布し、
前記積層欠陥が、前記内包領域との界面である内包領域側壁で伝搬が遮断されており、
前記内包領域は、当該炭化珪素基板の厚さ方向と平行な方向である高さをHとした場合に、幅S、互いに隣り合う内包領域との中心間距離をP、積層欠陥と前記側壁とのなす角をθとすると、
H≧(P-S)/tanθを満たすこと
を特徴とする炭化珪素基板である。
前記炭化珪素基板は、立方晶炭化珪素であり、主表面が{001}面であり、 前記不整合界面が、{110}面に平行であること
を特徴とする上記第1乃至第6の態様いずれか1態様に記載の炭化珪素基板である。
前記炭化珪素基板は、立方晶炭化珪素であり、主表面が{111}面であり、
前記不整合界面が、{111}面、{110}面、{211}面のいずれかに平行であること
を特徴とする上記第1乃至第6の態様いずれか1態様に記載の炭化珪素基板である。
前記炭化珪素基板は、六方晶炭化珪素であり、主表面が{0001}面であり、
前記不整合界面が、{11-20}面または{-1100}面に平行であること
を特徴とする上記第1乃至第6の態様いずれか1態様に記載の炭化珪素基板である。
上記第1~9のいずれか1態様に記載の炭化珪素基板を用いて形成された半導体素子であって、
前記炭化珪素基板表面には、前記炭化珪素基板を形成する炭化珪素と同一結晶構造の炭化珪素層が形成され、
前記炭化珪素層には、内部電界が形成されること
を特徴とする半導体素子である。
(001)面を表面とする炭化珪素基板に{110}面を側壁として有する複数の離散領域を形成する工程と、
前記炭化珪素基板上にホモエピタキシャル成長する工程と、を有し、
前記ホモエピタキシャル成長する工程は、以下に示す(2)式を満たすように成長させる工程を備えること
を特徴とする炭化珪素基板の製造方法である。
rg[001]×tan35.3°-rg[110]>0 ・ ・ ・(2)
なお、rg[001]は、[001]方向の結晶成長速度であり、rg[110]は、[110]方向の結晶成長速度を表す。
前記炭化珪素基板上にホモエピタキシャル成長する工程の後、前記複数の離散領域同士の上端を横方向成長させて互いに連結させる工程を備えること
を特徴とする上記第11の態様に記載の炭化珪素基板の製造方法である。
本発明の炭化珪素基板は、実質的に単結晶炭化珪素からなる。「実質的に」とは、基板内部に不整合界面を隔てて内包領域を有すること、および基板内部に欠陥を有することから、完全な単結晶炭化珪素ではないことを意味するものである。本発明の炭化珪素基板は、内部に積層欠陥と内包領域を含有するが、基板全体に対して内包領域や欠陥の割合は非常に少なく、実質的には単結晶炭化珪素である。
また、内包領域13は、珪素、炭素、窒素、水素、ヘリウム、ネオン、アルゴン、クリプトン、キセノンのうち少なくとも1つを含んでいたり、空間(真空の場合も含む)となっていたりすればよい。言い換えれば、内包領域13は、単結晶(基板自体の結晶性と配向が異なるため不整合界面を有する場合)、多結晶、またはアモルファスの炭化珪素、炭化珪素以外の材料、もしくは空間により形成されている。また、内包領域13が分布している層は、主表面12と略平行であり、内包領域13の側壁(内包領域を構成する壁面のうち、主表面と略平行でない壁面)は、{110}面に略平行である。
<第1実施形態>
以下に、本発明の第1実施形態に係る炭化珪素基板について説明する。
(I)離散領域の形成
(II)ホモエピタキシャル成長による積層欠陥密度の低減
(III)離散領域同士の連結による低積層欠陥領域の拡大
以下、(I)~(III)について詳細に説明をする。
まず、図12に示すように、3C-SiCである立方晶炭化珪素基板(以下、単にSiC基板200とも呼ぶ。)の(001)面上に{110}面の側壁を持つ、突起形状(以下、離散領域210と呼ぶ。)を形成する。この離散領域210は、俗にいうライン&スペースであってもよいし、単なる凹凸などであってもよい。条件としては、上述したように、{110}面の側壁を持つことが極めて好ましい。このような、離散領域210は、SiC基板200上の一部にマスクを施して、SiC基板自体をエッチングして形成することもできるし、後述する第2実施形態のようにSiC基板200の表面の一部にマスクを施して、マスク以外の部分にSiCを成膜して形成しても良い。
この方法で形成された離散領域の形状として、ライン&スペースを採用している。サイズは、それぞれ、ライン幅WL=5μm、スペース幅WS=20μm、ライン高さd=15~20μmとした。
図14に示す離散領域は、ラインを[-110]方向に平行に形成することで、その側壁を(110)面及び(-1-10)面とした。このように形成した離散領域に対しては、3C-SiC中に存在する2種類の積層欠陥のうち基板表面にカーボン面を露出する積層欠陥(以下、C-SFと呼ぶ。)に対して、後述する積層欠陥密度の低減機構が働くことになる。
離散領域210を有するSiC基板200には、上述したように(001)面と54.7度の角度、言い換えれば{110}面と35.3°の角度をなす積層欠陥が残留することになる。このように残留した積層欠陥は、機構M1と機構M2との2つの機構によりその密度を大幅に低減することができる。
まず、機構M1について説明をする。図13に示すようにSiC基板200に対して更に炭化珪素をホモエピタキシャル成長させると、もともとSiC基板200内に存在していた積層欠陥SF1も新たな炭化珪素内に伝搬することになる。しかしながら図13の点線201までホモエピタキシャル成長に伴い積層欠陥SF1が成長すると、同じくホモエピタキシャル成長した成長中離散領域211の側壁に阻まれて、その領域内部への侵入を阻止されることになる。このような積層欠陥密度の低減手法を機構M1と呼ぶ。なお、後述する第2実施形態のようにSiC基板200の表面の一部にマスクを施した後にSiCをホモエピタキシャル成長させる場合には、マスクの存在によりSF1の領域内部への侵入が阻止されることになる。
次に、機構M2について説明をする。図13に示すようにSiC基板200をホモエピタキシャル成長させると、もともとSiC基板200内に存在していた積層欠陥SF2も新たな炭化珪素内に伝搬することになる。これは、離散領域210内についても変わらず同じである。積層欠陥SF2は、図13に示すように欠陥がSiC基板200の表面に露出した状態となっている。
まず、図13に示すように、ファーストステップとして、点線201まで、つまり成長中離散領域211までホモエピタキシャル成長させたとする。しかしながら、この状態においても積層欠陥SF2は、成長中離散領域211の表面に露出した状態となっている。
次に、セカンドステップとして、実線202まで、つまり成長後離散領域212までホモエピタキシャル成長させると、今まで成長中離散領域211の表面に露出していた積層欠陥SF2が、成長後離散領域212の側壁へと到達し内包領域へとぶつかるため、これ以上の欠陥成長が阻止される。このような積層欠陥密度の低減手法を機構M2と呼ぶ。
rg[001]×tan35.3°-rg[110]>0 ・ ・ ・(2)
上記を満たすような結晶成長速度比のコントロールは、成長温度、材料ガスの供給比、成長圧力を調整することにより達成される。
このような機構M1、機構M2による積層欠陥密度の低減によりSiC基板200をホモエピタキシャル成長させた後の基板表面の積層欠陥は大幅に低減された良好なものとなり低積層欠陥密度領域が形成されることになる。
t[001]×tan35.3°-Δt[110]>WL ・ ・ ・(3)
さらに、実際には離散領域は単体で形成されているわけではなく、複数の離散領域がある間隔で配列している。そのため、隣り合う別の離散領域の存在を考慮する必要がある。積層欠陥密度低減機構に不可欠な「領域の離散性(Isolation)」を維持するために、ここでは、「隣接する側壁同士が会合する前に、1つの離散領域上の積層欠陥を側壁に排出させる」という条件を加える。そのため、離散領域間の間隔をWSとすると、(3)式には以下に示す(4)式の制限が加わる。
・ ・ ・(4)
・ ・ ・(5)
このような炭化珪素の成長は、後述する第2実施形態の表2で示す成長条件にて、原料供給比や成膜温度を変化させて結晶成長方向を制御することで実現することができる。
次に、(II)で説明したように離散領域内の全ての積層欠陥を側壁へと排出することで図15に示す低積層欠陥密度のアレイが形成されている状態から、図16に示すように離散領域同士を連結することで低積層欠陥密度領域を拡大させる。なお、図16は、離散領域同士を横方向成長させて連結させた状態を模式的に示した図である。
離散領域同士の連結を行うには、積層欠陥が排出された側壁をそのままの状態で維持しながら離散領域同士を連結することが重要である。例えば、積層欠陥が排出された側壁をそのままの状態で維持することなく連結させてしまった場合、側壁がなくなったことにより、(II)において一旦、排出させた積層欠陥が結晶内を再び伝搬してしまうことになる。このような状態で連結させると基板表面にまで積層欠陥が到達してしまうことになり、本来の目的を逸脱してしまう。
離散領域の上端を横方向に成長させるには、後述する第2実施形態の表3で示す成長条件にて、原料供給比や成膜温度を変化させて結晶成長方向を制御することで実現することができる。
上述した(I)~(III)にて説明したように、第1実施形態において形成される炭化珪素基板は、例えば、ライン&スペースの離散領域の状態から炭化珪素を成長させながら積層欠陥を排出する機構により最終的な基板となっている。そこで、この第一実施形態を例に、最終的に得られる炭化珪素基板を成長させる前の離散領域を規定するパラメータを用いつつ、炭化珪素基板における内包領域13、積層欠陥の関係を規定した関係式から(1)式が帰納されることを以下に示す。なお、以下、説明のため成長前の離散領域を形成した基板は、ライン(以下、離散領域とも呼ぶ。)&スペースとして説明をするが、図12に示したSiC基板200のような状態であれば、(I)で説明したようにどのような基板であってもよい。
まず、上述した図12に基づき成長前の離散領域を離散領域210とする。次に、図21に示すように、成長前の基板における各パラメータと成長後に形成されることになる内包領域13に関係する各パラメータを以下に示すように規定する。
L:成長前の離散領域幅
C:成長前のスペース幅
h:成長前の離散領域の高さ
なお、内包領域の側壁と積層欠陥とのなす角度をθとする場合、ライン(離散領域)から伝搬してくる積層欠陥の場合は、h≧C/tanθである。ここで、積層欠陥が{111}面に平行、内包領域の側壁が{110}の場合、θは35.3°である。
H:内包領域の高さ
S:内包領域の幅
H={L+(C-S)/2}/tanθ+{h-(C+S)/2/tanθ}
=(L-S)/tanθ+h≧(L+C-S)/tanθ ・ ・ ・(6)
となる。
この(6)式においてL+Cは、隣り合う内包領域13の中心間距離Pであるため、以下に示す(7)式のように変換することができる。
H≧(P-S)/tanθ ・ ・ ・(7)
上述した(a)と同様、図12に基づき成長前の離散領域を離散領域210とする。次に、図22に示すように、成長前の基板における各パラメータと内包領域13に関係する各パラメータを以下に示すように規定する。
L:成長前の離散領域幅
C:成長前のスペース幅
h:成長前の離散領域の高さ
なお、内包領域の側壁と積層欠陥とのなす角度をθとする場合、ライン(離散領域)から伝搬してくる積層欠陥の場合は、h<C/tanθである。ここで、積層欠陥が{111}面に平行、内包領域の側壁が{110}の場合、θは35.3°である。
H:内包領域の高さ
S:内包領域の幅
H={L+C+(C-S)/2}/tanθ-(C+S)/2/tanθ
=(L+C-S)/tanθ ・ ・ ・(8)
となる。
この(8)式においてL+Cは、隣り合う内包領域13の中心間距離Pであるため、上述した(7)式を満たすことになる。
H≧(P-S)/tanθ ・ ・ ・ (7)
このようにして導出された(7)式において、隣り合う内包領域13の中心間距離Pと内包領域の幅Sの差P-Sは、(1)式における隣り合う内包領域の幅Wに他ならず、上述した(1)式を満たす。
第1実施形態においては、(I)~(III)において説明した製造手順を実行することで、内部に炭化珪素との界面に不整合界面を形成する内包領域を有する。これにより、不整合界面にて、炭化珪素内の積層欠陥の伝搬を遮断することができるため、炭化珪素基板の表面を低積層欠陥密度とすることができる。これにより、半導体デバイス用基板として好ましい炭化珪素基板となる。
また、{0001}面を主表面とした六方晶炭化珪素を用いる場合には、内包領域の側壁を{11-20}面または{-1100}面と平行にする。この場合、積層欠陥が伝播する最稠密面は(0001)面であり、積層欠陥は主表面と30~60度の角度で交わるので、本実施形態における上述の各工程を実施することで、本実施形態と同様の効果を得ることができる。
以下に、本発明の第2実施形態に係る炭化珪素基板について説明する。
以下に、本発明の第3実施形態に係る炭化珪素基板について説明する。
また、上述した各実施形態における構成要素は適宜、既存の構成要素などとの置き換えが可能であり、また、他の既存の構成要素との組み合わせを含む様々なバリエーションが可能である。したがって、上述した各実施形態の記載をもって、特許請求の範囲に記載された発明の内容を限定するものではない。
11;立方晶炭化珪素
12;主表面
13;内包領域
14;積層欠陥
Claims (12)
- 少なくとも内部に積層欠陥を有する炭化珪素基板において、
前記基板の内部に前記炭化珪素との界面に不整合界面を形成する内包領域を有し、
前記不整合界面において、炭化珪素内の積層欠陥の伝搬が遮断されていること
を特徴とする炭化珪素基板。 - 前記内包領域は、珪素、炭素、窒素、水素、ヘリウム、ネオン、アルゴン、クリプトン、キセノンのうち少なくとも1つを含んでいること
を特徴とする請求項1記載の炭化珪素基板。 - 前記内包領域は、空間であることを特徴とする請求項1記載の炭化珪素基板。
- 当該炭化珪素基板は、略平行かつ異なる積層欠陥密度を有する二つの平面を有し、
前記炭化珪素と内包領域との不整合界面において、前記平面のうち積層欠陥密度の高い面側から積層欠陥密度の低い面への積層欠陥の伝搬が遮断されていること
を特徴とする請求項1乃至請求項3のいずれか1項に記載の炭化珪素基板。 - 前記内包領域は、当該炭化珪素基板の厚さ方向と平行な方向である高さをHとした場合に、幅S、互いに隣り合う内包領域との中心間距離をP、積層欠陥と前記不整合界面とのなす角をθとすると、
H≧(P-S)/tanθを満たすこと
を特徴とする請求項1乃至請求項4のいずれか1項に記載の炭化珪素基板。 - 少なくとも内部に積層欠陥を有し、かつ、少なくとも1つ以上の主表面を有する炭化珪素基板であって、
内部に複数の内包領域を備え、
前記複数の内包領域は、前記主表面の1つにほぼ平行に分布し、
前記積層欠陥が、前記内包領域との界面である側壁で伝搬が遮断されており、
前記内包領域は、当該炭化珪素基板の厚さ方向と平行な方向である高さをHとした場合に、幅S、互いに隣り合う内包領域との中心間距離をP、積層欠陥と前記側壁とのなす角をθとすると、
H≧(P-S)/tanθを満たすこと
を特徴とする炭化珪素基板。 - 前記炭化珪素基板は、立方晶炭化珪素であり、主表面が{001}面であり、
前記不整合界面が、{110}面に平行であること
を特徴とする請求項1乃至6のいずれか1項に記載の炭化珪素基板。 - 前記炭化珪素基板は、立方晶炭化珪素であり、主表面が{111}面であり、
前記不整合界面が、{111}面、{110}面、{211}面のいずれかに平行であること
を特徴とする請求項1乃至6のいずれか1項に記載の炭化珪素基板。 - 前記炭化珪素基板は、六方晶炭化珪素であり、主表面が{0001}面であり、
前記不整合界面が、{11-20}面または{―1100}面に平行であること
を特徴とする請求項1乃至6のいずれか1項に記載の炭化珪素基板。 - 請求項1~9いずれか1項に記載の炭化珪素基板を用いて形成された半導体素子であって、
前記炭化珪素基板表面には、前記炭化珪素基板を形成する炭化珪素と同一結晶構造の炭化珪素層が形成され、
前記炭化珪素層には、内部電界が形成されることを特徴とする半導体素子。 - (001)面を表面とする炭化珪素基板に{110}面を側壁として有する複数の離散領域を形成する工程と、
前記炭化珪素基板上にホモエピタキシャル成長する工程と、を有し、
前記ホモエピタキシャル成長する工程は、以下に示す(2)式を満たすように成長させる工程を備えること
を特徴とする炭化珪素基板の製造方法。
rg[001]×tan35.3°-rg[110]>0 ・ ・ ・(2)
なお、rg[001]は、[001]方向の結晶成長速度であり、rg[110]は、[110]方向の結晶成長速度である。 - 前記炭化珪素基板上にホモエピタキシャル成長する工程の後、前記複数の離散領域同士の上端を横方向成長させて互いに連結させる工程を備えること
を特徴とする請求項11記載の炭化珪素基板の製造方法。
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JPH0251369A (ja) * | 1988-08-12 | 1990-02-21 | Alps Electric Co Ltd | 超音波ソレノイド |
WO2012157670A1 (ja) * | 2011-05-18 | 2012-11-22 | Hoya株式会社 | 炭化珪素基板 |
JP2015020945A (ja) * | 2013-07-17 | 2015-02-02 | 国立大学法人東北大学 | 炭化珪素基板ならびに半導体素子 |
JP2015086123A (ja) * | 2013-11-01 | 2015-05-07 | 国立大学法人東北大学 | 炭化珪素基板、炭化珪素基板製造方法、半導体素子 |
WO2018151189A1 (ja) | 2017-02-16 | 2018-08-23 | 信越化学工業株式会社 | 化合物半導体積層基板及びその製造方法、並びに半導体素子 |
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US9536954B2 (en) * | 2014-10-31 | 2017-01-03 | Seiko Epson Corporation | Substrate with silicon carbide film, semiconductor device, and method for producing substrate with silicon carbide film |
US9558943B1 (en) * | 2015-07-13 | 2017-01-31 | Globalfoundries Inc. | Stress relaxed buffer layer on textured silicon surface |
US9564494B1 (en) * | 2015-11-18 | 2017-02-07 | International Business Machines Corporation | Enhanced defect reduction for heteroepitaxy by seed shape engineering |
WO2017090279A1 (ja) * | 2015-11-24 | 2017-06-01 | 住友電気工業株式会社 | 炭化珪素単結晶基板、炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法 |
US10017182B2 (en) | 2016-06-28 | 2018-07-10 | Ford Global Technologies, Llc | System and method for controlling a torque converter clutch |
US10011283B2 (en) | 2016-06-28 | 2018-07-03 | Ford Global Technologies, Llc | System and method for driving vehicle accessories |
JP6782263B2 (ja) | 2018-02-07 | 2020-11-11 | 株式会社東芝 | 半導体装置、基板、半導体装置の製造方法、及び、基板の製造方法 |
JP6808668B2 (ja) | 2018-03-13 | 2021-01-06 | 株式会社東芝 | 半導体記憶装置、半導体記憶装置の制御方法、そのプログラム及び半導体記憶装置の製造方法 |
CN109300787B (zh) * | 2018-09-21 | 2019-07-12 | 苏州汉骅半导体有限公司 | 回收碳面极性碳化硅衬底的方法 |
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- 2011-11-15 WO PCT/JP2011/076226 patent/WO2012067079A1/ja active Application Filing
- 2011-11-15 WO PCT/JP2011/076280 patent/WO2012067105A1/ja active Application Filing
- 2011-11-15 US US13/885,573 patent/US20130228797A1/en not_active Abandoned
- 2011-11-15 TW TW100141794A patent/TW201232772A/zh unknown
- 2011-11-15 JP JP2012544255A patent/JP5945505B2/ja not_active Expired - Fee Related
- 2011-11-15 JP JP2012544244A patent/JPWO2012067079A1/ja active Pending
- 2011-11-15 TW TW100141780A patent/TW201234611A/zh unknown
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WO2012157670A1 (ja) * | 2011-05-18 | 2012-11-22 | Hoya株式会社 | 炭化珪素基板 |
JP2015020945A (ja) * | 2013-07-17 | 2015-02-02 | 国立大学法人東北大学 | 炭化珪素基板ならびに半導体素子 |
JP2015086123A (ja) * | 2013-11-01 | 2015-05-07 | 国立大学法人東北大学 | 炭化珪素基板、炭化珪素基板製造方法、半導体素子 |
WO2018151189A1 (ja) | 2017-02-16 | 2018-08-23 | 信越化学工業株式会社 | 化合物半導体積層基板及びその製造方法、並びに半導体素子 |
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Also Published As
Publication number | Publication date |
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TW201232772A (en) | 2012-08-01 |
US20130228797A1 (en) | 2013-09-05 |
JPWO2012067105A1 (ja) | 2014-05-12 |
JP5945505B2 (ja) | 2016-07-05 |
US20130234164A1 (en) | 2013-09-12 |
TW201234611A (en) | 2012-08-16 |
US8890170B2 (en) | 2014-11-18 |
WO2012067079A1 (ja) | 2012-05-24 |
JPWO2012067079A1 (ja) | 2014-05-12 |
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