US20090236261A1 - Electronic component accommodating device - Google Patents

Electronic component accommodating device Download PDF

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Publication number
US20090236261A1
US20090236261A1 US12/477,984 US47798409A US2009236261A1 US 20090236261 A1 US20090236261 A1 US 20090236261A1 US 47798409 A US47798409 A US 47798409A US 2009236261 A1 US2009236261 A1 US 2009236261A1
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US
United States
Prior art keywords
electronic component
semiconductor device
accommodating device
component accommodating
tray
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/477,984
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English (en)
Inventor
Yuuji Hasegawa
Yukio Ando
Keiichi Sasamura
Hideyasu Hashiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Assigned to FUJITSU MICROELECTRONICS LIMITED reassignment FUJITSU MICROELECTRONICS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ANDO, YUKIO, SASAMURA, KEIICHI, HASEGAWA, YUUJI, HASHIBA, HIDEYASU
Publication of US20090236261A1 publication Critical patent/US20090236261A1/en
Assigned to FUJITSU SEMICONDUCTOR LIMITED reassignment FUJITSU SEMICONDUCTOR LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU MICROELECTRONICS LIMITED
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/67333—Trays for chips
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D85/00—Containers, packaging elements or packages, specially adapted for particular articles or materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D1/00—Containers having bodies formed in one piece, e.g. by casting metallic material, by moulding plastics, by blowing vitreous material, by throwing ceramic material, by moulding pulped fibrous material, by deep-drawing operations performed on sheet material
    • B65D1/34—Trays or like shallow containers
    • B65D1/36—Trays or like shallow containers with moulded compartments or partitions
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D21/00—Nestable, stackable or joinable containers; Containers of variable capacity
    • B65D21/02—Containers specially shaped, or provided with fittings or attachments, to facilitate nesting, stacking, or joining together
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders

Definitions

  • the embodiments discussed herein are related to electronic component accommodating devices.
  • FIG. 1 is a view illustrating a related art semiconductor device accommodating tray.
  • FIG. 1( a ) is a plan view of the tray and
  • FIG. 1( b ) is a cross-sectional view taken along a line X-X in a state where two of the trays are stacked.
  • a semiconductor device accommodating tray 10 is a molded article made of a material such as plastic.
  • the semiconductor device accommodating tray 10 has, as discussed below, a step configuration. Therefore, plural semiconductor device accommodating trays 10 can be stacked in a vertical direction. In an example illustrated in FIG. 1 , two semiconductor device accommodating trays 10 - 1 and 10 - 2 are stacked in the vertical direction.
  • Plural concave-shaped accommodating parts 1 are formed at an upper surface of the semiconductor device accommodating tray 10 , so that semiconductor devices are accommodated inside the concave-shaped accommodating parts 1 .
  • FIG. 2( a ) is an expanded view of a part surrounded by a dotted line A in FIG. 1 .
  • FIG. 2( b ) is an expanded view of a part surrounded by a dotted line B in FIG. 1 .
  • flanges 2 - 1 and 2 - 1 are formed in the vicinities of side end parts at lower surfaces of the semiconductor device accommodating trays 10 - 1 and 10 - 2 so as to extend downward.
  • Side surfaces at center sides of the semiconductor device accommodating trays 10 - 1 and 10 - 2 of the flanges 2 - 1 and 2 - 2 are formed so as to incline the side end parts of the semiconductor device accommodating trays 10 - 1 and 10 - 2 from the vertical direction.
  • the side surfaces at the center sides of the semiconductor device accommodating trays 10 - 1 and 10 - 2 of the flanges 2 - 1 and 2 - 2 are inclined from a horizontal surface at approximately 83 degrees.
  • tray upper side surface side wall parts 3 - 1 and 3 - 2 are formed in the vicinities of the side end parts at the upper surfaces of the semiconductor device accommodating trays 10 - 1 and 10 - 2 so as to extend upward.
  • the tray upper side surface side wall parts 3 - 1 and 3 - 2 form side wall parts of the concave-shaped accommodating parts 1 positioned at the outermost circumferential sides of upper surfaces of the semiconductor device accommodating trays 10 - 1 and 10 - 2 .
  • semiconductor devices 4 are accommodated in the concave-shaped accommodating parts 1 of the semiconductor device accommodating tray 10 - 2 .
  • the side surfaces of the semiconductor device accommodating trays 10 - 1 and 10 - 2 at the side end part sides of the semiconductor device accommodating trays 10 - 1 and 10 - 2 are formed so as to incline toward the center side of the semiconductor device accommodating trays 10 - 1 and 10 - 2 from the vertical direction and incline from a horizontal surface at approximately 83 degrees.
  • Japanese Laid-Open Patent Application Publication No. 6-72478 discloses a tray for a semiconductor device, the tray being equipped with a locking part to lock corner parts of a packaging main body, has been suggested.
  • Surfaces extending from ends of L shaped locking surfaces of a locking part and constituting an end of lead storage parts form an acute angle with the locking surfaces. The surfaces are constituted by retracting the end of the lead storage parts.
  • the semiconductor device accommodating tray 10 having the above-discussed structure is, as discussed above, a molded article made of a material such as plastic. Accordingly, dimensional tolerance variation due to unevenness at the time of molding may be generated. Therefore, when the semiconductor device accommodating trays 10 - 1 and 10 - 2 are stacked, as illustrated in dotted lines C and D in FIG. 2 , a gap of approximately 0.065 mm as a minimum may be formed between the side surface of the tray upper surface side wall part 3 - 2 at the side end part side of the semiconductor device accommodating tray 10 - 2 and the side surface of the flange 2 - 1 at the center side of the semiconductor device accommodating tray 10 - 1 stacked right above the semiconductor device accommodating tray 10 - 2 .
  • the semiconductor device accommodating tray 10 - 1 may have configurations where the side end part sides are deformed downward.
  • the gap formed between the side surface of the tray upper surface side wall part 3 - 2 at the side end part side of the semiconductor device accommodating trays 10 - 2 and the side surface of the flange 2 - 1 at the center side of the semiconductor device accommodating tray 10 - 1 becomes zero.
  • the semiconductor device accommodating trays 10 - 1 and 1 - 2 are in contact so that, as indicated by a dotted line in FIG. 3 , the warp where the substantially center part of the semiconductor device accommodating tray 10 - 1 is bent upward may occur.
  • FIG. 4( a ) is an expanded view of a part surrounded by a dotted line A in FIG. 3 .
  • FIG. 4( b ) is an expanded view of a part surrounded by a dotted line B in FIG. 3 .
  • the side surface at the center side of the semiconductor device accommodating tray 10 - 1 (which is stacked right above the semiconductor device accommodating tray 10 - 2 ) of the flange 2 - 1 comes in contact with the side surface of the tray upper surface side wall part 3 - 2 of the semiconductor device accommodating tray 10 - 2 at the side end part side of the semiconductor device accommodating tray 10 - 1 , so that interference is formed.
  • the gap formed between the side surface of the tray upper surface side wall part 3 - 2 at the side end part side of the semiconductor device accommodating trays 10 - 2 and the side surface of the flange 2 - 1 at the center side of the semiconductor device accommodating tray 10 - 1 becomes zero.
  • the side surface of the flange 2 - 1 at the center side of the semiconductor device accommodating tray 10 - 1 interferes approximately 0.1 mm with the side surface of the tray upper surface side wall part 3 - 2 of the side end part side of the semiconductor device accommodating tray 10 - 2 .
  • the semiconductor device accommodating tray 10 - 1 is engaged with the semiconductor device accommodating tray 10 - 2 , and thereby positional precision of the concave-shaped accommodating parts 1 of the semiconductor device accommodating trays 10 - 1 and 10 - 2 is degraded.
  • an electronic component accommodating device which can be stacked in plural, the electronic component accommodating device including: an upper surface side wall part extending from an upper surface of the electronic component accommodating device, the upper surface side wall part being positioned close to a flange extending from a lower surface of another electronic component accommodating device stacked on the electronic component accommodating device, wherein a side surface of the upper surface side wall part a side end part of the electronic component accommodating device is formed in a taper shape and has an inclination angle from a horizontal surface, the inclination angle being equal to or less than 60 degrees.
  • an electronic component accommodating device which can be stacked in plural, the electronic component accommodating device including: an upper surface side wall part extending from an upper surface of the electronic component accommodating device, the upper surface side wall part being positioned close to a flange extending from a lower surface of another electronic component accommodating device stacked on the electronic component accommodating device, wherein the upper surface side wall part includes a side surface positioned at a side end part side of the electronic component accommodating device; and the side surface includes a first surface formed in a taper manner from the upper surface of the electronic component accommodating device, the first surface having an inclination angle from a horizontal surface equal to or less than 60 degrees.
  • FIG. 1 is a view illustrating a related art semiconductor device accommodating tray
  • FIG. 2 is an expanded view of a part surrounded by a dotted line in FIG. 1 ;
  • FIG. 3 is a view for explaining problems of the semiconductor device accommodating tray illustrated in FIG. 1 ;
  • FIG. 4 is an expanded view of a part surrounded by a dotted line in FIG. 3 ;
  • FIG. 5 is a view illustrating a semiconductor device accommodating tray of an embodiment
  • FIG. 6 is an expanded view of a part surrounded by a dotted line in FIG. 5 ;
  • FIG. 7 is a view showing a state where a warp is generated in the semiconductor device accommodating tray illustrated in FIG. 5 ;
  • FIG. 8 is an expanded view of a part surrounded by a dotted line in FIG. 7 ;
  • FIG. 9 is a view of a part surrounded by a dotted line C in FIG. 7 ;
  • FIG. 10 is a view illustrating a first modified example of the semiconductor device accommodating tray illustrating in FIG. 6 and FIG. 8 ;
  • FIG. 11 is a view showing a state where a warp is generated in the semiconductor device accommodating tray illustrated in FIG. 10 ;
  • FIG. 12 is a view illustrating a second modified example of the semiconductor device accommodating tray illustrating in FIG. 6 and FIG. 8 .
  • the embodiments of the present invention may provide a novel and useful electronic component accommodating device which can be stacked in plural, the electronic component accommodating device having a configuration whereby even if an upward warp of the substantially center part is generated in a state where the electronic component accommodating device is stacked on another electronic component accommodating device, it is possible to prevent the electronic component accommodating device from being engaged with the other electronic component accommodating device.
  • a semiconductor device accommodating device of an embodiment is discussed with reference to FIG. 5 through FIG. 12 .
  • FIG. 5 is a view illustrating a semiconductor device accommodating tray 50 of the embodiment.
  • FIG. 5( a ) is a plan view of the tray 50 and
  • FIG. 5( b ) is a cross-sectional view taken along a line X-X in a state where two of the trays 50 are stacked.
  • the semiconductor device accommodating tray 50 is a molded article made of plastic resin such as polystyrene (PS) or polyphenylene ether (PPE).
  • PS polystyrene
  • PPE polyphenylene ether
  • the semiconductor device accommodating tray 50 has, as discussed below, a step configuration. Therefore, plural semiconductor device accommodating trays 50 can be stacked in a vertical direction. In an example illustrated in FIG. 5 , two semiconductor device accommodating trays 50 - 1 and 50 - 2 are stacked in the vertical direction.
  • Plural concave-shaped accommodating parts 41 are formed at an upper surface of the semiconductor device accommodating tray 50 , so that semiconductor devices are accommodated inside the concave-shaped accommodating parts 41 .
  • FIG. 6( a ) is an expanded view of a part surrounded by a dotted line A in FIG. 5 .
  • FIG. 6( b ) is an expanded view of a part surrounded by a dotted line B in FIG. 5 .
  • flanges 42 - 1 and 42 - 2 are formed in the vicinities of side end parts at lower surfaces of the semiconductor device accommodating trays 50 - 1 and 50 - 2 so as to extend downward.
  • Side surfaces of the flanges 42 - 1 and 42 - 2 at center sides of the semiconductor device accommodating trays 50 - 1 and 50 - 2 are formed so as to have the side end parts of the semiconductor device accommodating trays 50 - 1 and 50 - 2 inclined from the vertical direction.
  • tray upper side surface side wall parts 43 - 1 and 43 - 2 are formed in the vicinities of the side end parts at the upper surfaces of the semiconductor device accommodating trays 50 - 1 and 50 - 2 so as to extend upward.
  • the tray upper side surface side wall parts 43 - 1 and 43 - 2 form side wall parts 41 - 1 and 41 - 2 of the concave-shaped accommodating parts 41 positioned at outermost circumferential sides of upper surfaces of the semiconductor device accommodating trays 50 - 1 and 50 - 2 .
  • semiconductor devices 44 are accommodated in the concave-shaped accommodating parts 41 of the semiconductor device accommodating tray 50 - 2 .
  • the side surface of the tray upper surface side wall part 43 - 2 at the side end part side of the semiconductor device accommodating tray 50 - 2 is formed so as to be inclined (in a taper state) from the vertical direction to the center side of the semiconductor device accommodating tray 50 - 2 and has an inclination angle from the horizontal surface equal to or less than approximately 60 degrees.
  • the semiconductor device accommodating tray 50 is a molded article made of plastic resin such as polystyrene (PS) or polyphenylene ether (PPE). Accordingly, the semiconductor device accommodating tray 50 may have dimensional tolerance variation due to unevenness at the time of molding or the like. Accordingly, when the semiconductor device accommodating tray 50 - 1 and the semiconductor device accommodating tray 50 - 2 are stacked, as illustrated in dotted lines C and D in FIG.
  • gaps having a length of approximately 0.065 mm as minimum can be generated between the side surfaces of the tray upper surface side wall parts 43 - 2 at the side end part sides of the semiconductor device accommodating tray 50 - 2 and the side surfaces of the flanges 42 - 1 at the lower edge part of the center side of the semiconductor device accommodating tray 50 - 1 stacked right above the semiconductor device accommodating tray 50 - 2 .
  • the semiconductor device accommodating tray 50 - 1 may have configurations where the side end part sides are deformed downward.
  • the gaps formed between the side surfaces of the tray upper surface side wall parts 43 - 2 at the side end part side of the semiconductor device accommodating tray 50 - 2 and the side surfaces of the flanges 42 - 1 at the center side of the semiconductor device accommodating tray 50 - 1 become zero.
  • the semiconductor device accommodating trays 50 - 1 and 50 - 2 are in contact so that, as indicated by a dotted line in FIG. 7 , the warp where the substantially center part of the semiconductor device accommodating tray 50 - 1 is bent upward may occur.
  • the side surfaces of the tray upper surface side wall parts 43 - 2 at the side end part side of the semiconductor device accommodating tray 50 - 2 are formed so as to be inclined (in a taper state) from the vertical direction to the center side of the semiconductor device accommodating tray 50 - 2 and have inclination angles from the horizontal surface equal to or less than approximately 60 degrees. Accordingly, in this example unlike the example illustrated in FIG. 4 , even if the warp occurs where the substantially center part of the semiconductor device accommodating tray 50 - 1 is bent upward, the semiconductor device accommodating tray 50 - 1 is not engaged with the semiconductor device accommodating tray 50 - 2 .
  • FIG. 8( a ) is an expanded view of a part surrounded by a dotted line A.
  • FIG. 8( a ) is an expanded view of a part surrounded by a dotted line A in FIG. 7 .
  • FIG. 8( b ) is an expanded view of a part surrounded by a dotted line B in FIG. 7 .
  • FIG. 9 is an expanded view of a part surrounded by a dotted line C in FIG. 8 .
  • the lower edge parts 42 - 1 a of the flanges 42 - 1 of the semiconductor device accommodating tray 50 - 1 at the center side of the semiconductor device accommodating tray 50 - 1 slide on the side surfaces 43 - 2 a of the tray upper surface side wall parts 43 - 2 at the side end part sides of the semiconductor device accommodating tray 50 - 2 which have inclination angles from the horizontal surface equal to or less than approximately 60 degrees.
  • the side surface of the tray upper surface side wall part 3 - 2 (corresponding to tray upper surface side wall part 43 - 2 ) at the side end part side of the semiconductor device accommodating tray 10 - 2 (corresponding to the semiconductor device accommodating tray 50 - 2 ) is formed so as to be inclined from the horizontal surface at approximately 83 degrees. Therefore, as discussed above, the side surface of the flange 2 - 1 at the center side of the semiconductor device accommodating tray 10 - 1 interferes approximately 0.1 mm with the side surface of the tray upper surface side wall part 3 - 2 of the side end part side of the semiconductor device accommodating tray 10 - 2 .
  • the side surface 43 - 2 a of the tray upper surface side wall part 43 - 2 at the side end part side of the semiconductor device accommodating tray 50 - 2 has an inclination angle from the horizontal surface equal to or less than approximately 60 degrees.
  • the inventors grasp through simulation that in a case where the inclination angle from the horizontal surface of the side surface 43 - 2 a of the tray upper surface side wall part 43 - 2 at the side end part side of the semiconductor device accommodating tray 50 - 2 is greater than approximately 60 degrees, the lower edge part 42 - 1 a of the flange 42 - 1 of the semiconductor device accommodating tray 50 - 1 at the center side of the semiconductor device accommodating tray 50 - 1 comes in contact with the side surface 43 - 2 a of the tray upper surface side wall part 43 - 2 at the side end part side of the semiconductor device accommodating tray 50 - 2 so that the interference occurs.
  • the semiconductor device accommodating tray 50 - 1 is not engaged with the semiconductor device accommodating tray 50 - 2 .
  • the side surfaces of the flanges 42 - 1 and 42 - 2 of the semiconductor device accommodating trays 50 - 1 and 50 - 2 at the center sides of the semiconductor device accommodating trays 50 - 1 and 50 - 2 are formed so as to be inclined toward the side end parts of the semiconductor device accommodating trays 50 - 1 and 50 - 2 from the vertical direction.
  • the inclination angle there is no limitation of the inclination angle.
  • FIG. 10 illustrates a state where a semiconductor device accommodating tray 50 - 1 ′ which is a modified example of the semiconductor device accommodating tray 50 - 1 illustrated in FIG. 6 is stacked on the semiconductor device accommodating tray 50 - 2 illustrated in FIG. 6 .
  • FIG. 10( a ) corresponds to FIG. 6( a )
  • FIG. 10( b ) corresponds to FIG. 6( b ).
  • parts that are the same as the parts depicted in FIG. 6 are given the same reference numerals, and explanation thereof is omitted.
  • a flange 42 - 1 ′ is formed at a lower surface of the semiconductor device accommodating tray 50 - 1 ′ and in the vicinity of the side end part of the semiconductor device accommodating tray 50 - 1 ′ so as to extend downward.
  • the side surface of the flange 42 - 1 ′ at the center side of the semiconductor device accommodating tray 50 - 1 ′ is formed so as to be inclined (in a taper state) from the vertical direction to the side end part of the semiconductor device accommodating tray 50 - 1 ′ and has an inclination angle from the horizontal surface equal to or less than approximately 60 degrees, which is the same as the inclination angle of the tray upper surface side wall part 43 - 2 .
  • FIG. 11( a ) corresponds to FIG. 10( a )
  • FIG. 11( b ) corresponds to FIG. 10( b ).
  • An inclination angle of the side surface of the flange 42 - 1 ′ at the center side of the semiconductor device accommodating tray 50 - 1 ′ from the horizontal surface is equal to or smaller than approximately 60 degrees which is substantially the same as the inclination angle of the tray upper surface side wall part 43 - 2 . Therefore, as indicated by a dotted line in FIG.
  • the side surfaces 42 - 1 a ′ of the flanges 42 - 1 ′ at the center side of the semiconductor device accommodating tray 50 - 1 ′ are received on the side surfaces 43 - 2 a ′ of the tray upper surface side wall parts 43 - 2 at the side end part sides of the semiconductor device accommodating tray 50 - 2 .
  • the side surface 42 - 1 a ′ of the flange 42 - 1 ′ at the center side of the semiconductor device accommodating tray 50 - 1 ′ is received on the side surface 43 - 2 a ′ of the tray upper surface side wall part 43 - 2 at the side end part side of the semiconductor device accommodating tray 50 - 2 . Therefore, it is possible to prevent generation of a positional shift in a horizontal direction between the semiconductor device accommodating trays 50 - 1 ′ and 50 - 2 .
  • An inclination angle of the side surface of the flange 42 - 1 a ′ of the flange 42 - 1 ′ of the semiconductor device accommodating tray 50 - 1 at the center side of the semiconductor device accommodating tray 50 - 1 ′ from the horizontal surface is equal to or smaller than approximately 60 degrees. Therefore, in this example compared to the examples illustrated in FIG. 6 and FIG. 8 , the width of the semiconductor device accommodating tray 50 - 1 ′ is increased so that rigidity of the semiconductor device accommodating tray 50 - 1 ′ is improved. Accordingly, it is possible to reduce generation of the warp where the substantially center part of the semiconductor device accommodating tray 50 - 1 ′ is curved upward.
  • the side surface 43 - 2 a of the tray upper side surface wall part 43 - 2 at the side end part of the semiconductor device accommodating tray 50 - 2 has a plane surface where any part has an inclination angle from the horizontal surface equal to or less than approximately 60 degrees (See FIG. 9 ).
  • the embodiment is not limited to such an example and an example illustrated in FIG. 12 can be applied.
  • FIG. 12 illustrates a state where the semiconductor device accommodating tray 50 - 2 illustrated in FIG. 6 is stacked on a semiconductor device accommodating tray 50 - 2 ′ which is a modified example of the semiconductor device accommodating tray 50 - 2 illustrated in FIG. 6 .
  • FIG. 12( a ) corresponds to FIG. 6( a )
  • FIG. 12( b ) is an expanded view of a part surrounded by a dotted line in FIG. 12( a ).
  • parts that are the same as the parts depicted in FIG. 6 are given the same reference numerals, and explanation thereof is omitted.
  • a tray upper side surface side wall part 43 - 2 ′ is formed at the upper surface of the semiconductor device accommodating tray 50 - 2 ′ in the vicinity of the side end part at the upper surfaces of the semiconductor device accommodating tray 50 - 2 ′ so as to extend upward.
  • the side surface of the tray upper surface side wall part 43 - 2 ′ at the side end part side of the semiconductor device accommodating tray 50 - 2 ′ is formed by a first side surface part 43 - 2 ′ b extending from the upper surface of the semiconductor device accommodating tray 50 - 2 ′ formed obliquely upward with an inclination angle equal to or less than approximately 60 degrees and a second side surface part 43 - 2 ′ c extending obliquely upward with a designated angle ⁇ from the first upper surface part 43 - 2 ′ b .
  • the second side surface part 43 - 2 ′ c extends from the first side surface part 43 - 2 ′ b with an inclination angle from the upper surface of the semiconductor device accommodating tray 50 - 2 ′ which is a horizontal surface, the angle being different from an inclination angle of the first side surface part 43 - 2 ′ b which is equal to or less than 60 degrees.
  • the semiconductor device accommodating tray 50 - 1 is not engaged with the semiconductor device accommodating tray 50 - 2 . Therefore, it is possible to prevent positional precision of the concave-shaped accommodating parts 41 of the semiconductor device accommodating trays 50 - 1 and 50 - 2 from being degraded.
  • the side surface of the tray upper surface side wall part 43 - 2 ′ at the side end part side of the semiconductor device accommodating tray 50 - 2 ′ has a two surfaces structure formed by the first side surface part 43 - 2 ′ b and the second side surface part 43 - 2 ′ c .
  • the side surface at the side end part side of the semiconductor device accommodating tray 50 - 2 ′ may have a multi surfaces structure having at least three or more surfaces.
  • the first side surface part 43 - 2 ′ b is formed at the side surface of the tray upper surface side wall part 43 - 2 ′ at the side end part side of the semiconductor device accommodating tray 50 - 2 ′ so as to extend, obliquely upward, with an inclination angle equal to or less than approximately 60 degrees from the upper surface of the semiconductor device accommodating tray 50 - 2 ′
  • the semiconductor device accommodating tray configured to accommodate the semiconductor devices is discussed in the description above as an example, the electronic component accommodating device of the embodiment can be applied to a device configured to accommodate electronic components other than the semiconductor devices.
  • an electronic components accommodating device which can be stacked in plural, the electronic component accommodating device having a configuration whereby even if an upward warp of the substantially center part is generated in a state where the electronic component accommodating device is stacked on another electronic component accommodating device, it is possible to prevent the electronic component accommodating device from being engaged with the other electronic component accommodating device.
  • the embodiment can be applied to an electronic component accommodating device configured to accommodate electronic components such as semiconductor devices so that the electronic components are carried.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Packaging Frangible Articles (AREA)
  • Stackable Containers (AREA)
  • Containers Having Bodies Formed In One Piece (AREA)
  • Ceramic Capacitors (AREA)
US12/477,984 2007-03-16 2009-06-04 Electronic component accommodating device Abandoned US20090236261A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/055435 WO2008114366A1 (ja) 2007-03-16 2007-03-16 電子部品収納容器

Related Parent Applications (1)

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PCT/JP2007/055435 Continuation WO2008114366A1 (ja) 2007-03-16 2007-03-16 電子部品収納容器

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US (1) US20090236261A1 (ja)
JP (1) JP4832568B2 (ja)
KR (1) KR20090092302A (ja)
CN (1) CN101573277A (ja)
WO (1) WO2008114366A1 (ja)

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JP5051797B2 (ja) * 2010-05-06 2012-10-17 シノン電気産業株式会社 半導体集積回路用トレー
CN110239811B (zh) * 2018-03-07 2021-09-03 奥特斯科技(重庆)有限公司 用于处理载板件的托盘装置
TWI681914B (zh) * 2019-03-28 2020-01-11 日商東京威爾斯股份有限公司 電子零件收納裝置

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US5492223A (en) * 1994-02-04 1996-02-20 Motorola, Inc. Interlocking and invertible semiconductor device tray and test contactor mating thereto
US6357595B2 (en) * 1999-04-30 2002-03-19 Nec Corporation Tray for semiconductor integrated circuit device
US6769549B2 (en) * 2000-07-11 2004-08-03 Oki Electric Industry Co., Ltd. Embossed carrier tape for electronic devices
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JP4832568B2 (ja) 2011-12-07
CN101573277A (zh) 2009-11-04

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