US20090085222A1 - Electronic apparatus and manufacturing method thereof - Google Patents

Electronic apparatus and manufacturing method thereof Download PDF

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Publication number
US20090085222A1
US20090085222A1 US12/238,699 US23869908A US2009085222A1 US 20090085222 A1 US20090085222 A1 US 20090085222A1 US 23869908 A US23869908 A US 23869908A US 2009085222 A1 US2009085222 A1 US 2009085222A1
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Prior art keywords
semiconductor
apparatuses
disposed
electronic apparatus
semiconductor apparatuses
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US12/238,699
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English (en)
Inventor
Takaharu Yamano
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Assigned to SHINKO ELECTRIC INDUSTRIES CO., LTD. reassignment SHINKO ELECTRIC INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YAMANO, TAKAHARU
Publication of US20090085222A1 publication Critical patent/US20090085222A1/en
Priority to US12/588,076 priority Critical patent/US7875499B2/en
Abandoned legal-status Critical Current

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    • H01L2924/3511—Warping

Definitions

  • the present disclosure relates to an electronic apparatus and a manufacturing method thereof, and relates to an electronic apparatus comprising a plurality of semiconductor chips stacked on a wiring substrate and a sealing resin with which the plurality of semiconductor chips are sealed, and a manufacturing method of the electronic apparatus.
  • FIG. 1 is a sectional diagram of a related-art electronic apparatus.
  • a related-art electronic component 200 has a wiring substrate 201 , semiconductor chips 202 to 204 , a sealing resin 205 and external connection terminals 206 .
  • the wiring substrate 201 has a core substrate 211 , through vias 212 , pads 213 , 216 , and solder resists 214 , 217 .
  • the core substrate 211 is a substrate formed in a plate shape and has through holes 219 .
  • the through vias 212 are disposed in the through holes 219 .
  • the upper end of the through via 212 is connected to the pad 213 and the lower end of the through via 212 is connected to the pad 216 .
  • the pad 213 is disposed on an upper surface 211 A of the core substrate 211 .
  • the pad 213 is connected to the upper end of the through via 212 .
  • the pad 213 is connected to a metal wire 222 electrically connected to the semiconductor chip 202 .
  • the solder resist 214 is disposed on the upper surface 211 A of the core substrate 211 so as to expose the pad 213 .
  • the pad 216 is disposed on a lower surface 211 B of the core substrate 211 .
  • the pad 216 is connected to the lower end of the through via 212 .
  • the external connection terminal 206 is disposed on the pad 216 .
  • the solder resist 217 is disposed on the lower surface 211 B of the core substrate 211 so as to expose the pad 216 .
  • the semiconductor chip 202 has a semiconductor substrate 226 , a semiconductor integrated circuit 227 , electrode pads 228 and a protective film 229 .
  • the semiconductor integrated circuit 227 is disposed on the upper surface side of the semiconductor substrate 226 .
  • the electrode pad 228 is disposed on the semiconductor integrated circuit 227 and is electrically connected to the semiconductor integrated circuit 227 .
  • the metal wire 222 connected to the pad 213 of the wiring substrate 201 is connected to the electrode pad 228 . Consequently, the semiconductor chip 202 is electrically connected to the wiring substrate 201 .
  • the protective film 229 is disposed on the semiconductor integrated circuit 227 so as to expose the electrode pads 228 .
  • the semiconductor chip 202 constructed above is a chip in which a short open test is passed.
  • the semiconductor chip 202 is a chip in which a functional inspection (concretely, an action check of the semiconductor integrated circuit 227 disposed in the semiconductor chip 202 (for example, a check of the presence or absence of a reading error)) is not made. That is, the semiconductor chip 202 is not a KGD (Known Good Die).
  • the semiconductor chip 202 is glued on the solder resist 214 of the wiring substrate 201 by a sticky layer 232 stuck on a lower surface of the semiconductor substrate 226 .
  • the semiconductor chip 203 has a semiconductor substrate 234 , a semiconductor integrated circuit 235 , electrode pads 236 and a protective film 237 .
  • the semiconductor integrated circuit 235 is disposed on the upper surface side of the semiconductor substrate 234 .
  • the electrode pad 236 is disposed on the semiconductor integrated circuit 235 and is electrically connected to the semiconductor integrated circuit 235 .
  • a metal wire 223 connected to the electrode pad 228 of the semiconductor chip 202 and a metal wire 224 connected to an electrode pad 244 of the semiconductor chip 204 are connected to the electrode pad 236 . Consequently, the semiconductor chip 203 is electrically connected to the semiconductor chips 202 , 204 .
  • the protective film 237 is disposed on the semiconductor integrated circuit 235 so as to expose the electrode pads 236 .
  • the semiconductor chip 203 constructed above is a chip in which a short open test is passed.
  • the semiconductor chip 203 is a chip in which a functional inspection (concretely, an action check of the semiconductor integrated circuit 235 disposed in the semiconductor chip 203 (for example, a check of the presence or absence of a reading error)) is not made. That is, the semiconductor chip 203 is not a KGD (Known Good Die).
  • the semiconductor chip 203 is glued on the protective film 229 of the semiconductor chip 202 by a sticky layer 232 stuck on a lower surface of the semiconductor substrate 234 .
  • the semiconductor chip 204 has a semiconductor substrate 242 , a semiconductor integrated circuit 243 , electrode pads 244 and a protective film 245 .
  • the semiconductor integrated circuit 243 is disposed on the upper surface side of the semiconductor substrate 242 .
  • the electrode pad 244 is disposed on the semiconductor integrated circuit 243 and is electrically connected to the semiconductor integrated circuit 243 .
  • the metal wire 224 connected to the electrode pad 236 of the semiconductor chip 203 is connected to the electrode pad 244 . Consequently, the semiconductor chip 204 is electrically connected to the semiconductor chip 203 .
  • the protective film 245 is disposed on the semiconductor integrated circuit 243 so as to expose the electrode pads 244 .
  • the semiconductor chip 204 constructed above is a chip in which a short open test is passed.
  • the semiconductor chip 204 is a chip in which a functional inspection (concretely, an action check of the semiconductor integrated circuit 243 disposed in the semiconductor chip 204 (for example, a check of the presence or absence of a reading error)) is not made. That is, the semiconductor chip 204 is not a KGD (Known Good Die).
  • the semiconductor chip 204 is glued on the protective film 237 of the semiconductor chip 203 by a sticky layer 232 stuck on a lower surface of the semiconductor substrate 242 .
  • the semiconductor chips 202 to 204 for example, NAND type flash memory can be used.
  • the sealing resin 205 is disposed on the wiring substrate 201 so as to seal the stacked semiconductor chips 202 to 204 and the metal wires 222 to 224 .
  • a molding resin having thermosetting properties can be used as the sealing resin 205 .
  • the external connection terminal 206 is arranged on the pad 216 of the wiring substrate 201 .
  • the external connection terminal 206 is a terminal electrically connected to a mounting substrate (not shown) such as a motherboard.
  • a solder bump can be used as the external connection terminal 206 .
  • FIGS. 2 to 7 are diagrams showing manufacturing steps of the related-art electronic apparatus.
  • the same numerals are assigned to the same components as those of the related-art electronic apparatus 200 .
  • a wiring substrate 201 is manufactured by a well-known technique.
  • a plurality of semiconductor chips 202 to 204 are prepared.
  • the plurality of semiconductor chips 202 to 204 are a semiconductor chip which is not a KGD (Known Good Die).
  • sticky layers 232 are stuck on lower surfaces of semiconductor substrates 226 , 234 , 242 disposed in the semiconductor chips 202 to 204 .
  • the semiconductor chips 202 to 204 on which the sticky layers 232 are formed are sequentially stacked on the wiring substrate 201 and thereafter, wire bonding connection between the wiring substrate 201 and the semiconductor chips 202 to 204 is made using metal wires 222 to 224 .
  • the semiconductor chips 202 to 204 and the metal wires 222 to 224 are sealed with a sealing resin 205 (for example, a molding resin).
  • a sealing resin 205 for example, a molding resin.
  • the sealing resin 205 in a partially cured state is formed while applying a high pressure (for example, 5 MPa to 10 MPa) using a metal mold and thereafter, the sealing resin 205 in the partially cured state is heated (for example, 180° C.) and the sealing resin 205 is cured.
  • Patent Reference 1 Japanese Patent Unexamined Application Publication No. 2007-5800
  • the semiconductor chips 202 to 204 which are not a KGD (Known Good Die) are stacked on the wiring substrate 201 , so that there was a problem that a yield of the electronic apparatus 200 reduces.
  • KGD known Good Die
  • the sealing resin 205 was cured and packaging processing was performed.
  • a high pressure for example, 5 MPa to 10 MPa
  • a metal mold for example, a metal mold
  • heating for example, 180° C.
  • Exemplary embodiments of the present invention provide an electronic apparatus capable of improving a yield of the electronic apparatus by stacking semiconductor chips on a wiring substrate after previously performing WLP packaging processing of each of the semiconductor chips and forming a KGD before a sealing resin formation step, and a manufacturing method of the electronic apparatus.
  • an electronic apparatus comprising:
  • each of semiconductor apparatuses having a semiconductor chip having an electrode pad, an internal connection terminal disposed on the electrode pad, a resin layer which is disposed on a surface of the semiconductor chip in which the electrode pad is formed and expose the internal connection terminal, and a wiring pattern which is disposed on the resin layer and is connected to the internal connection terminal;
  • a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections made before being stacked on a wiring substrate while having resin layers which are disposed surfaces of semiconductor chips in which electrode pads are formed and expose the internal connection terminals and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals are stacked on the wiring substrate and thereby, a yield of an electronic apparatus can be improved.
  • KGD known Good Die
  • a manufacturing method of an electronic apparatus comprising a plurality of semiconductor apparatuses, a wiring substrate on which the plurality of semiconductor apparatuses are stacked, and a sealing resin with which the plurality of semiconductor apparatuses stacked on the wiring substrate are sealed, the method comprising:
  • electrical and functional inspections of a plurality of semiconductor apparatuses having resin layers which are disposed on surfaces of semiconductor chips in which electrode pads are formed and expose internal connection terminals and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals are made and the plurality of semiconductor apparatuses judged as good items are acquired and the plurality of semiconductor apparatuses (KGD (Known Good Die)) judged as the good items are stacked on the wiring substrate and then electrical connection between the wiring substrate and the stacked a plurality of semiconductor apparatuses are made and thereafter the plurality of semiconductor apparatuses are sealed with a sealing resin and thereby, a yield of an electronic apparatus can be improved.
  • KGD known Good Die
  • a yield of an electronic apparatus can be improved by preventing breakage of a semiconductor chip in a packaging processing process including a sealing resin formation step.
  • FIG. 1 is a sectional diagram of a related-art electronic apparatus.
  • FIG. 2 is a diagram showing a manufacturing step of the related-art electronic apparatus (first).
  • FIG. 3 is a diagram showing a manufacturing step of the related-art electronic apparatus (second).
  • FIG. 4 is a diagram showing a manufacturing step of the related-art electronic apparatus (third).
  • FIG. 5 is a diagram showing a manufacturing step of the related-art electronic apparatus (fourth).
  • FIG. 6 is a diagram showing a manufacturing step of the related-art electronic apparatus (fifth).
  • FIG. 7 is a diagram showing a manufacturing step of the related-art electronic apparatus (sixth).
  • FIG. 8 is a sectional diagram of an electronic apparatus according to an embodiment of the invention.
  • FIG. 9 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (first).
  • FIG. 10 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (second).
  • FIG. 11 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (third).
  • FIG. 12 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (fourth).
  • FIG. 13 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (fifth).
  • FIG. 14 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (sixth).
  • FIG. 15 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (seventh).
  • FIG. 16 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (eighth).
  • FIG. 17 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (ninth).
  • FIG. 18 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (tenth).
  • FIG. 19 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (eleventh).
  • FIG. 20 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (twelfth).
  • FIG. 21 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (thirteenth).
  • FIG. 22 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (fourteenth).
  • FIG. 23 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (fifteenth).
  • FIG. 24 is a diagram showing a manufacturing step of the electronic apparatus according to the embodiment of the invention (sixteenth).
  • FIG. 8 is a sectional diagram of an electronic apparatus according to an embodiment of the invention.
  • an electronic apparatus 10 of the present embodiment has a wiring substrate 11 , semiconductor apparatuses 12 - 1 to 12 - 3 which are a plurality of semiconductor apparatuses, a sealing resin 13 and external connection terminals 14 .
  • the wiring substrate 11 has a core substrate 21 , a through via 22 , a pad 23 , solder resists 24 , 28 , a diffusion preventive film 25 and pads 27 for external connection.
  • the core substrate 21 is a substrate formed in a plate shape and has a through hole 29 .
  • a glass epoxy resin or an FR-4 can be used as a material of the core substrate 21 .
  • the through via 22 is disposed in the through hole 29 .
  • the upper end of the through via 22 is connected to the pad 23 and the lower end of the through via 22 is connected to the pad 27 for external connection.
  • the through via 22 is a via for making electrical connection between the pad 23 and the pad 27 for external connection.
  • the pad 23 is disposed on an upper surface of the through via 22 and an upper surface 21 A of the core substrate 21 .
  • the pad 23 is connected to the through via 22 and also is electrically connected to the semiconductor apparatus 12 - 1 through a metal wire 16 and the diffusion preventive film 25 .
  • the solder resist 24 is disposed so as to cover the upper surface 21 A of the core substrate 21 .
  • the solder resist 24 has an opening part for exposing an upper surface of the pad 23 .
  • the diffusion preventive film 25 is disposed so as to cover the upper surface of the pad 23 .
  • the diffusion preventive film 25 is connected to the metal wire 16 electrically connected to the semiconductor apparatus 12 - 1 .
  • As the diffusion preventive film 25 for example, an Ni/Au film in which an Ni layer and an Au layer are sequentially provided on the pad 23 can be used.
  • the pad 27 for external connection is disposed on a lower surface of the through via 22 and a lower surface 21 B of the core substrate 21 . Consequently, the pad 27 for external connection is connected to the through via 22 .
  • the solder resist 28 is disposed so as to cover the lower surface 21 B of the core substrate 21 .
  • the solder resist 28 has an opening part for exposing a lower surface of the pad 27 for external connection.
  • the semiconductor apparatus 12 - 1 has a semiconductor chip 31 , an internal connection terminal 32 , a resin layer 33 , a wiring pattern 35 , dummy patterns 36 , a solder resist 37 and a diffusion preventive film 38 .
  • the semiconductor chip 31 has a semiconductor substrate 41 , a semiconductor integrated circuit 42 , an electrode pad 43 and a protective film 44 .
  • the semiconductor substrate 41 is a substrate formed in a plate shape.
  • a silicon substrate can be used as the semiconductor substrate 41 .
  • a thickness of the semiconductor substrate 41 can be set at, for example, 50 ⁇ m to 100 ⁇ m.
  • the semiconductor integrated circuit 42 is disposed on the side of an upper surface 41 A of the semiconductor substrate 41 .
  • the semiconductor integrated circuit 42 is a circuit constructed by a diffusion layer, an insulating film, a via and wiring (not shown).
  • the electrode pad 43 is disposed on the semiconductor integrated circuit 42 .
  • the electrode pad 43 is electrically connected to the diffusion layer, the via and the wiring (all are not shown) disposed in the semiconductor integrated circuit 42 .
  • the protective film 44 is disposed on the semiconductor integrated circuit 42 so as to expose the electrode pad 43 .
  • protective film 44 is a film for protecting the semiconductor integrated circuit 42 .
  • the protective film 44 for example, an SiN film or a PSG film can be used. Also, a polyimide film may be formed on a film such as the SiN film or the PSG film.
  • the internal connection terminal 32 is disposed on the electrode pad 43 .
  • the internal connection terminal 32 is electrically connected to the semiconductor integrated circuit 42 through the electrode pad 43 .
  • An upper surface 32 A of the internal connection terminal 32 is formed in substantially a flat surface and is connected to the wiring pattern 35 .
  • a height of the internal connection terminal 32 can be set at, for example, 10 ⁇ m to 60 ⁇ m.
  • an Au bump or a metal bump constructed of a Ni film formed by an electroless plating method and an Au film with which its Ni film is covered can be used as the internal connection terminal 32 .
  • the Au bump can be formed by, for example, a bonding method or a plating method.
  • Substantially the flat upper surface 32 A of the internal connection terminal 32 can be formed by, for example, pressing the upper ends of the internal connection terminal 32 and the resin layer 33 by a flat plate to which a high pressure is applied after the resin layer 33 is formed so as to cover the internal connection terminal 32 .
  • the resin layer 33 is disposed on the protective film 44 so as to cover the upper surface 32 A of the internal connection terminal 32 .
  • An upper surface 33 A of the resin layer 33 is formed so as to be substantially flush with the upper surface 32 A of the internal connection terminal 32 .
  • a sheet-shaped resin having thermosetting properties for example, an NCF (Non Conductive Film)
  • a pasty resin for example, an NCP (Non Conductive Paste)
  • an anisotropic conductive resin for example, an ACF (Anisotropic Conductive Film)
  • a thickness of the resin layer 33 can be set at, for example, 10 ⁇ m to 60 ⁇ m.
  • 180° C. can be used as a heating temperature in the case of curing the resin layer 33 .
  • the wiring pattern 35 is disposed on the upper surface 32 A of the internal connection terminal 32 and the upper surface 33 A of the resin layer 33 . Consequently, the wiring pattern 35 is electrically connected to the internal connection terminal 32 .
  • the wiring pattern 35 has a connection part 48 and a pad 49 for inspection.
  • the connection part 48 is electrically connected to metal wires 16 , 17 through the diffusion preventive film 38 .
  • the pad 49 for inspection is placed in a position spaced from the connection part 48 .
  • the pad 49 for inspection is a pad for test on which a probe pin disposed in a probe apparatus is abutted in the case of inspecting the semiconductor apparatus 12 - 1 using the probe apparatus (not shown) which is an inspection apparatus for making electrical and functional inspections.
  • the functional inspection refers to an inspection such as an action check of the semiconductor integrated circuit 42 disposed in the semiconductor chip 31 (for example, a check of the presence or absence of a reading error)).
  • the probe pin does not damage the connection part 48 , so that reliability of electrical connection between the wiring pattern 35 and metal wires 16 to 18 can be improved.
  • a Cu film As a material of the wiring pattern 35 constructed above, for example, a Cu film can be used. In the case of using Cu as the material of the wiring pattern 35 , a thickness of the wiring pattern 35 can be set at, for example, 5 ⁇ m to 15 ⁇ m.
  • the dummy pattern 36 is disposed on the upper surface 33 A of the resin layer 33 of the portion in which the wiring pattern 35 is not disposed.
  • the dummy pattern 36 is constructed so as to have the same material as that of the wiring pattern 35 and become substantially the same thickness as that of the wiring pattern 35 .
  • the dummy pattern 36 constructed by the same material as that of the wiring pattern 35 on the resin layer 33 of the portion in which the wiring pattern 35 is not disposed and setting a thickness of the dummy pattern 36 at substantially the same thickness as that of the wiring pattern 35 thus, warpage occurring in the semiconductor apparatus 12 - 1 can be reduced. Consequently, stacking the semiconductor apparatus 12 - 1 to the wiring substrate 11 is facilitated.
  • the solder resist 37 is disposed on the upper surface 33 A of the resin layer 33 so as to cover the dummy pattern 36 and the wiring pattern 35 of the portion excluding the connection part 48 and the pad 49 for inspection.
  • the solder resist 37 has an opening part for exposing an upper surface of the connection part 48 and an opening part for exposing an upper surface of the pad 49 for inspection.
  • the diffusion preventive film 38 is disposed on the connection part 48 and the pad 49 for inspection.
  • the metal wire 16 electrically connected to the pad 23 of the wiring substrate 11 and the metal wire 17 electrically connected to the semiconductor apparatus 12 - 2 are connected to the diffusion preventive film 38 . Consequently, wire bonding connection to the semiconductor apparatus 12 - 2 and the wiring substrate 11 is made in the semiconductor apparatus 12 - 1 .
  • the diffusion preventive film 38 for example, an Ni/Au film in which an Ni layer and an Au layer are sequentially provided on the connection part 48 and the pad 49 for inspection can be used.
  • a thickness of the Ni layer can be set at, for example, 2 ⁇ m to 5 ⁇ m.
  • a thickness of the Au layer can be set at, for example, 1 ⁇ m.
  • the semiconductor apparatus 12 - 1 constructed above is glued on the solder resist 24 of the wiring substrate 11 by a sticky sheet 51 (concretely, for example, a die attach film) stuck on a lower surface 41 B of the semiconductor substrate 41 .
  • the semiconductor apparatus 12 - 1 is a semiconductor apparatus (KGD (Known Good Die)) judged as a good item in electrical and functional inspections made before being glued on the wiring substrate 11 .
  • the semiconductor apparatus 12 - 2 has a configuration similar to that of the semiconductor apparatus 12 - 1 .
  • the semiconductor apparatus 12 - 2 is glued on the solder resist 37 of the semiconductor apparatus 12 - 1 by a sticky sheet 51 stuck on a lower surface of a semiconductor substrate 41 .
  • the semiconductor apparatus 12 - 2 is stepwise placed on the semiconductor apparatus 12 - 1 so as to expose the diffusion preventive film 38 disposed on the connection part 48 of the semiconductor apparatus 12 - 1 .
  • a diffusion preventive film 38 disposed on a connection part 48 of the semiconductor apparatus 12 - 2 is electrically connected to the semiconductor apparatuses 12 - 1 , 12 - 3 through the metal wires 17 , 18 . That is, wire bonding connection between the semiconductor apparatus 12 - 2 and the semiconductor apparatuses 12 - 1 , 12 - 3 is made.
  • the semiconductor apparatus 12 - 2 constructed above is a semiconductor apparatus (KGD (Known Good Die)) judged as a good item in electrical and functional inspections made before being glued on the semiconductor apparatus 12 - 1 .
  • KGD known Good Die
  • the semiconductor apparatus 12 - 3 has a configuration similar to that of the semiconductor apparatus 12 - 1 .
  • the semiconductor apparatus 12 - 3 is glued on a solder resist 37 of the semiconductor apparatus 12 - 2 by a sticky sheet 51 stuck on a lower surface of a semiconductor substrate 41 .
  • the semiconductor apparatus 12 - 3 is stepwise placed on the semiconductor apparatus 12 - 2 so as to expose a diffusion preventive film 38 disposed on a connection part 48 of the semiconductor apparatus 12 - 2 .
  • a diffusion preventive film 38 disposed on a connection part 48 of the semiconductor apparatus 12 - 3 is electrically connected to the semiconductor apparatus 12 - 2 through the metal wire 18 . That is, wire bonding connection between the semiconductor apparatus 12 - 3 and the semiconductor apparatus 12 - 2 is made.
  • the semiconductor apparatus 12 - 3 constructed above is a semiconductor apparatus (KGD (Known Good Die)) judged as a good item in electrical and functional inspections made before being glued on the semiconductor apparatus 12 - 2 .
  • the semiconductor apparatuses 12 - 1 to 12 - 3 are stepwise stacked.
  • the semiconductor chips 31 disposed in the plurality of semiconductor apparatuses 12 - 1 to 12 - 3 previously judged as the good items before the sealing resin 13 is formed since a load by packaging processing of a high pressure or a high temperature, etc. at the time of forming the wiring pattern 35 and the resin layer 33 is applied to the semiconductor chips 31 disposed in the plurality of semiconductor apparatuses 12 - 1 to 12 - 3 previously judged as the good items before the sealing resin 13 is formed, the semiconductor chips 31 disposed in the plurality of semiconductor apparatuses 12 - 1 to 12 - 3 judged as the good items become resistant to breakage, so that a yield of the electronic apparatus 10 can be improved.
  • the sealing resin 13 is disposed on the wiring substrate 11 so as to seal the metal wires 16 to 18 and the semiconductor apparatuses 12 - 1 to 12 - 3 stacked.
  • a molding resin for example, an epoxy resin
  • thermosetting properties can be used.
  • the external connection terminal 14 is arranged on the pad 27 for external connection of the wiring substrate 11 .
  • the external connection terminal 14 is a terminal electrically connected to a mounting substrate (not shown) such as a motherboard.
  • a solder bump can be used as the external connection terminal 14 .
  • the electronic apparatus of the embodiment by stepwise stacking the semiconductor apparatuses 12 - 1 to 12 - 3 (KGD (Known Good Die)) previously judged as the good items on the wiring substrate 11 while having the resin layers 33 which are disposed on surfaces of the semiconductor chips 31 in which the electrode pads 43 are formed and expose the internal connection terminals 32 placed on the electrode pads 43 and the wiring patterns 35 which are disposed on the resin layers 33 and are connected to the internal connection terminals 32 , a yield of the electronic apparatus 10 can be improved.
  • KGD known Good Die
  • the semiconductor chips 31 disposed in the plurality of semiconductor apparatuses 12 - 1 to 12 - 3 previously judged as the good items before the sealing resin 13 is formed since a load by packaging processing of a high pressure or a high temperature, etc. at the time of forming the wiring pattern 35 and the resin layer 33 is applied to the semiconductor chips 31 disposed in the plurality of semiconductor apparatuses 12 - 1 to 12 - 3 previously judged as the good items before the sealing resin 13 is formed, the semiconductor chips 31 disposed in the plurality of semiconductor apparatuses 12 - 1 to 12 - 3 previously judged as the good items become resistant to breakage by influence of a pressure or a temperature, etc. at the time of forming the sealing resin 13 , so that a yield of the electronic apparatus 10 can be improved.
  • FIGS. 9 to 24 are diagrams showing manufacturing steps of the electronic apparatus according to the embodiment of the invention.
  • the same numerals are assigned to the same components as those of the electronic apparatus 10 of the embodiment.
  • B shows a position (hereinafter called a “cut position B”) in which a dicer or a slicer cuts a semiconductor substrate 61 .
  • the semiconductor substrate 61 having a plurality of semiconductor apparatus formation regions A is prepared, and a semiconductor chip 31 having a semiconductor integrated circuit 42 , an electrode pad 43 and a protective film 44 is formed on the side of an upper surface 61 A of the semiconductor substrate 61 corresponding to the semiconductor apparatus formation region A by a well-known technique.
  • the semiconductor apparatus formation region A is a region in which a semiconductor apparatus 12 is formed.
  • the semiconductor apparatus 12 is a semiconductor apparatus having a configuration similar to that of the semiconductor apparatuses 12 - 1 to 12 - 3 (see FIG. 8 ) described above.
  • the semiconductor substrate 61 results in the semiconductor substrate 41 (see FIG. 8 ) described above by being formed in a thin plate and being cut in the cut positions B in steps described below.
  • the semiconductor substrate 61 for example, a silicon wafer can be used.
  • a thickness of the semiconductor substrate 61 can be set at, for example, 500 ⁇ m to 775 ⁇ m.
  • a material of the electrode pad 43 for example, Al can be used.
  • the protective film 44 for example, an SiN film or a PSG film can be used.
  • one internal connection terminal 32 is respectively formed on all the electrode pads 43 .
  • the internal connection terminal 32 for example, an Au bump or a metal bump constructed of a Ni film formed by an electroless plating method and an Au film with which its Ni film is covered can be used.
  • the Au bump can be formed by, for example, a bonding method.
  • variations in height may be present in the plurality of internal connection terminals 32 formed in the step shown in FIG. 10 .
  • a resin layer 33 is formed so as to cover the internal connection terminals 32 and the plurality of semiconductor chips 31 (the upper surface side of the plurality of semiconductor chips 31 ) of the side on which the internal connection terminals 32 are disposed.
  • a sheet-shaped resin having thermosetting properties and sticky properties for example, an NCF (Non Conductive Film)
  • a pasty resin having thermosetting properties for example, an NCP (Non Conductive Paste)
  • an anisotropic conductive resin for example, an ACF (Anisotropic Conductive Film)
  • the resin layer 33 is formed by sticking the sheet-shaped resin on the upper surface side of a structural body shown in FIG. 10 .
  • a pasty resin is formed on the upper surface side of the structural body shown in FIG. 10 by a printing method etc. and thereafter is pre-baked and the resin is partially cured. This partially cured resin has adhesive properties.
  • a thickness of the resin layer 33 can be set at, for example, 20 ⁇ m to 100 ⁇ m.
  • a metal layer 63 is formed on an upper surface 33 A of the resin layer 33 .
  • the metal layer 63 is etched and results in a wiring pattern 35 and a dummy pattern 36 in a step shown in FIG. 14 described below.
  • the metal layer 63 is formed on the upper surface 33 A of the resin layer 33 by preparing Cu foil as the metal layer 63 and sticking this Cu foil on the upper surface 33 A of the resin layer 33 .
  • a thickness of the metal layer 63 can be set at, for example, 5 ⁇ m to 15 ⁇ m.
  • a heating temperature is, for example, 180° C.
  • a flat plate (not shown) is placed on the metal layer 63 and the metal layer 63 is pressed from the side of an upper surface 63 A of the metal layer 63 through the flat plate (a pressure is, for example, 1.5 MPa to 3.0 MPa) and a lower surface 63 B of the metal layer 63 is brought into contact with upper surfaces 32 A of the plurality of internal connection terminals 32 and the metal layer 63 is crimped on the internal connection terminals 32 .
  • the resin layer 33 cures by heating the structural body shown in FIG. 12 .
  • a thickness of the resin layer 33 after crimping can be set at, for example, 10 ⁇ m to 60 ⁇ m.
  • the metal layer 63 is patterned by etching and wiring patterns 35 and dummy patterns 36 are simultaneously formed and thereafter, roughening treatment of the wiring patterns 35 and the dummy patterns 36 is performed.
  • a resist film patterned is formed on the metal layer 63 and then using this resist film as a mask, the metal layer 63 is etched and the wiring patterns 35 and the dummy patterns 36 are formed.
  • the manufacturing steps can be simplified as compared with the case of separately forming the wiring patterns 35 and the dummy patterns 36 .
  • the roughening treatment of the wiring patterns 35 and the dummy patterns 36 can be performed by any method of blackening treatment or roughening etching treatment.
  • the roughening treatment is treatment for improving adhesion between the wiring patterns 35 and the dummy patterns 36 and a solder resist 37 formed on side surfaces and upper surfaces of the wiring patterns 35 and the dummy patterns 36 .
  • the solder resist 37 is disposed on the upper surface 33 A of the resin layer 33 so as to cover the dummy patterns 36 and the wiring patterns 35 of the portion excluding connection parts 48 and pads 49 for inspection and thereafter, a diffusion preventive film 38 is formed on the connection parts 48 and the pads 49 for inspection.
  • the diffusion preventive film 38 can be formed by, for example, a plating method.
  • As the diffusion preventive film 38 for example, an Ni/Au film in which an Ni layer and an Au layer are sequentially provided on the connection parts 48 and the pads 49 for inspection can be used.
  • a thickness of the Ni layer can be set at, for example, 2 ⁇ m to 5 ⁇ m.
  • a thickness of the Au layer can be set at, for example, 1 ⁇ m.
  • the semiconductor substrate 61 is polished or ground from the side of a lower surface 61 B of the semiconductor substrate 61 and the semiconductor substrate 61 is formed in a thin plate.
  • a back side grinder can be used in the thin plate formation of the semiconductor substrate 61 .
  • a thickness of the semiconductor substrate 61 after the thin plate formation can be set at, for example, 50 ⁇ m to 100 ⁇ m.
  • the semiconductor substrate 61 formed in the thin plate is cut along the cut positions B. Consequently, a plurality of semiconductor apparatuses 12 are manufactured (the steps shown in FIGS. 9 to 17 correspond to a semiconductor apparatus formation step).
  • the plurality of semiconductor apparatuses 12 are semiconductor apparatuses having configurations similar to those of the semiconductor apparatuses 12 - 1 to 12 - 3 described above and also are the semiconductor apparatuses before electrical and functional inspections are made. In addition, the electrical and functional inspections of the semiconductor apparatuses 12 may be made before the semiconductor apparatuses 12 are individualized.
  • a probe pin is brought into contact with the diffusion preventive film 38 disposed on the pad 49 for inspection of the semiconductor apparatus 12 shown in FIG. 17 and the electrical and functional inspections of the plurality of semiconductor apparatuses 12 and the semiconductor apparatuses 12 - 1 to 12 - 3 (KGD (Known Good Die)) judged as good items are acquired (a good item semiconductor apparatus acquisition step).
  • KGD known Good Die
  • sticky tapes 51 are stuck on lower surfaces 41 B of semiconductor substrates 41 disposed in the semiconductor apparatuses 12 - 1 to 12 - 3 judged as the good items in the step shown in FIG. 18 .
  • the sticky tape 51 for example, a die attach film can be used.
  • the sticky tape 51 may be stuck on the lower surface 41 B of the semiconductor substrate 41 disposed in the semiconductor apparatus 12 before individualization. In this case, the sticky tape 51 is cut together with the semiconductor substrate 61 formed in the thin plate.
  • a wiring substrate 11 is formed by a well-known technique.
  • the semiconductor apparatuses 12 - 1 to 12 - 3 judged as the good items are sequentially stacked stepwise on the wiring substrate 11 shown in FIG. 20 (a semiconductor apparatus stacking step).
  • the semiconductor apparatus 12 - 2 stepwise stacked on the semiconductor apparatus 12 - 1 is placed so as to expose the diffusion preventive film 38 disposed on the connection part 48 of the semiconductor apparatus 12 - 1
  • the semiconductor apparatus 12 - 3 stepwise stacked on the semiconductor apparatus 12 - 2 is placed so as to expose the diffusion preventive film 38 disposed on the connection part 48 of the semiconductor apparatus 12 - 2 .
  • electrical connection (wire bonding connection) between the wiring substrate 11 shown in FIG. 21 and the semiconductor apparatuses 12 - 1 to 12 - 3 judged as the good items are made by metal wires 16 to 18 (an electrical connection step).
  • a sealing resin 13 for sealing the metal wires 16 to 18 and the semiconductor apparatuses 12 - 1 to 12 - 3 judged as the good items shown in FIG. 22 is formed (a sealing resin formation step).
  • a sealing resin 13 for example, a molding resin (for example, an epoxy resin) having thermosetting properties can be used.
  • the molding resin to which a pressure (for example, 5 MPa to 10 MPa) is applied is introduced into the metal mold and thereafter the molding resin is heated (a heating temperature is, for example, 180° C.) and cured and thereby, the sealing resin 13 is formed. Since the high heat and the high pressure have already been applied to the semiconductor apparatuses 12 - 1 to 12 - 3 judged as the good items in the step shown in FIG. 13 described above, the semiconductor chips 31 disposed in the semiconductor apparatuses 12 - 1 to 12 - 3 judged as the good items are not broken in a packaging processing process including the subsequent sealing resin formation step.
  • a pressure for example, 5 MPa to 10 MPa
  • external connection terminals 14 are formed on pads 27 for external connection of a structural body shown in FIG. 23 . Consequently, an electronic apparatus 10 of the embodiment is manufactured.
  • the external connection terminal 14 for example, a solder bump can be used.
  • the manufacturing method of the electronic apparatus of the embodiment electrical and functional inspections of the plurality of semiconductor apparatuses 12 having the resin layers 33 which are disposed on surfaces of the semiconductor chips 31 in which the electrode pads 43 are formed and expose the internal connection terminals 32 and the wiring patterns 35 which are disposed on the resin layers 33 and are connected to the internal connection terminals 32 are made and the plurality of semiconductor apparatuses 12 - 1 to 12 - 3 (KGD (Known Good Die)) judged as good items are acquired and the semiconductor apparatuses 12 - 1 to 12 - 3 previously judged as the good items are stacked on the wiring substrate 11 and then electrical connection between the wiring substrate 11 and the stacked semiconductor apparatuses 12 - 1 to 12 - 3 are made and thereafter the semiconductor apparatuses 12 - 1 to 12 - 3 are sealed with the sealing resin 13 and thereby, a yield of the electronic apparatus 10 can be improved.
  • KGD known Good Die
  • the semiconductor chips 31 disposed in the plurality of semiconductor apparatuses 12 - 1 to 12 - 3 previously judged as the good items before the sealing resin 13 is formed since a high pressure or a high temperature, etc. at the time of forming the wiring pattern 35 and the resin layer 33 is applied to the semiconductor chips 31 disposed in the plurality of semiconductor apparatuses 12 - 1 to 12 - 3 previously judged as the good items before the sealing resin 13 is formed, the semiconductor chips 31 disposed in the plurality of semiconductor apparatuses 12 - 1 to 12 - 3 previously judged as the good items become resistant to breakage by influence of a pressure or a temperature, etc. at the time of forming the sealing resin 13 , so that a yield of the electronic apparatus 10 can be improved.
  • the case of stacking three semiconductor apparatuses (semiconductor apparatuses 12 - 1 to 12 - 3 ) on the wiring substrate 11 has been described by way of example, but the number of semiconductor apparatuses stacked on the wiring substrate 11 may be two or three or more.
  • the manufacturing method of the semiconductor apparatuses 12 - 1 to 12 - 3 disposed in the electronic apparatus 10 is not limited to the steps shown in FIGS. 9 to 17 .
  • the invention can be applied to an electronic apparatus comprising a plurality of semiconductor chips (KGD (Known Good Die)) stacked on a wiring substrate and a sealing resin with which the plurality of semiconductor chips (KGD (Known Good Die)) are sealed, and a manufacturing method of the electronic apparatus.
  • KGD known Good Die
US12/238,699 2007-09-27 2008-09-26 Electronic apparatus and manufacturing method thereof Abandoned US20090085222A1 (en)

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US7875499B2 (en) 2011-01-25
EP2043152A3 (de) 2010-03-17
TW200915533A (en) 2009-04-01
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EP2043152A2 (de) 2009-04-01
JP2009081355A (ja) 2009-04-16
US20100022035A1 (en) 2010-01-28
JP4317245B2 (ja) 2009-08-19

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