US20080237787A1 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
- Publication number
- US20080237787A1 US20080237787A1 US11/836,609 US83660907A US2008237787A1 US 20080237787 A1 US20080237787 A1 US 20080237787A1 US 83660907 A US83660907 A US 83660907A US 2008237787 A1 US2008237787 A1 US 2008237787A1
- Authority
- US
- United States
- Prior art keywords
- wiring
- fuse
- layer
- electrode pad
- fuse wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention is an invention concerning a semiconductor integrated circuit, and especially relates to the semiconductor integrated circuit provided with a fuse.
- the fuse By forming a fuse in a semiconductor integrated circuit, the fuse was cut, the value of resistance was adjusted and relief processing, such as transposing a defective element to a normal element, was performed. And generally the laser fuse cut by the laser beam irradiation from the outside was used as a fuse conventionally used for relief processing.
- the electric fuse which sends current and is cut and which is relievable even if it is on site or after molding, naturally on wafer is used for the semiconductor integrated circuit. Since it cut by doing laser irradiation from the outside, the trimming dedicated device and the relief processing step were required of the laser fuse. However, since it can trim immediately after a test using a circuit tester with an electric fuse, it is newly unnecessary in trimming equipment or a relief processing step. This electric fuse is described to Patent Reference 1 or Patent Reference 2.
- Patent Reference 1 Japanese Unexamined Patent Publication No. 2005-39220
- Patent Reference 2 Japanese Unexamined Patent Publication No. 2005-57186
- the present invention aims at offering the semiconductor integrated circuit which can perform reliable relief processing using an electric fuse.
- the solving means concerning the present invention comprises a fuse wiring cut by passing beyond a predetermined current value, a first electrode pad connected to one side of the fuse wiring, a second electrode pad connected to the other of the fuse wiring, a pollution-control layer formed in an upper layer and a lower layer of the fuse wiring via an insulating layer, a first via hole wiring of a pair which is formed via the insulating layer to a side surface of the fuse wiring, connects with the pollution-control layer, and surrounds the fuse wiring, and a second via hole wiring of a pair formed in an outside of the first via hole wiring to the fuse wiring so that the first via hole wiring may be surrounded.
- a semiconductor integrated circuit described in the present invention is provided with the first via hole wiring of the pair which connects with a pollution-control layer and surrounds a fuse wiring, and the second via hole wiring of a pair formed so that a first via hole wiring may be surrounded.
- an electric fuse When an electric fuse is cut, it prevents the wiring material of a cut section dispersing and polluting a periphery, and has the effect of improving the reliability of a semiconductor integrated circuit.
- the up-and-down layer concerned can be wired and reduction of chip size is attained.
- FIG. 1 is a block diagram explaining the usage use of the electric fuse used for a semiconductor integrated circuit
- FIG. 2 is a perspective view of the electric fuse concerning Embodiment 1 of the present invention.
- FIG. 3 is a cross-sectional view of the semiconductor integrated circuit concerning Embodiment 1 of the present invention.
- FIG. 4 is the SEM photography of the electric fuse concerning Embodiment 1 of the present invention.
- FIG. 5 is the SEM photography in which a plurality of electric fuses concerning Embodiment 1 of the present invention are arranged;
- FIG. 6 is the SEM photography of the electric fuse concerning Embodiment 2 of the present invention.
- FIG. 7 is the section SEM photography of the electric fuse concerning Embodiment 2 of the present invention.
- FIG. 8 is a plan view of the electric fuse concerning Embodiment 2 of the present invention.
- FIGS. 9 and 10 are cross-sectional views of the electric fuse concerning Embodiment 2 of the present invention.
- FIGS. 11 and 12 are drawings explaining the relation of the crack expansion prevention layer of an electric fuse and crack concerning Embodiment 2 of the present invention.
- FIGS. 13 to 15 are drawings explaining the distance of the pollution-control layer of an electric fuse and fuse wiring concerning Embodiment 2 of the present invention.
- FIGS. 16 to 18 are drawings showing the fuse current before and after the cutting processing of the electric fuse concerning Embodiment 2 of the present invention.
- FIGS. 19 and 20 are cross-sectional views of the electric fuse concerning Embodiment 3 of the present invention.
- FIG. 1 is the drawing which expressed the processing after wafer test (WT) 101 schematically.
- a test and relief processing can be completed at one step by performing electric fuse trimming 102 after wafer test (WT) 101 .
- WT wafer test
- it is necessary to perform laser trimming 103 of a separated process after wafer test (WT) 101 and, in the case of the semiconductor integrated circuit using a laser fuse, two steps are needed for performing test and relief processing. Therefore, one step can be skipped by using an electric fuse for a semiconductor integrated circuit. That is, by combining an electric fuse and BIST (built in self-test), it becomes possible to build a self repair test, and the cost of a test can be reduced.
- BIST built in self-test
- FT final test
- the wiring blowout type electricity fuse is used in the semiconductor integrated circuit concerning this embodiment.
- polysilicon was used for this electric fuse as a fuse wiring material until now. Since the frequency in use of metal wiring will increase from now on, Cu, Al, Ti, Ta, etc. come to be used as a fuse wiring material. So, this embodiment explains the electric fuse which used Cu as a fuse wiring material. Even if it uses fuse wiring materials other than Cu, an effect equivalent to the effect described below can be acquired.
- FIG. 2 The perspective view of the electric fuse related to this embodiment at FIG. 2 is shown, and the cross-sectional view of the semiconductor integrated circuit which includes the electric fuse related at this embodiment at FIG. 3 is shown.
- electrode pad 2 for feeding power is connected to one side of fuse wiring 1
- electrode pad 3 for GND supply is connected to the other.
- a plurality of plugs 4 for feeding power are formed in electrode pad 2 for feeding power.
- a plurality of plugs 5 for GND supply are formed in electrode pad 3 for GND supply.
- Fuse length is the length of fuse wiring 1 from electrode pad 2 for feeding power to electrode pad 3 for GND supply.
- fuse wirings 1 which can be stably cut with the minimum cutting current differ according to fuse width, fuse thickness, material, etc.
- fuse width was set as 0.12 ⁇ m
- fuse thickness was set as 250 nm
- material was set as Cu.
- the number of plugs 4 for feeding power and the number of plugs 5 for GND supply are made into the same number.
- Each cross section of plug 4 for feeding power and plug 5 for GND supply is the same.
- the number of plugs 4 for feeding power and the number of plugs 5 for GND supply are not necessarily restricted to the same number.
- the total of a contact cross section with electrode pad 2 for feeding power of a plurality of plugs 4 for feeding power is the same as the total of a contact cross section with electrode pad 3 for GND supply of a plurality of plugs 5 for GND supply, it is good.
- the electric fuse concerning this embodiment is formed in a fine layer in the semiconductor integrated circuit with which a global layer is about 1000 nm, a semi global layer is about 350 nm, and a fine layer is about 200 nm.
- the fine layer is about 200 nm, generally the layer about 300 nm—about 100 nm is called fine layer.
- FIG. 3 With the cross-sectional view shown in FIG. 3 , the fine layer from M 1 layer to M 5 layer is illustrated.
- fuse wiring 1 may be formed in any M 1 layer to M 5 layer shown in FIG. 3 , it is formed in M 3 layer by this embodiment.
- the wiring layer from M 1 layer to M 5 layer is formed via TEOS layer 7 on Si substrate 6 . And it separates by a SiCN layer between each wiring layer, and separates by SiOC between each wiring in the same wiring layer.
- FIG. 3 the enlarged view of fuse wiring 1 corresponding to the A-A′ surface of FIG. 2 is illustrated. With this enlarged view, barrier metal layer 8 is formed between fuse wiring 1 of Cu, and SiOC of an insulating film. This barrier metal layer 8 is formed by Ta or TaN.
- fuse wiring 1 In order to cut fuse wiring 1 , it is necessary to change the material of fuse wiring 1 from a solid to a liquid. That is, it is necessary to send current through fuse wiring 1 and to raise the temperature of fuse wiring 1 self at the lowest to the melting point (for a melting point to be about 1100° C., when material is Cu) of the material concerned.
- FIG. 4 A state that fuse wiring 1 of middle was cut and the deposit part of the wiring material has spread near the concerned cut section is shown by FIG. 4 .
- the deposit part generated at the time of cutting of this fuse wiring 1 occurs near electrode pad 2 for feeding power, or the electrode pad 3 for GND supply, there is concern which produces the bad influence of short-circuiting with other adjoining wirings. Therefore, in the electric fuse concerning this embodiment, the number of plug 4 for feeding power connected to electrode pad 2 for feeding power and the number of plug 5 for GND supply connected to electrode pad 3 for GND supply were made into the same number, and the cut section is controlled to occur in the central part of fuse wiring 1 .
- the simulation of the heat generated in fuse wiring 1 is done by the case where the number of plug 4 for feeding power and the number of plug 5 for GND supply are made into the same number, and the case where it is made a different number.
- the portion which reaches beyond a melting point becomes short within fuse wiring 1 .
- the portion more than melting point temperature concentrates on the central part of fuse wiring 1 .
- a plurality of electric fuses are formed.
- the present invention may be structure which is not restricted to this but is located in a line with a longitudinal direction.
- Several of the electric fuse shown in FIG. 5 are cut in the central part of the fuse wiring.
- FIG. 6 The SEM photography for a cut section of fuse wiring 1 is shown in FIG. 6
- FIG. 7 the section SEM photography for a cut section of fuse wiring 1 is shown in it at FIG. 7 .
- FIG. 6 and FIG. 7 show a state that Cu component of the cut section of fuse wiring 1 which became high temperature has deposited as a Cu crack to the upper oxide film when fuse wiring 1 is cut in high electric current.
- FIB Fluorine Beam
- Cu crack shown in FIG. 6 and FIG. 7 extends by stress application of temperature, bias, etc., and there is a possibility of having a bad influence on the reliability of a semiconductor integrated circuit.
- Cu which dispersed on the outskirts at the time of cutting of fuse wiring 1 may be diffused around a fuse, may cause metallic contamination, and may cause the malfunction of a nearby transistor etc.
- crack expansion prevention layer 10 shown in FIG. 8 through FIG. 10 as crack expansion preventive measures is formed.
- This crack expansion prevention layer 10 arranges many wirings about width 0.10 ⁇ m in parallel to the short side of fuse wiring 1 as crack progress prevention layer 10 in the up-and-down layer (at the layer structure shown in FIG. 3 , they are M 2 layer and M 4 layer) of fuse wiring 1 , as shown in FIG. 9 or FIG. 10 . That is, crack expansion prevention layer 10 forms the discontinuous layer to the wiring direction of fuse wiring 1 . Since this crack expansion prevention layer 10 is formed in a wiring layer, it is formed with wiring materials, such as Cu.
- FIG. 8 shows the plan view of the electric fuse concerning this embodiment.
- the cross-sectional view in a B-B′ surface of the electric fuse shown in FIG. 8 is FIG. 9
- the cross-sectional view in a C-C′ surface of the electric fuse shown in FIG. 8 is FIG. 10 .
- the description of M 1 -M 5 shown in right-hand side at FIG. 9 and FIG. 10 corresponds with the layer structure shown in FIG. 3 .
- pollution-control layer 11 and via hole wirings 12 and 13 shown in FIG. 8 through FIG. 10 are formed as measures against metallic contamination by Cu scattering of fuse wiring 1 .
- This pollution-control layer 11 is formed in the further upper layer (at the layer structure shown in FIG. 3 , it is M 5 layer), and a further lower layer of crack expansion prevention layer 10 (at the layer structure shown in FIG. 3 , it is M 1 layer) platy, as shown in FIG. 9 or FIG. 10 .
- via hole wiring 12 is formed so that an M 5 layer pollution-control layer 11 and M 1 layer pollution-control layer 11 may be connected and fuse wiring 1 may be surrounded.
- via hole wiring 13 is formed in the outside of via hole wiring 12 to fuse wiring 1 . It means that this had formed the double pollution-control layer to the horizontal direction of fuse wiring 1 with the electric fuse concerning this embodiment.
- Via hole wirings 12 and 13 are wirings which connect the wiring layer from M 5 layer to M 1 layer, and are formed with wiring materials, such as Cu.
- one end of via hole wiring 12 approaches electrode pad 2 for feeding power, and the other end of via hole wiring 13 is close to electrode pad 3 for GND supply.
- the one end of via hole wiring 12 approaches electrode pad 2 for feeding power means the state where they are approaching to the degree which can prevent dispersed Cu, although an insulating film exists between via hole wiring 12 and electrode pad 2 for feeding power. It is also the same that the other end of via hole wiring 13 approaches electrode pad 3 for GND supply.
- via hole wiring 12 and via hole wiring 13 presupposed that alternate structure like FIG. 8 is taken.
- the present invention may not be restricted to this but may be an alternate structure (a part of via hole wiring 13 touches electrode pad 2 for feeding power physically via an insulating film, and a part of via hole wiring 12 touches electrode pad 3 for GND supply physically via an insulating film) contrary to FIG. 8 .
- via hole wiring 12 and via hole wiring 13 do not necessarily need to become alternate structure.
- Electrode pad 2 for feeding power and electrode pad 3 for GND supply may be close to the ends of via hole wirings 12 and 13 , and do not need to be close.
- crack expansion prevention layer 10 has a structure discontinuous to the wiring direction of fuse wiring 1 , as shown in FIG. 8 or FIG. 10 . This is for setting it as the structure where the relief rate lowering by short-circuit with crack expansion prevention layer 10 is avoided, and crack expansion can be prevented at the time of cutting of fuse wiring 1 .
- the case of the structure where crack expansion prevention layer 10 is following the wiring direction of fuse wiring 1 at FIG. 11 is shown. Since crack expansion prevention layer 10 is following the wiring direction in FIG. 11 when crack 14 generated into the portion from which fuse wiring 1 was cut touches crack expansion prevention layer 10 , fuse wiring 1 which must have been cut will conduct via crack 14 and crack expansion prevention layer 10 . Therefore, when crack expansion prevention layer 10 is following the wiring direction of fuse wiring 1 , the relief rate of an electric fuse will fall.
- FIG. 12 the case of structure with crack expansion prevention layer 10 discontinuous to the wiring direction of fuse wiring 1 is shown in FIG. 12 like this embodiment.
- FIG. 12 even if crack 14 generated into the portion from which fuse wiring 1 was cut touches crack expansion prevention layer 10 , since crack expansion prevention layer 10 is discontinuous to a wiring direction, it does not conduct via crack 14 and crack expansion prevention layer 10 . Therefore, in the case of discontinuous crack expansion prevention layer 10 shown in FIG. 12 , crack expansion can be prevented, without the relief rate of an electric fuse falling.
- the electric fuse concerning this embodiment is shown in FIG. 8 and FIG. 10 , at least 400 nm or more (in the case of a fine layer, they are two or more layers) of distance of crack expansion prevention layer 10 , pollution-control layer 11 and via hole wiring 12 , and fuse wiring 1 is opened.
- the electric fuse concerning this embodiment can avoid decline in a relief rate.
- FIG. 13 shows the cross-sectional view of the electric fuse when pollution-control layer 11 is formed in M 4 layer and distance with fuse wiring 1 in M 3 layer is set to 200 nm.
- FIG. 14 shows the cross-sectional view of the electric fuse when pollution-control layer 11 is formed in M 2 layer and distance with fuse wiring 1 in M 3 layer is set to 200 nm.
- FIG. 15 shows the cross-sectional view of the electric fuse when pollution-control layer 11 is formed in M 1 and M 5 layers and distance with fuse wiring 1 in M 3 layer is set to 400 nm.
- FIG. 16 through FIG. 18 the result of having measured the fuse current before and after cutting processing (processing which applies the current beyond a predetermined current value for cutting) to the electric fuse of the structure shown in FIG. 13 through FIG. 15 is shown in FIG. 16 through FIG. 18 , respectively.
- the result shown in FIG. 16 is the result of using the electric fuse of the structure shown in FIG. 13 .
- fuse current about 0.02A is flowing before the cutting processing of an electric fuse in the result of FIG. 16
- almost all fuse current is about 1.0E-07A or about 1.0E-08A after the cutting processing of an electric fuse.
- the result of FIG. 16 means that the relief rate in an electric fuse falls, when the distance of pollution-control layer 11 in M 4 layer and fuse wiring 1 is 200 nm.
- the result shown in FIG. 17 is the result of using the electric fuse of the structure shown in FIG. 14 .
- fuse current about 0.02A is flowing before the cutting processing of an electric fuse.
- fuse current is about 1.0E-07A, poor cutting which flows in more than 1.0E-03A is included. That is, the result shown in FIG. 17 means that the relief rate in an electric fuse falls, when the distance of pollution-control layer 11 in M 2 layer and fuse wiring 1 is 200 nm.
- the result shown in FIG. 18 is the result of using the electric fuse of the structure shown in FIG. 15 .
- fuse current about 0.02A is flowing before the cutting processing of an electric fuse.
- Almost all fuse current is stable about 1.0E-08A after the cutting processing of an electric fuse. That is, the result shown in FIG. 18 means that the relief rate in an electric fuse does not fall, when the distance of pollution-control layer 11 in M 1 , M 5 layers and fuse wiring 1 is 400 nm.
- one layer is about 200 nm when forming the wiring layer shown in FIG. 15 etc. in a fine layer, it is necessary to detach at least two or more layers, and to form crack expansion prevention layer 10 or pollution-control layer 11 from fuse wiring 1 .
- the present invention is not restricted to this, but as long as the pollution control by scattering of a wiring material can be disregarded, it may form only crack expansion prevention layer 10 . In the present invention, as long as crack expansion can be disregarded, only pollution-control layer 11 , and via hole wirings 12 and 13 may be formed.
- pollution-control layer 11 is provided as measures against metallic contamination by Cu scattering of fuse wiring 1 .
- This pollution-control layer 11 is formed in the further upper layer of crack expansion prevention layer 10 (at the layer structure shown in FIG. 3 , it is M 5 layer), and a further lower layer (at the layer structure shown in FIG. 3 , it is M 1 layer) platy via member 20 .
- fuse wiring 1 is shown in FIG. 16 through FIG. 18 , in order to obtain the characteristics of an electric fuse in the case of the structure shown in FIG. 10 , it was a premise that at least one of member 20 between fuse wiring 1 and crack expansion prevention layer 10 and members 20 between crack expansion prevention layer 10 and pollution-control layer 11 is insulated.
- As a method of securing insulation of member 20 when using an insulating material for the material of member 20 itself, it may not be restricted, but the structure of forming an insulating film between member 20 and pollution-control layer 11 etc. may be used.
- cut section 21 is formed in pollution-control layer 11 between members 20 .
- pollution-control layer 11 between members 20 it is pollution-control layer 11 located by left-hand side member 20 from member 20 of the right-hand side in a drawing, and pollution-control layer 11 of the position corresponding to fuse wiring 1 which functions as an electric fuse is said.
- Cut section 21 shown in FIG. 19 is not restricted when cut physically, but it should just electrically be cut. At this embodiment, there is no need of giving insulation to member 20 by forming cut section 21 in pollution-control layer 11 . It becomes possible to form member 20 in the same process as via hole wirings 12 and 13 shown in FIG. 9 . Therefore, the electric fuse concerning this embodiment simplifies a process, and has the characteristic effect of reducing cost.
- Cut section 21 shown in FIG. 19 was structure which two right and left form to each of pollution-control layer 11 of the upper layer and a lower layer.
- the present invention is not restricted to this, but as shown in FIG. 20 , it should just form one cut section 21 in each pollution-control layer 11 .
- one cut section 21 is formed at a time in the upper layer and lower layer pollution-control layer 11 of the right-hand side in a drawing. In pollution-control layer 11 of the upper layer and a lower layer, at the same position or at the same side, it is not necessary to form cut section 21 .
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/592,949 US8723291B2 (en) | 2006-08-11 | 2012-08-23 | Semiconductor integrated circuit |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006-219370 | 2006-08-11 | ||
JP2006219370 | 2006-08-11 | ||
JP2007030263A JP5132162B2 (ja) | 2006-08-11 | 2007-02-09 | 半導体集積回路 |
JP2007-30263 | 2007-02-09 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/592,949 Continuation US8723291B2 (en) | 2006-08-11 | 2012-08-23 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080237787A1 true US20080237787A1 (en) | 2008-10-02 |
Family
ID=39289087
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/836,609 Abandoned US20080237787A1 (en) | 2006-08-11 | 2007-08-09 | Semiconductor integrated circuit |
US13/592,949 Active US8723291B2 (en) | 2006-08-11 | 2012-08-23 | Semiconductor integrated circuit |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/592,949 Active US8723291B2 (en) | 2006-08-11 | 2012-08-23 | Semiconductor integrated circuit |
Country Status (5)
Country | Link |
---|---|
US (2) | US20080237787A1 (de) |
JP (1) | JP5132162B2 (de) |
KR (1) | KR101360709B1 (de) |
CN (1) | CN101241900B (de) |
TW (1) | TWI418014B (de) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100207239A1 (en) * | 2009-02-18 | 2010-08-19 | Nec Electronics Corporation | Semiconductor device and manufacturing method thereof |
US20140145194A1 (en) * | 2011-09-13 | 2014-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device Components and Methods |
US9679858B2 (en) | 2015-08-26 | 2017-06-13 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing same |
US11026325B2 (en) * | 2017-05-25 | 2021-06-01 | Orpyx Medical Technologies Inc. | Flexible circuit package |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100904827B1 (ko) * | 2007-05-02 | 2009-06-25 | 동부일렉트로닉스 주식회사 | 퓨즈 테스트 장치 |
US7956466B2 (en) * | 2008-05-09 | 2011-06-07 | International Business Machines Corporation | Structure for interconnect structure containing various capping materials for electrical fuse and other related applications |
US8772156B2 (en) * | 2008-05-09 | 2014-07-08 | International Business Machines Corporation | Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications |
JP5632766B2 (ja) * | 2011-02-07 | 2014-11-26 | ローム株式会社 | 半導体装置 |
KR102096614B1 (ko) * | 2013-10-11 | 2020-04-03 | 삼성전자주식회사 | 반도체 장치의 이-퓨즈 구조체 |
JP7425566B2 (ja) * | 2019-09-09 | 2024-01-31 | 日清紡マイクロデバイス株式会社 | 半導体装置およびそのトリミング方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5780918A (en) * | 1990-05-22 | 1998-07-14 | Seiko Epson Corporation | Semiconductor integrated circuit device having a programmable adjusting element in the form of a fuse mounted on a margin of the device and a method of manufacturing the same |
US6222244B1 (en) * | 1998-06-08 | 2001-04-24 | International Business Machines Corporation | Electrically blowable fuse with reduced cross-sectional area |
US6295721B1 (en) * | 1999-12-28 | 2001-10-02 | Taiwan Semiconductor Manufacturing Company | Metal fuse in copper dual damascene |
US20020017704A1 (en) * | 2000-08-01 | 2002-02-14 | Takashi Yajima | Semiconductor device and method of manufacture |
US6486526B1 (en) * | 1999-01-04 | 2002-11-26 | International Business Machines Corporation | Crack stop between neighboring fuses for protection from fuse blow damage |
US6566238B2 (en) * | 1999-02-26 | 2003-05-20 | Infineon Technologies Ag | Metal wire fuse structure with cavity |
US20040262710A1 (en) * | 2003-06-26 | 2004-12-30 | Nec Electronics Corporation | Semiconductor device |
US20050029620A1 (en) * | 2003-08-07 | 2005-02-10 | Nec Electronics Corporation | Semiconductor device |
US6872648B2 (en) * | 2002-09-19 | 2005-03-29 | Infineon Technologies Ag | Reduced splattering of unpassivated laser fuses |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5863147A (ja) * | 1981-10-09 | 1983-04-14 | Toshiba Corp | 半導体装置 |
JPS63160242A (ja) * | 1986-12-23 | 1988-07-04 | Nec Corp | 半導体装置 |
JP2004304002A (ja) * | 2003-03-31 | 2004-10-28 | Sony Corp | 半導体装置 |
JP4284242B2 (ja) * | 2004-06-29 | 2009-06-24 | パナソニック株式会社 | 半導体装置およびその製造方法 |
JP2006073947A (ja) * | 2004-09-06 | 2006-03-16 | Renesas Technology Corp | ヒューズ構造 |
-
2007
- 2007-02-09 JP JP2007030263A patent/JP5132162B2/ja active Active
- 2007-05-29 TW TW096119137A patent/TWI418014B/zh active
- 2007-06-18 KR KR1020070059218A patent/KR101360709B1/ko active IP Right Grant
- 2007-07-11 CN CN2007101362315A patent/CN101241900B/zh active Active
- 2007-08-09 US US11/836,609 patent/US20080237787A1/en not_active Abandoned
-
2012
- 2012-08-23 US US13/592,949 patent/US8723291B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5780918A (en) * | 1990-05-22 | 1998-07-14 | Seiko Epson Corporation | Semiconductor integrated circuit device having a programmable adjusting element in the form of a fuse mounted on a margin of the device and a method of manufacturing the same |
US6222244B1 (en) * | 1998-06-08 | 2001-04-24 | International Business Machines Corporation | Electrically blowable fuse with reduced cross-sectional area |
US6486526B1 (en) * | 1999-01-04 | 2002-11-26 | International Business Machines Corporation | Crack stop between neighboring fuses for protection from fuse blow damage |
US6566238B2 (en) * | 1999-02-26 | 2003-05-20 | Infineon Technologies Ag | Metal wire fuse structure with cavity |
US6295721B1 (en) * | 1999-12-28 | 2001-10-02 | Taiwan Semiconductor Manufacturing Company | Metal fuse in copper dual damascene |
US20020017704A1 (en) * | 2000-08-01 | 2002-02-14 | Takashi Yajima | Semiconductor device and method of manufacture |
US6872648B2 (en) * | 2002-09-19 | 2005-03-29 | Infineon Technologies Ag | Reduced splattering of unpassivated laser fuses |
US20040262710A1 (en) * | 2003-06-26 | 2004-12-30 | Nec Electronics Corporation | Semiconductor device |
US20050029620A1 (en) * | 2003-08-07 | 2005-02-10 | Nec Electronics Corporation | Semiconductor device |
US7282751B2 (en) * | 2003-08-07 | 2007-10-16 | Nec Electronics Corporation | Semiconductor device |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100207239A1 (en) * | 2009-02-18 | 2010-08-19 | Nec Electronics Corporation | Semiconductor device and manufacturing method thereof |
US8159041B2 (en) * | 2009-02-18 | 2012-04-17 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
US20140145194A1 (en) * | 2011-09-13 | 2014-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device Components and Methods |
US9875964B2 (en) * | 2011-09-13 | 2018-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device components and methods |
US9679858B2 (en) | 2015-08-26 | 2017-06-13 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing same |
US11026325B2 (en) * | 2017-05-25 | 2021-06-01 | Orpyx Medical Technologies Inc. | Flexible circuit package |
US11659657B2 (en) | 2017-05-25 | 2023-05-23 | Orpyx Medical Technologies Inc. | Flexible circuit package |
Also Published As
Publication number | Publication date |
---|---|
JP5132162B2 (ja) | 2013-01-30 |
US20130049166A1 (en) | 2013-02-28 |
CN101241900A (zh) | 2008-08-13 |
KR20080014601A (ko) | 2008-02-14 |
CN101241900B (zh) | 2012-10-31 |
TW200814293A (en) | 2008-03-16 |
KR101360709B1 (ko) | 2014-02-07 |
JP2008066693A (ja) | 2008-03-21 |
US8723291B2 (en) | 2014-05-13 |
TWI418014B (zh) | 2013-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8723291B2 (en) | Semiconductor integrated circuit | |
KR101151302B1 (ko) | 집적 회로 장치의 퓨즈 구조 | |
KR101531772B1 (ko) | 메탈 e-퓨즈의 구조 | |
JP4364515B2 (ja) | ヒューズレイアウト,及びトリミング方法 | |
US8178942B2 (en) | Electrically alterable circuit for use in an integrated circuit device | |
US7667289B2 (en) | Fuse structure having a tortuous metal fuse line | |
US8598680B2 (en) | Semiconductor device with electrical fuse | |
JP4995512B2 (ja) | 半導体装置 | |
KR102463139B1 (ko) | 켈빈 저항 테스트 구조 및 그 제조 방법 | |
JP2012527768A (ja) | 集積回路のための電気的に切断される金属ヒューズの構造体及びその形成方法 | |
US9214427B2 (en) | Method of self-correcting power grid for semiconductor structures | |
JP5492929B2 (ja) | 半導体装置の製造方法 | |
US20120286390A1 (en) | Electrical fuse structure and method for fabricating the same | |
US9548178B2 (en) | Fuse structure and monitoring method thereof | |
TW202312528A (zh) | 半導體裝置及其製造方法 | |
JP3353748B2 (ja) | 半導体装置およびその製造方法 | |
JP2021174782A (ja) | 半導体装置及びその製造方法 | |
WO2010032350A1 (ja) | 半導体装置及びその製造方法 | |
KR20130050114A (ko) | 반도체 소자의 안티퓨즈 및 그 형성 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: RENESAS TECHNOLOGY CORP., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YONEZU, TOSHIAKI;IWAMOTO, TAKESHI;OBAYASHI, SHIGEKI;AND OTHERS;REEL/FRAME:019678/0644;SIGNING DATES FROM 20070222 TO 20070306 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:024864/0635 Effective date: 20100401 Owner name: NEC ELECTRONICS CORPORATION, JAPAN Free format text: MERGER;ASSIGNOR:RENESAS TECHNOLOGY CORP.;REEL/FRAME:024879/0190 Effective date: 20100401 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |