US20080191240A1 - Avalanche Photo Diode - Google Patents

Avalanche Photo Diode Download PDF

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Publication number
US20080191240A1
US20080191240A1 US11/914,871 US91487105A US2008191240A1 US 20080191240 A1 US20080191240 A1 US 20080191240A1 US 91487105 A US91487105 A US 91487105A US 2008191240 A1 US2008191240 A1 US 2008191240A1
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layer
light absorption
avalanche photodiode
semiconductor layer
electrode
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Eiji Yagyu
Eitaro Ishimura
Masaharu Nakaji
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Assigned to MITSUBISHI ELECTRIC CORPORATION reassignment MITSUBISHI ELECTRIC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ISHIMURA, EITARO, NAKAJI, MASAHARU, YAGYU, EIJI
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
    • H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This invention relates to a light receiving element using a semiconductor and in particular to an avalanche photodiode with low dark current and high reliability for the long term.
  • An avalanche photodiode which is used for optical communications or the like, is a semiconductor light receiving element including, in addition to a layer for performing photoelectric conversion, a layer for performing avalanche multiplication of photoelectric converted carriers, which achieves enhanced light reception sensitivity; it is required for the avalanche photodiode to have a low dark current property and high reliability.
  • the mesa structure is a structure in which a mesa is formed on a substrate and a pn junction is contained in the mesa.
  • a breakdown easily occurs on the surface of the mesa periphery.
  • it is designed to suppress the dark current at law level by employing a structure formed with a slope and a structure in which a buried layer as a high resistance part is provided in the mesa outer peripheral region (for example, Patent Document 1).
  • the planar structure is a structure in which a pn junction is formed by providing a selective diffusion region, but an edge breakdown in the edge part of the pn junction introduces a problem.
  • a current flows in the edge part, if voltage is increased, the reverse voltage of the pn junction of a light reception section positioned at the center scarcely increases and thus the function as an avalanche photodiode cannot be demonstrated.
  • a measure such that a high-resistance guard ring is provided by injecting impurities into the edge part is taken (for example, Patent Document 2).
  • Patent Document 1 JP-A-2002-324911 (FIG. 1)
  • Patent Document 2 JP-A-7-312442 (pages 4-6, FIGS. 2 and 6)
  • planar structure which is described as pseudo planar structure in Patent Document 2
  • a trench must be formed for conducting ion implantation of Ti, etc. and the activation of the implanted ion is required, and an etching stopper layer needs to be provided.
  • an impurity diffusion layer is provided on the outer periphery and thus the process becomes complicated and the manufacturing cost rises and the yield becomes poor. Since the electric field strength of the guard ring in a light absorption layer becomes high, the tunnel dark current increases.
  • the invention is conceived for solving the problems and it is an object of the invention to provide an avalanche photodiode that can be manufactured in a simple process, can suppress dark current, and ensures long-term reliability.
  • An avalanche photodiode includes a first electrode; and a substrate including a first semiconductor layer made of a first conduction type electrically connected to the first electrode, wherein at least an avalanche multiplication layer, a light absorption layer, and a second semiconductor layer made of a second conduction type with a larger band gap than the light absorption layer are deposited on the substrate, wherein the second semiconductor layer is separated into an inner region and an outer region by a groove formed therein, and wherein the inner region is electrically connected to a second electrode.
  • an avalanche photodiode with low dark current and high long-term reliability in a simple process.
  • FIG. 1 is a sectional view to show the schematic structure of an avalanche photodiode according to a first embodiment of the invention.
  • FIG. 2 is a characteristic drawing to represent an electric field strength distribution in the depth direction in a section taken on line A-A′ in FIG. 1 according to the first embodiment of the invention.
  • FIG. 3 is a characteristic drawing to represent an electric field strength distribution in the plane direction in a section taken on line B-B′ and a section taken on line C-C′ in FIG. 1 according to the first embodiment of the invention.
  • FIG. 4 is a sectional view to show the schematic structure of an avalanche photodiode according to a second embodiment of the invention.
  • FIG. 5 is a sectional view to show the schematic structure of an avalanche photodiode according to a third embodiment of the invention.
  • FIG. 6 is a sectional view to show the schematic structure of an avalanche photodiode according to a fourth embodiment of the invention.
  • FIG. 7 is a top view to show the schematic structure of an avalanche photodiode according to a fourth embodiment of the invention.
  • FIG. 8 is a characteristic drawing to show the relationships among current, multiplication factor M, and reverse bias voltage about the avalanche photodiode according to the fourth embodiment of the invention.
  • FIG. 9 is a sectional view to show the schematic structure of an avalanche photodiode according to a fifth embodiment of the invention.
  • FIG. 10 is a sectional view to show the schematic structure of an avalanche photodiode according to a sixth embodiment of the invention.
  • FIG. 11 is a perspective view to show the schematic structure of an avalanche photodiode according to a seventh embodiment of the invention.
  • FIG. 1 is a sectional view to show the schematic structure of an avalanche photodiode according to a first embodiment of the invention.
  • n type is used as a first conduction type
  • p type is used as a second conduction type
  • an n electrode is used as a first electrode
  • a p electrode is used as a second electrode.
  • Each semiconductor layer can be manufactured using MO-CVD, a molecular beam epitaxy (MBE), etc., on a wafer-like substrate 1 of n type InP, etc., for example.
  • the semiconductor layers are manufactured according to the following step order;
  • a first semiconductor layer 2 (which will be hereinafter referred to as buffer layer) of n type InP, etc., at a carrier density of 0.2 to 2 ⁇ 10 19 cm ⁇ 3 is grown to a thickness of 0.1 to 1 ⁇ m, an avalanche multiplication layer 4 of i type AlInAs is grown to a thickness of 0.15 to 0.4 ⁇ m, a field relaxation layer 5 of p type InP at a carrier density of 0.5 to 1 ⁇ 10 18 cm ⁇ 3 is grown to a thickness of 0.03 to 0.06 ⁇ m, a light absorption layer 6 of p ⁇ type GaInAs at a carrier density of 1 to 5 ⁇ 10 15 cm ⁇ 3 is grown to a thickness of 1 to 1.5 ⁇ m, a second semiconductor layer 8 p type InP is grown to a thickness of 1 to 2 ⁇ m, and a contact layer 9 of p type GaInAs is grown to a thickness of 0.1 to 0.5 ⁇
  • detected light is incident from the opposite side to the substrate 1 (which will be hereinafter referred to as surface incidence) and thus the band gap of the second semiconductor layer 8 is made larger than energy of the detected light.
  • the second semiconductor layer 8 allows detected light to pass through and therefore will be hereinafter referred to as window layer.
  • an SiOx film is formed as a mask, and the center and the external part are etched out so that the contact layer 9 is left like a ring having an inner diameter of 20 ⁇ m and a width of 5 to 10 ⁇ m.
  • the SiNx film is removed, and thereafter an SiOx film is formed as a mask, and then the groove 10 with a ring shape having a width of 5 mm is formed by removing at least the second semiconductor layer 8 , thereby being divided into an inner region 110 and an outer region 111 .
  • an SiNx surface protective film and concurrently reflection prevention film 120 is formed by evaporation and the SiNx surface protective film and concurrently reflection prevention film 120 on the contact layer 9 is removed and a p electrode 14 is formed of AuZn/Au on the contact layer 9 .
  • the face of the substrate 1 opposite to the deposition layer of the buffer layer 2 is ground and an n electrode 13 is formed of AuGe/Au and the buffer layer 2 is electrically connected to the n electrode 13 .
  • cleavage separation of the wafer-like substrate 1 is performed to form an element about 300 ⁇ m square having a cleavage plane 27 .
  • Light 28 is made incident from the p electrode 14 side in a state in which a reverse bias voltage is applied from the outside so that the n electrode 13 side becomes plus and the p electrode 14 side becomes minus.
  • a reverse bias voltage is applied from the outside so that the n electrode 13 side becomes plus and the p electrode 14 side becomes minus.
  • the light passes through the window layer 8 with large band gap and is absorbed in the light absorption layer 6 to generate an electron-hole pair and the electron moves to the n electrode 13 side and the hole moves to the p electrode 14 side.
  • the electron is ionized to generate a new electron-hole pair and causes further ionization together with the newly generated electron and hole, whereby avalanche multiplication of multiplying the electrons and the holes like an avalanche is caused.
  • FIG. 2 is a characteristic drawing to represent an electric field strength distribution in the depth direction in a section taken on line A-A′ in FIG. 1
  • FIG. 3 is a characteristic drawing to represent an electric field strength distribution in the plane direction in a section taken on line B-B′ and a section taken on line C-C′ in FIG. 1 .
  • the symbols on the horizontal axes of FIGS. 2 and 3 denote the formed semiconductor layers described above and in the figures, the A-A′ section is represented as A-A′, the B-B′ section is represented as B-B′, and the C-C′ section is represented as C-C′.
  • FIG. 2 is a characteristic drawing to represent an electric field strength distribution in the depth direction in a section taken on line A-A′ in FIG. 1
  • FIG. 3 is a characteristic drawing to represent an electric field strength distribution in the plane direction in a section taken on line B-B′ and a section taken on line C-C′ in FIG. 1 .
  • the portion of the highest electric field becomes the avalanche multiplication layer 4 .
  • the electric field strength distribution in the B-B′ section in FIG. 3 the light reception region center just below the inner region 110 becomes the highest region and the electric field strength lessens as the region is closer to the peripheral portion.
  • the electric field strength in the peripheral portion of the inner region 110 becomes higher than the center, but is lower than the electric field strength applied to the avalanche multiplication layer 4 as compared with the electric field strength distribution in the B-B′ section in FIG. 2 , so that the current amplification in the peripheral portion known as edge breakdown and the occurrence of current known as tunnel breakdown can be suppressed and the avalanche photodiode can be functioned as an avalanche photodiode.
  • the avalanche photodiode according to the embodiment need not be provided with a structure called a guard ring for suppressing an edge breakdown, and an avalanche photodiode having a low dark current and high reliability can be easily realized.
  • a p type conductive region 10 by selective thermal diffusion using Zn may be any if it gives p conduction type.
  • a p type conductive region may be formed by a Zn selective thermal diffusion method using an SiOx film in which a circle is cut as a mask, then a Zn film of a supply source of diffusion and the SiOx film may be removed, and further thermal diffusion treatment may be again performed for diffusing Zn in the p type conductive region (which will be hereinafter referred to as Zn addition diffusion).
  • the avalanche photodiode can also be formed, for example, by executing ion implantation of Be using a photo resist film in which a circle is cut as a mask and then removing the photo resist film and thermal annealing treatment is performed for about 12 hours at about 700° C. (which will be hereinafter referred to as Be implantation).
  • FIG. 4 is a characteristic drawing to show the carrier density differences in the depth direction (conductive region 10 -window layer 8 junction part) when the Zn selective thermal diffusion (D in the figure), the Zn addition diffusion (E in the figure), and the Be implantation (F in the figure) are used as the forming method of the p type conductive region 10 (the symbols on the horizontal axis correspond to the layers)
  • Zn selective thermal diffusion D in the figure
  • Zn addition diffusion E in the figure
  • F Be implantation
  • the field relaxation layer 5 is formed of p type InP by way of example, but may be formed of AlInAs.
  • the field relaxation layer 5 can also be omitted depending on the situation.
  • the contact layer 9 for electrically connecting the p type conductive region 10 and the p electrode 14 is provided by way of example, but the p type conductive region 10 and the p electrode 14 may be brought into direct contact with each other.
  • i type InP is used by way of example, but the conduction type may be any of semi-insulation property, insulation property, n type, or low-conductivity p type.
  • a stopper layer 3 containing GaInAsP, AlInAs, AlGaInAs, GaInAsP, etc., is provided between the window layer 8 and the light absorption layer 6 because diffusing of the p type conductive region from the p type conductive region 10 to the light absorption layer 6 can be suppressed.
  • FIG. 4 is a sectional view to show a schematic structure of an avalanche photodiode according to a second embodiment of the invention.
  • a third semiconductor layer 15 with a larger band than the light absorption layer 6 and formed of i type InP having about 0.03 ⁇ m is provided between the light absorption layer 6 and the second semiconductor layer 8 , and a groove 10 is formed by leaving the third semiconductor layer 15 .
  • the lower portion of the groove 10 exposed to the outside can be formed with a larger band gap than the light absorption layer 6 . Therefore, it is possible to achieve suppression of surface deterioration in the lower portion of the groove 10 , suppression of deterioration in dark current characteristics, and improvement in durability.
  • the region in which electric field strength thereof is partially high in the periphery of the light reception region can be formed with a larger band gap than the light absorption layer 6 . Therefore, it is possible to suppress the amplification of current in the periphery known as the edge breakdown and to suppress the occurrence of current known as the tunnel breakdown.
  • i type InP is used as the third semiconductor layer 15 by way of example, but i type AlInAs, i type AlGaInAs, and the like may be used. Since it is possible to perform a selective etching due to difference in an etching rate by using materials different from composition of the window layer 8 , the groove 10 having a desired depth can be formed with high reliability. In this case, it is possible to serve as a hole transition layer as well.
  • i type is used as the third semiconductor layer 15 by way of example, but the third semiconductor layer 15 may have a larger band gap that the light absorption layer 6 and may not be the second conduction type. Therefore, a semi-insulating type may be used.
  • the third semiconductor layer 15 is formed of one layer by way of example, but may be formed of a plurality of layers.
  • FIG. 5 is a sectional view to show a schematic structure of an avalanche photodiode according to a third embodiment of the invention.
  • an outer trench 26 is further provided in the outer periphery of the inner region 110 separated by the groove 10 and by removing up to the light absorption layer 6 , for example, so that a circular region is left about 100 ⁇ m in diameter to form the side face 25 .
  • a depletion region 11 is formed right under the inner region 110 .
  • the dark current occurs mainly from the light absorption layer 6 and flows through the depletion region 11 and along the side face of the element. Accordingly, when the outer trench 26 is provided in the periphery of the light absorption layer 6 surrounding the depletion region 11 , it is possible to shut off the path of the dark current, thereby decreasing the dark current.
  • a width (W 1 in FIG. 4 ) from the outside of the inner region 110 to the side face 25 may be nm order, but long-term characteristics thereof can be kept as it be comes larger. Accordingly, the width may be 5 ⁇ m or more, preferably 10 ⁇ m or more, and more preferably 30 ⁇ m or more.
  • the width or the diameter of the light absorption layer 6 left at the forming the outer trench 26 is set to about 50 to about 200 ⁇ m.
  • the shape of the light absorption layer 6 is not limited; it may be left like a circle or an ellipse or may be polygonal such as quadrangular or pentagonal. When it is polygonal, preferably each corner is rounded because electric field concentration in the corner can be prevented.
  • the dark current is suppressed from occurring in the outer trench 26 on the inside; and scratch and chip are prevented from occurring at the end of element outer trench (not shown) on the outside, thereby preventing physical damage.
  • the outer trench 26 may be formed in the same manner as the manner for forming the above-described groove 10 .
  • a hydrochloric acid base solution such as a hydrochloric acid/phosphoric acid mix solution may be used.
  • an organic acid base solution such as organic acid (citric acid, tartaric acid, etc.)/hydrogen peroxide water mix solution or a nitric acid base solution may be used. If Br base solution such as HBr/hydrogen peroxide water, Br/methanol, and the like small in selective etching property or the like is used in combination with them, it is possible to accomplish any desired side face removal.
  • the side face 25 may be provided with a protective film 12 (not shown) formed using organic materials such as SiNx and SiOx.
  • the protective film 12 is provided, whereby oxidation and moisture absorption can be prevented, occurrence of a dark current can be suppressed, and further long-term reliability can be obtained.
  • semiconductor crystal may be re-grown by MO-CVD or the like to serve as the protective film 12 .
  • the semiconductor crystal serving as the protective film 12 crystal having low-conductive i type or crystal having a semi-insulating property and a large band gap may be used, for example, InP, AlInAs, etc. Since the protective film 12 is formed of the semiconductor crystal, it is possible to suppress deterioration on an interface in comparison with a dielectric.
  • the outer trench 26 is formed up to the field relaxation layer 5 by way of example, but it may be removed up to a deeper layer than the avalanche multiplication layer 4 .
  • the window layer 8 and the light absorption layer 6 are joined to each other by way of example, but a transition layer 7 (not shown) or an etching stopper layer 3 (not shown) may be provided between the window layer 8 and the light absorption layer 6 .
  • the side face 25 is provided perpendicular to the substrate 1 by way of example, but it may be provided in another shape such as a trapezoid. Since it is difficult that the dark current flows due to a step provided between the light absorption layer 6 and the field relaxation layer 5 , it may be partially removed.
  • the field relaxation layer 5 when the field relaxation layer 5 is not necessary, the field relaxation layer 5 may be omitted and a step may be provided thereunder between the avalanche multiplication layer 4 and the light absorption layer 6 .
  • FIG. 6 is a sectional view to show a schematic structure of an avalanche photodiode according to a fourth embodiment of the invention
  • FIG. 7 is a top view thereof.
  • an n type low refractive index layer such as InP or AlInAs at a carrier density of about 0.1 to 2 ⁇ 10 19 cm ⁇ 3 and a high refractive index layer such as GaInAs, GaInAsP, or AlGaInAs are set as a pair.
  • the reflection adjustment layer 24 adjusts a phase of light between the light absorption layer 6 and the reflection layer 23 , and increases reflectance of the light, which passes through the light absorption layer 6 , in the reflection layer 23 .
  • the second semiconductor layer (window layer) 8 is formed of two layers of a first window layer 81 formed of p type AlInAs grown to a thickness of about 0.1 to 0.3 ⁇ m at a carrier density of about 0.1 to 2 ⁇ 10 19 cm ⁇ 3 and a second window layer 82 formed of p type InP grown to a thickness of about 0.4 to 1.0 ⁇ m.
  • the first window layer 81 has a larger width than that of the second window layer 82 with a gap of about 2 ⁇ m width between the first window layer 81 and the second window layer 82 .
  • a hole transition layer 7 As a hole transition layer 7 , 3 to 9 layers of i type GaInAsP or AlGaInAs are deposited each about 0.03 ⁇ m between the light absorption layer 6 and the first window layer 81 , gradually increasing band gap energies.
  • i type InP layer is provided by about 0.01 to 0.05 ⁇ m.
  • a groove 10 is provided for separation between the inner region 110 and the outer region 111 , and the groove 10 is formed to generate a difference in width of about 2 ⁇ m on one side between the first window layer 81 and the second window layer 82 .
  • a part of the outer region 111 is removed up to the reflection layer 23 to provide an outer trench 26 for forming a side face 25 , and a field relaxation layer 5 is formed to protrude from the side face 25 by about 5 ⁇ m.
  • a protective film 12 is provided on the surface of the element.
  • a width W 1 in FIGS. 6 and 7 that is, a distance from the outside of the inner region 110 to the side face 25 is about 80 ⁇ m.
  • a width W 2 that is, a width of the light absorption layer 6 in the outer trench 26 is about 200 ⁇ m.
  • a layer formed by depositing 1 ⁇ 4 wavelength distribution Bragg reflection layer 23 and the reflection adjustment layer 24 is formed as the first semiconductor layer 2 , it is possible to reflect some light, which is not absorbed by the light absorption layer 6 and passes therethrough, to the light absorption layer 6 again. Therefore, it is possible to more increase the amount of light absorption in the light absorption layer 6 and thus it is possible to increase light sensitivity of the avalanche photodiode.
  • the transition layer 7 is provided between the light absorption layer 6 and the first window layer 81 , the discontinuous amount of the valence band between the light absorption layer 6 and the first window layer 81 is suppressed and pile-up of holes at a hetero interface can be prevented. Therefore, higher-speed light response can be realized from low multiplication factor.
  • the etching stopper layer 3 is provided between the light absorption layer 6 and the first window layer 81 , it is possible to reliably etch the first window layer 81 by the groove 10 .
  • the window layer 8 is formed of the first window layer 81 (upper portion) having low mobility and the second window layer 82 (lower portion) having high mobility, the second window layer 82 can be made thin. Therefore, it is possible to more decrease resistance than a case where only window layers having low mobility are provided.
  • first window layer 81 has a lager width than that of the second window layer 82 , resistance of the outer periphery of the second window layer 82 in the inner region 110 can be more increased than that of the center thereof. Therefore, it is possible to prevent the tunnel dark current from flowing in the outer periphery. Also, it is possible to prevent breakdown.
  • the light absorption layer 6 is removed by the outer trench 26 , it is possible to prevent, in the outer region 111 surrounded by the outer trench 26 , current generated in the light absorption layer 6 from flowing through the avalanche multiplication layer 4 to the reflection layer 23 or the reflection adjustment layer 24 as a path of the side face 25 . Therefore, it is possible to reduce the dark current.
  • the outer trench 26 is provide in a part of the outer region 111 to form the side face 25 and the outmost region is left, it is possible to suppress the dark current and to secure the strength of the element.
  • FIG. 8 is a characteristic diagram to show a relation among current, multiplication factor M, and reverse bias voltage in the avalanche photodiode according to the present embodiment.
  • the dashed line in the figure indicates the dark current characteristic of the avalanche photodiode with element separation by providing the groove 10 and simply executing cleavage without providing the outer trench 26 .
  • the dark current (Idark in the figure) independent of the reverse bias voltage is a generated dark current from the light absorption layer 6 and in the configuration of simple cleavage, the generated dark current flows via a cleavage plane, and thus the dark current becomes 10 ⁇ 7 A level (Idark dashed line in the figure).
  • the path of the generated dark current can be shut off from the light absorption layer 6 , so that the dark current can be decreased to 10 ⁇ 8 A level (Idark solid line in the figure).
  • the high multiplication factor of fifty times or more it is possible to obtain the high multiplication factor of fifty times or more.
  • the groove 10 is provided with the step and the first window layer 81 has a larger width than that of the second window layer 82 by way of example, and the outer trench 26 is provided with the step by way of example, but both examples have an advantage of reducing the dark current. Accordingly, any one of both may be used.
  • the reflection layer 23 and the reflection adjustment layer 24 are deposited as the first semiconductor layer 2 by way of example, the transition layer 7 is provided between the light absorption layer 6 and the first window layer 81 by way of example, and the etching stopper layer 3 is provided between the light absorption layer 6 and the first window layer 81 by way of example, but all the examples have an advantage of improving the characteristics of the avalanche photodiode. Accordingly, any one of them or combination of them may be used.
  • the reflection layer 23 and the reflection adjustment layer 24 are deposited as the first semiconductor layer 2 by way of example, but the first semiconductor layer 2 may be formed of a part of the substrate 1 and another layer may be added.
  • the transition layer 7 and the etching stopper layer 3 are formed of i type as the hole transition layer by way of example, but a semi-insulating type or a low conduction type (preferably, n type) at a carrier density of 5 ⁇ 10 15 cm ⁇ 3 or less may be used.
  • the etching stopper layer 3 is formed of InP and the first window layer 81 coming into contact with the etching stopper layer 3 is formed of AlInAs, but the other materials may be used if the combination of the materials is suitable to selectively execute the etching.
  • the etching stopper layer 3 may be formed of AlInAs and the first window layer 81 may be formed of InP. 4-element based semiconductor may be used.
  • a third semiconductor layer 15 with a larger band gap than light absorption layer 6 may be provided between the first window layer 81 and the light absorption layer 6 .
  • the first layer 81 is configured to have a larger width than that of the second window layer 82 , but both layers may have the same width.
  • the whole second semiconductor layer 8 in the outer region 111 may be removed by the groove 10 .
  • the outer trench 26 is provided with the step, but the outer trench 26 may be formed in a straight shape. Further, the periphery of the outer region 111 may be provided with a second outer trench. Accordingly, it is possible to prevent physical damage, which may be caused in the vicinity of the cleavage plane at the time of handling the element, by the second outer trench.
  • the outer trench 26 may extend to the cleavage plane 27 .
  • the outer trench 26 may be formed to reach the reflection layer 23 or the reflection adjustment layer 24 (first semiconductor layer 2 ).
  • the n electrode 13 can be provided in this portion and the p electrode 14 and the n electrode 13 are on the same plane. Therefore, it is possible to simplify the process, which is preferable.
  • the lower portion thereof is on the n type GaInAs layer, contact resistance decreases, which is more preferable.
  • FIG. 9 is a sectional view to show a schematic structure of an avalanche photodiode according to a fifth embodiment of the invention.
  • an n type or Fe-doped high optical-transparency semi-insulating substrate is used as the substrate 1 , and light 28 is made incident from the substrate 1 side.
  • n type InP or AlInAs is deposited at a carrier density 0.1 to 2 ⁇ 10 19 cm ⁇ 3 with a thickness of 0.1 to 1.5 ⁇ m as a first semiconductor layer 2
  • i type AlIAs is deposited with a thickness of 0.15 to 0.4 ⁇ m as the avalanche multiplication 4
  • p type InP or AlInAs is deposited at a carrier density of 0.3 to 1 ⁇ 10 18 cm ⁇ 3 with a thickness of 0.03 to 0.1 ⁇ m as a field relaxation layer 5
  • GaInAs is deposited at a carrier density of 5 ⁇ 10 15 cm ⁇ 3 or less with a thickness of 1 to 2.5 ⁇ m as a light absorption layer 6 .
  • i type GaInAsP or AlGaInAs having a large band gap energy are sequentially deposited with a thickness of 0.01 to 0.03 ⁇ m/layer as a transition layer 7 , i type InP is grown with a thickness of 0.01 to 0.05 ⁇ m as an etching stopper layer 3 , p type AlInAs (first cap layer 83 ) is grown at a carrier density of 0.1 to 2 ⁇ 10 19 cm ⁇ 3 as a second semiconductor layer 8 (serving as a cap layer), InP (second cap layer 84 ) is grown with a thickness of 0.3 to 1.0 ⁇ m, and p type GaInAs is grown with a thickness of 0.1 to 0.5 ⁇ m as a contact layer 9 , sequentially.
  • a groove 10 is formed, the contact layer 9 in the inner region 110 is removed by leaving it in a circular shape, an outer trench 26 is formed up to the first semiconductor layer 2 in a longitudinal direction (it is preferable to perform the removal up to a portion where the n type InP appears) and up to the cleavage plane 27 in a width direction.
  • a protective film 12 is formed of SiNx
  • an n electrode 13 is formed on a portion excluding the protective film 12 on the first semiconductor layer 2 in the lower portion of the outer trench 26
  • a p electrode 14 is formed on a portion excluding the protective film 12 above the contact layer 9 .
  • Grinding and etching are performed on a surface of the substrate 1 opposite to a surface thereof on which the semiconductor layers are deposited, a reflection prevention film 21 is formed of SiNx, and a sinter treatment is performed thereon. Cleavage separation of the wafer-like substrate 1 is performed to form an element with a size of 300 ⁇ m ⁇ 300 ⁇ m having a cleavage plane 27 .
  • the avalanche photodiode according to the present embodiment is formed in the above-described manner, the light 28 is made incident from the substrate 1 side, the light passing through the light absorption layer 6 is reflected by the p electrode 14 , and the light is absorbed again by the light absorption layer 6 .
  • the n electrode 13 and the p electrode 14 are provided on the same plane side of the substrate 1 , a flip chip mounting is applicable.
  • the back-surface incident type according to the present embodiment it is possible to make the area of the inner region 110 become smaller than that of the front-surface incident type according to the first to third embodiments Therefore, it is possible to reduce the volume of the element and to perform a high-speed operation.
  • the reflection of the electrode 14 is applicable, it is possible to obtain reliable sensitivity without the reflection layer 23 .
  • the groove 10 and the outer trench 26 are continuously formed to prevent the protective layer 12 from cutoff by way of example, but the back-surface type may be produced in the same manner as a configuration of only the groove 10 or a configuration of the groove 10 and the outer trench 26 that are not continuously formed, as shown in the first to fourth embodiments.
  • FIG. 10 is a sectional view to show a schematic structure of an avalanche photodiode according to a sixth embodiment of the invention.
  • a plurality of semiconductor layers are formed in the same manner as the fifth embodiment.
  • the outer trench 26 is formed to extend from the groove 10 , the outer region 111 in the periphery thereof is removed again up to the etching stopper layer 3 , and the n electrode 13 is provided in the outer trench 26 and on the protective film 12 formed on the etching stopper layer 3 .
  • the n electrode 13 is provided on the protective film 12 , adhesion of the n electrode 13 is improved and thus it is possible to prevent it from peeling off.
  • the inner region 110 does not have a protruding shape, it is possible to prevent damage caused by physical contact to the inner region 110 .
  • the substrate 1 is grinded to attach another substrate to the opposite surface of the substrate 1 , it is possible to disperse pressure applied to the opposite surface of the substrate 1 . Therefore, it is possible to improve strength and to prevent damage.
  • FIG. 11 is a perspective view to show a schematic structure of an avalanche photodiode according to a seventh embodiment of the invention.
  • light 28 is made incident to a side face thereof.
  • a method of depositing each semiconductor layer is the same as the fourth embodiment.
  • the inner region 110 is left in a rectangular shape and is removed up to the etching stopper layer 3 by the groove 10 .
  • a clad is formed by removing the outer region 111 up to the upper portion of the first semiconductor layer 2 by the outer trench 26 in a rectangular shape so as to surround the inner region 110 left in the rectangular shape.
  • a contact layer 9 is provided on the window layer 8 in the inner region 110 , and a p electrode 14 is formed on the protective film 12 provided on the etching stopper layer 3 from the contact layer 9 through a wall portion of the groove 10 .
  • a light incidence face is the side wall of the inner region 110 .
  • the groove 10 and the outer trench 26 are continuously removed up to the second semiconductor layer (preferably, up to a portion where the n type InP appears) in a depth direction and up to cleavage plane 27 in a width direction.
  • n electrode 13 is provided on the protective film 12 on the upper portion of the first semiconductor layer 2 , and an element is mounted by the use of a metallic member (now shown).
  • the avalanche photodiode may have a waveguide structure using the light absorption layer 6 as a core.
  • the light 28 is made incident to the side wall of the inner region 110 , the light is absorbed during a waveguide transmission of the light. Therefore, it is possible to make the light absorption layer 6 thin, and to make the area of pn junction small. Since it is possible to reduce a traveling time of electrons or holes and to reduce a volume, it is possible to perform a high-speed operation.
  • the avalanche photodiode is used as a strip-loaded type waveguide by way of example, but a slab type waveguide and a reclaimed type waveguide may be applicable.
  • a clad layer may be provided on both upper and lower portions or on any one of both, between the first semiconductor layer 2 and the multiplication layer 4 or on the light absorption layer 6 , so as to tighten optical confinement.
  • the n type is used as the first conduction type
  • the p type is used as the second conduction type
  • the n electrode is used as the first electrode
  • the p electrode is used as the second electrode by way of example, but the p type may be used as the first conduction type
  • the n type may be used as the second conduction type
  • the p electrode may be used as the first electrode
  • the n electrode may be used as the second electrode.

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US20100019275A1 (en) * 2007-01-22 2010-01-28 Nec Corporation Semiconductor photo detector
US8039918B2 (en) * 2007-01-22 2011-10-18 Nec Corporation Semiconductor photo detector
US20100133637A1 (en) * 2008-12-02 2010-06-03 Mitsubishi Electric Corporation Avalanche photodiode
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EP2747154A1 (en) 2012-12-21 2014-06-25 ams AG Lateral single-photon avalanche diode and method of producing a lateral single-photon avalanche diode
WO2014096210A1 (en) 2012-12-21 2014-06-26 Ams Ag Lateral single-photon avalanche diode and method of producing a lateral single-photon avalanche diode
US10128385B2 (en) 2012-12-21 2018-11-13 Ams Ag Lateral single-photon avalanche diode and method of producing a lateral single photon avalanche diode
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