US20070201275A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
US20070201275A1
US20070201275A1 US11/699,501 US69950107A US2007201275A1 US 20070201275 A1 US20070201275 A1 US 20070201275A1 US 69950107 A US69950107 A US 69950107A US 2007201275 A1 US2007201275 A1 US 2007201275A1
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film
insulating film
semiconductor device
nitride film
insulating
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Wakako Takeuchi
Hiroshi Akahori
Murato Kawai
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Toshiba Corp
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AKAHORI, HIROSHI, KAWAI, MURATO, TAKEUCHI, WAKAKO
Publication of US20070201275A1 publication Critical patent/US20070201275A1/en
Priority to US12/659,482 priority Critical patent/US8153487B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a semiconductor device including a nonvolatile semiconductor memory such as a NAND flash memory and a method for manufacturing the semiconductor device.
  • a nonvolatile semiconductor memory is one of the semiconductor memory devices.
  • the nonvolatile semiconductor device is in increasing demand as data storage device.
  • NAND flash memory is known as typical electrically rewritable nonvolatile memory using floating gate (FG) electrode and control gate (CG) electrode.
  • FG floating gate
  • CG control gate
  • a stacked type electrode comprising a first electrode formed of polycrystalline silicon and a second electrode provided on the first electrode and formed of metal silicide (Jpn. Pat. Appln. KOKAI Publication No. 2-188969).
  • Device elements have been increasingly miniaturized in order to increase the storage capacity of NAND flash memory.
  • the miniaturization of the device elements increases the aspect ratio of the device element structure.
  • the CG electrode of the stacked type it is difficult to inhibit an increase in the aspect ratio of the CG electrode resulting from the miniaturization of the device elements. The reason is as mentioned below. Because the electrode formed of polycrystalline silicon has a higher resistance than the electrode formed of metal silicide, it requires thickening the electrode formed of metal silicide in order to suppress resistance increase caused by miniaturization of the device elements.
  • a semiconductor device comprising: a semiconductor substrate; a first insulating film provided on the semiconductor substrate; a charge storage layer provided on the first insulating film; a second insulating film comprising a plurality of insulating films provided on the charge storage layer and comprising a nitride film as an uppermost layer; and a single-layer control gate electrode provided on the second insulating film and comprising metal silicide.
  • a semiconductor device comprising: a semiconductor substrate; a first insulating film provided on the semiconductor substrate; a charge storage layer provided on the first insulating film; a second insulating film provided on the charge storage layer; and a multilayer control gate electrode provided on the second insulating film and comprising a semiconductor film, a third insulating film whose an uppermost layer is a nitride film, and a metal silicide film provided on the third insulating film.
  • a method for manufacturing a semiconductor device comprising a nonvolatile semiconductor memory including a semiconductor substrate and a gate structure provided on the semiconductor substrate, the gate structure comprising an insulating film and a control gate electrode provided on the insulating film, the method comprising: forming an insulating film whose uppermost layer is a nitride film as the insulating film of the gate structure; forming a semiconductor film on the insulating film; processing the semiconductor film and the insulating film into a gate; forming a refractory metal film on an area including the semiconductor film; and forming a single-layer control gate electrode comprising a metal silicide film, the forming the control gate electrode comprising converting whole of the semiconductor film into a metal silicide film by heat treatment.
  • FIG. 1 is a plan view showing a part of a memory cell array in a NAND flash memory
  • FIG. 2 is an equivalent circuit diagram of the memory cells shown in FIG. 1 ;
  • FIG. 3 is a sectional view showing a method for manufacturing a NAND flash memory in accordance with a first embodiment
  • FIG. 4 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the first embodiment following FIG. 3 ;
  • FIG. 5 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the first embodiment following FIG. 4 ;
  • FIG. 6 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the first embodiment following FIG. 5 ;
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the first embodiment following FIG. 6 ;
  • FIG. 8 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the first embodiment following FIG. 7 ;
  • FIG. 9 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the first embodiment following FIG. 8 ;
  • FIG. 10 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the first embodiment following FIG. 9 ;
  • FIG. 11 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the first embodiment following FIG. 10 ;
  • FIG. 12 is a sectional view showing a method for manufacturing a NAND flash memory in accordance with a second embodiment
  • FIG. 13 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the second embodiment following FIG. 12 ;
  • FIG. 14 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the second embodiment following FIG. 13 ;
  • FIG. 15 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the second embodiment following FIG. 14 ;
  • FIG. 16 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the second embodiment following FIG. 15 ;
  • FIG. 17 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the second embodiment following FIG. 16 ;
  • FIG. 18 is a cross-sectional view showing the method for manufacturing the NAND flash memory of the first embodiment following FIG. 17 .
  • FIG. 1 is a plain view showing a part of a memory cell array in a NAND flash memory.
  • FIG. 2 is an equivalent circuit diagram of the memory cell array shown in FIG. 1 .
  • M 1 , M 2 , . . . , Mn ⁇ 1, and Mn denote a plurality of memory cells.
  • the plurality of memory cells M 1 , M 2 , . . . , Mn ⁇ 1, and Mn constitute a NAND cell by being connected together in series so that the adjacent memory cells share a source/drain.
  • a drain terminal of the NAND cell is connected to a bit line BL via a select transistor Q 1 .
  • a source terminal of the NAND cell is connected to a source line SL via a select transistor Q 2 .
  • Each of the memory cells M 1 , M 2 , . . . , Mn ⁇ 1, and Mn comprises MOSFET including a double gate structure (in which a CG electrode is stacked on a FG electrode via an insulating film) on a silicon substrate via a gate insulating film.
  • Select transistors S 1 and S 2 comprise MOSFETs. The MOSFETs are formed on the same well substrate.
  • Gate electrodes of select transistors Q 1 and Q 2 are connected to select gate lines SG 1 and SG 2 disposed in the row direction of the memory cell array.
  • Each word line has a connection pad at one end which is connected to a peripheral circuit via a metal interconnection; this end is formed on an isolation film.
  • FIG. 3 - FIG. 11 are sectional views showing a method for manufacturing the NAND flash memory in accordance with the present embodiment.
  • FIGS. 3 to 11 correspond to sectional views of the NAND flash memory taken along line A-A′ in FIG. 1 .
  • FIG. 3 [ FIG. 3 ]
  • a silicon oxide film 2 is formed on a silicon substrate 1 by thermal oxidation method.
  • the silicon oxide film 2 is converted into an oxynitride film 3 .
  • the conversion from the silicon oxide film 2 into the oxynitride film is performed by nitriding treatment using nitriding agent, such as NO gas or ammonia gas.
  • nitriding agent such as NO gas or ammonia gas.
  • the oxynitride film 3 is generally called a tunnel insulating film.
  • the tunnel insulating film is not limited to the oxynitride film 3 , an oxide film may be used.
  • FIG. 5 [ FIG. 5 ]
  • a polycrystalline silicon film 4 doped with phosphorous as impurity is formed on the oxynitride film 3 by CVD process.
  • the silicon film 4 is processed into a FG electrode.
  • an amorphous silicon film is first formed and then converted into a polycrystalline silicon film 4 by heat treatment.
  • An insulating film (inter-gate-electrode insulating film) 5 comprises as a stacked structure which has a nitride film as an uppermost layer is formed on the silicon film 4 .
  • the nitride film functions as a barrier against metal.
  • the nitride film has a sufficient thickness (at least 0.5 mm) for blocking the formation of silicide. Too thick a nitride film constitutes a trap/detrap site, which affects a charge holding characteristic.
  • the thickness of the nitride film is preferably at most 3 nm.
  • the inter-gate-film insulating film 5 has the stacked structure comprising oxide film/nitride film/oxide film/nitride film and is called an ONON film.
  • a process of forming an ONON film includes a step for forming an insulating film having a stacked structure of oxide film/nitride film/oxide film which is called an ONO film, and a step of forming a nitride film on the ONO film. These steps are carried out by LPCVD process.
  • the inter-gate-film insulating film 5 may be an SiO film whose uppermost layer includes Si, O and N, or an SiON film.
  • the uppermost layer of the inter-gate-film insulating film may include at least bond of N and Si. The uppermost layer may include further bond of N, Si and O.
  • a silicon film 6 doped with phosphorous as impurity is formed on the inter-gate-electrode insulating film 5 by LPCVD process.
  • the silicon film 6 is amorphous.
  • the amorphous silicon film 6 is used because it can be converted into silicide more easily than polycrystalline silicon films.
  • the silicon film 6 has a thickness of, for example, 125 nm.
  • the surface of the nitride film located in the uppermost layer of the inter-gate-electrode insulating film 5 may be slightly oxidized but is preferably not oxidized. To achieve this, the inter-gate-electrode insulating film 5 and silicon film 6 are consecutively formed in the same chamber.
  • a silicon nitride film 7 is formed on the silicon film 6 by LPCVD process.
  • a resist pattern 8 is formed on the silicon nitride film 7 .
  • the pattern of the resist pattern 8 is transferred to the silicon nitride film 7 by etching the silicon nitride film 7 .
  • the silicon nitride film 7 is etched by using, for example, an RIE (Reactive Ion Etching) process with using the resist pattern 8 as a mask.
  • the resist pattern 8 is removed, and the silicon film 6 , inter-gate-electrode insulating film 5 , silicon film 4 , and oxynitride film 3 are etched in a vertical direction using the silicon nitride film 7 as a mask. These films 6 to 3 are etched by, for example, RIE process.
  • the post-oxidation forms a post-oxidized film 9 on the opened surface of silicon substrate 1 , and sidewalls of silicon films 4 and 6 .
  • the source/drain areas 10 are formed by implanting ions into a surface of the silicon substrate 1 by ion implantation process, and then activating the implanted ions by thermal annealing. Shallow diffusion areas called extensions are also often formed. However, it is omitted for simplification.
  • the area between the cells is filled with an insulating layer 11 , and then the insulating layer upper than top surface of the silicon nitride film 7 is planarized.
  • a stacked film of a thermal oxide film, a silicon nitride film, and a BPSG film is used as the insulating film 11 .
  • the thermal oxide film, the silicon nitride film, and the BPSG film are sequentially formed so as to fill the area between the cells, thereafter, the entire surface is planarized by CMP (Chemical Mechanical Polishing) process.
  • CMP Chemical Mechanical Polishing
  • the silicon nitride film 7 is removed by etching.
  • the insulating film 11 has a higher etching rate than the silicon nitride film 7 .
  • a Co (cobalt) film 12 is deposited all over the surface by sputter process so as to fill a recess formed by removing the silicon nitride film 7 .
  • the Co film 12 has a thickness of, for example, 26 mm.
  • the Co film 12 and silicon film 6 are reacted with each other by heat treatment, thereby the silicon film 6 is completely converted into a Co silicide film 13 .
  • the Co silicide film is substantially silicidized down to the interface of the inter-gate-electrode insulating film 5 .
  • the CO silicide film 13 is used as the CG electrode.
  • the unreacted Co film 12 is removed. Thereafter, the NAND flash memory is completed through a well-known process.
  • the NAND flash memory of the present embodiment comprises the silicon substrate 1 , the oxynitride film 3 provided on the silicon substrate 1 and serving as the tunnel insulating film, the silicon film 4 provided on the oxynitride film 3 and serving as the FG electrode, the inter-gate-electrode insulating film 5 provided on the silicon film 4 and having an nitride film as the uppermost layer, and the Co silicide film 13 provided on the inter-gate-electrode film 5 and serving as the single-layer control gate electrode comprising metal silicide.
  • the formation of the Co silicide film 13 stops at the nitride film of the uppermost layer of the inter-gate-electrode insulating film 5 , therefore, the whole of the silicon film 6 is silicidized with high controllability. Thereby, the silicide film thickness is uniformed.
  • the nitride film is the uppermost layer of the inter-gate-electrode insulating film, spikes and diffusion of Co are suppressed. Thereby, the degradation of the inter-gate-electrode insulating film 5 and oxynitride film (tunnel oxide film) 3 are suppressed.
  • the height (aspect) of the CG electrode is reduced compared with the CG electrode comprising the silicon/metal silicide structure.
  • barrier height between the CG electrode and the inter-gate-electrode insulating film increases compared with the CG electrode comprising the silicon/metal silicide structure.
  • the ONON film is used as the inter-gate-electrode insulating film in the present embodiment
  • the inter-gate-electrode insulating film may be any insulating film comprising a single layer or multiple layers including at least one of an oxide film, a nitride film, an oxynitride film, a high dielectric metal oxide film, a high dielectric metal nitride film, and a high dielectric metal oxynitride film and having a nitride film as an uppermost layer.
  • An example of the inter-gate-electrode film is an ONON film.
  • the high dielectric metal oxide film, high dielectric metal nitride film, and high dielectric metal oxynitride film each have a larger dielectric constant than an SiO 2 film and include at least one of Al, Hf, Si, O, and N.
  • the Co silicide is used as metal silicide
  • the metal silicide may be any silicide including at least one refractory metal.
  • the refractory metal include, for example, Ni, Co, and Pt.
  • the present embodiment shows the method for manufacturing the NAND flash memory
  • the present embodiment exerts similar effects on MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) nonvolatile memories.
  • the MONOS comprises ONO film layers (oxide film-nitride film-oxide film) between the Si substrate and control electrode (gate electrode). While the nitride film in the center of the ONO film layers is an insulator, there are large numbers of traps located in that layer and it can capture and store charge. This layer can be made to function as a charge storing means by injecting and rejecting charge from these traps.
  • the control electrode on the ONO film in the MONOS nonvolatile memory is converted into a metal silicide electrode by the method of the present embodiment, the similar effect as the present embodiment is obtained.
  • Jpn. Pat. Appln. KOKAI Publication No. 2-188969 describes that a nitride film is interposed under the metal silicide layer to reduce leakage current.
  • this publication does not describe that the whole CG electrode is silicidized. Therefore, the lower interface of the metal silicide film have a high roughness, dispersion occurs in the thickness of the metal silicide films. These may be causes dispersion in resistance value of CG electrodes. Further, as spikes are formed along the grains of the polysilicon film and Co diffuses, the inter-gate-electrode insulating film or tunnel insulation is degraded.
  • FIG. 12 - FIG. 18 are sectional views showing a method for manufacturing a NAND flash memory in accordance with a second embodiment of the present invention.
  • the same reference numerals as FIG. 3 - FIG. 11 are given to designate portions corresponding to FIG. 3 - FIG. 11 , and the details are omitted.
  • the oxynitride film 3 , the polycrystalline silicon film 4 , and the inter-gate-electrode insulating film 5 are formed on a silicon substrate 1 .
  • a polycrystalline silicon film 6 ′ is formed on the inter-gate-electrode insulating film 5 .
  • an amorphous silicon film may be formed and then subjected to a thermal treatment or the like so as to be converted into a polycrystalline silicon film 6 ′.
  • the silicon film 6 ′ has a thickness of 40 nm.
  • the insulating film 15 is formed on the silicon 6 ′.
  • the insulating film 15 is an SiO film including Si, O, and N, an SiN film, or an SiON film.
  • the thickness of the insulating film 15 is at least 0.5 nm so as to enable the formation of silicide to be blocked.
  • the thickness of the insulating film is at most 2 nm so as not to hinder the conductivity of the polycrystalline silicon film and silicide film.
  • the insulating film 15 is formed by removing a native oxide film formed on a surface of the silicon film 6 ′ by dilute fluoric acid treatment beforehand, thereafter, wet treatment is applied to the surface of the silicon film 6 ′ using a solution added H 2 O 2 or O 3 .
  • insulating film 15 After the wet treatment, extremely small depth of surface of the insulating film 15 may be nitridized in a radial nitrogen atmosphere.
  • An amorphous silicon film 16 doped with phosphorous as impurity is formed on the insulating film 15 by LPCVD process.
  • the silicon film 16 has a thickness of, for example, 125 nm.
  • a silicon nitride film 7 is formed on the silicon film 16 by LPCVD process.
  • a resist pattern 8 is formed on the silicon nitride film 7 .
  • the pattern of the resist pattern 8 is transferred to the silicon nitride film 7 by etching the silicon nitride film 7 using the resist pattern 8 as a mask.
  • FIG. 15 [ FIG. 15 ]
  • the resist pattern 8 is removed, and the silicon film 16 , insulating film 15 , silicon film 6 ′, inter-gate-electrode insulating film 5 , silicon film 4 , and oxynitride film 3 are etched in a vertical direction using the silicon nitride film 7 as a mask. These films 3 to 6 ′, 15 , and 16 are etched by, for example, RIE process. Post-oxidation is executed to recover from damage caused by the etching, and then the post-oxidized film 9 is formed.
  • FIG. 16 [ FIG. 16 ]
  • the source/drain areas 10 are formed by implanting ions into the surface of the silicon substrate 1 by ion implantation process, and then activating the implanted ions by thermal annealing.
  • the shallow diffusion areas called extensions are also often formed. However, it is omitted for simplification.
  • the area between the cells is filled with the insulating film 11 , and then, the entire surface is planarized.
  • the silicon nitride film 7 is removed by etching, a Co film 12 having thickness, for example, 26 nm is deposited all over the surface by sputter process, thereafter, the Co film and silicon film 6 are reacted with each other by heat treatment, thereby the silicon film 16 is completely convert into a Co silicide film 17 .
  • the CO silicide film 17 , insulating film 15 and silicon film 16 are used as the CG electrode.
  • the CG electrode includes the insulating film 15 , which does not hinder the electrode from functioning properly because of its thickness set as described above.
  • the insulating film 11 has a higher etching rate than the silicon nitride film 7 , when the silicon nitride film 7 is etched, the insulating film 11 is also etched, the height of the insulating film 11 is lowered. Thereafter, a NAND flash memory is completed through a well-known process.
  • the NAND flash memory of the present embodiment comprises the silicon substrate 1 (semiconductor substrate), the oxynitride film 3 (first insulating film) provided on the silicon substrate 1 and serving as the tunnel insulating film, the polycrystalline silicon film 4 (charge storage layer) provided on the oxynitride layer 3 and serving as the FG electrode, the inter-gate-electrode insulating film 5 (second insulating film) provided on the silicon film 4 , and a multilayer control gate electrode provided on the inter-gate-electrode insulating film 5 and including the silicon film 6 ′ (semiconductor film) provided on the inter-gate-electrode insulating film 5 , the insulating film 15 (third insulating film) provided on the silicon film 6 ′ and including the nitride film as the uppermost layer, and the Co silicide film 17 (metal silicide film) provided on the insulating layer 15 .
  • the formation of the Co silicide film 17 stops at the insulating film 15 , therefore, the whole of the silicon film 16 is silicidized with high controllability. Thereby, the silicide film thickness is uniformed. In addition, as the spikes and the diffusion of Co are suppressed, the degradation of the inter-gate-electrode insulating film 5 and oxynitride film (tunnel oxide film) 3 are suppressed.
  • the Co silicide is used as metal silicide
  • the metal silicide may be any silicide including at least one refractory metal.
  • the refractory metal include, for example, Ni, Co, and Pt.
  • the present embodiment shows the method for manufacturing the NAND flash memory, the present embodiment exerts similar effects on MONOS nonvolatile memories. That is, the whole of the control electrode on an ONO film in a MONOS nonvolatile memory may be converted into an electrode of silicon/insulator/metal silicide structure by the method of the present embodiment.

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