US20070132080A1 - Semiconductor chip mounted interposer, semiconductor device, semiconductor chip interposer fabrication method, bare chip mounted interposer, and interposer sheet - Google Patents

Semiconductor chip mounted interposer, semiconductor device, semiconductor chip interposer fabrication method, bare chip mounted interposer, and interposer sheet Download PDF

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Publication number
US20070132080A1
US20070132080A1 US10/595,424 US59542403A US2007132080A1 US 20070132080 A1 US20070132080 A1 US 20070132080A1 US 59542403 A US59542403 A US 59542403A US 2007132080 A1 US2007132080 A1 US 2007132080A1
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United States
Prior art keywords
terminals
interposer
semiconductor chip
testing
semiconductor
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US10/595,424
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English (en)
Inventor
Moriyoshi Nakashima
Kazuo Kobayashi
Natsuo Ajika
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Genusion Inc
Original Assignee
Genusion Inc
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Filing date
Publication date
Application filed by Genusion Inc filed Critical Genusion Inc
Assigned to GENUSION INC. reassignment GENUSION INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AJIKA, NATSUO, KOBAYASHI, KAZUO, NAKASHIMA, MORIYOSHI
Publication of US20070132080A1 publication Critical patent/US20070132080A1/en
Priority to US12/235,734 priority Critical patent/US7723835B2/en
Abandoned legal-status Critical Current

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Definitions

  • the present invention relates to a semiconductor device package structure and packaging method.
  • SIP System in Package
  • a semiconductor chip 30 is mounted on a package substrate 10
  • another semiconductor chip 40 is further mounted on this semiconductor chip 30
  • wire bonding is executed with wire W between these semiconductor chips 30 and 40 and the package substrate 10 .
  • This technology is introduced in Nikkei Electronics 2002, 2-11 no. 815, p. 108, “Part One: If A Chip Can Not Be Used, There Is A Package”.
  • KGD known-Good-Die
  • a semiconductor device package structure includes:
  • a semiconductor chip mounted interposer configured by mounting a semiconductor chip to an interposer in which inside terminals to which terminals of a semiconductor chip to be mounted are connected, outside terminals to which terminals other than the terminals of the semiconductor chip are connected, and conductive wiring that makes an electrical connection between the outside terminals and the inside terminals are formed, and
  • the semiconductor chip mounted interposer is mounted along with another semiconductor chip to the base material, and the semiconductor chip mounted interposer and the other semiconductor chip are resin sealed along with the base material.
  • the semiconductor chip mounted interposer is mounted on a semiconductor chip that is mounted to the base material.
  • the semiconductor chip mounted interposer is configured by mounting semiconductor chips to both faces of the interposer, sandwiching the interposer.
  • the semiconductor chip mounted interposer is configured by disposing a plurality of semiconductor chips laminated on the interposer.
  • the semiconductor chip mounted interposer is configured by resin sealing the semiconductor chip mounted on the interposer along with the interposer, separate from resin sealing to the base material.
  • the interposer in a state before being mounted to the base material, is provided with terminals for connecting to a testing apparatus in order to perform predetermined reliability testing or operation testing, and the semiconductor chip mounted interposer, in a state before being mounted to the base material, is obtained by removing the terminals after the predetermined reliability testing or operation testing using the terminals has been performed.
  • a semiconductor chip mounted interposer is configured by mounting a semiconductor chip to an interposer in which inside terminals to which terminals of a semiconductor chip to be mounted are connected, outside terminals to which terminals other than the terminals of the semiconductor chip are connected, and conductive wiring that makes an electrical connection between the outside terminals and the inside terminals, are formed; the semiconductor chip mounted interposer is mounted to a substrate-like or frame-like base material; and the semiconductor chip mounted interposer is resin sealed together along with the base material.
  • terminals for connecting a testing apparatus are provided in the interposer, predetermined reliability testing or operation testing is performed by connecting the testing apparatus to the terminals, and after performing the reliability testing or operation testing the terminals are detached and the semiconductor chip mounted interposer is configured, and the semiconductor chip mounted interposer is mounted to the base material.
  • FIG. 1 is plan view that shows the package structure of a semiconductor device according to a first embodiment.
  • FIG. 2 is a cross-sectional view of the main portions of the semiconductor device according to the first embodiment.
  • FIG. 3 is a plan view that shows the structure of a semiconductor device according to a second embodiment.
  • FIG. 4 is a cross-sectional view that shows the structure of semiconductor device according to a third embodiment.
  • FIG. 5 is a cross-sectional view that shows the structure of semiconductor device according to a fourth embodiment.
  • FIG. 6 is a cross-sectional view that shows the structure of four semiconductor devices according to a fifth embodiment.
  • FIG. 7 shows a semiconductor chip mounted interposer testing method used for a semiconductor device according to a sixth embodiment.
  • FIG. 8 is a flowchart that shows the assembly process of an entire semiconductor device including an interposer test for the semiconductor device according to the sixth embodiment.
  • FIG. 9 is a cross-sectional view that shows the configuration of a conventional semiconductor device.
  • the semiconductor device package structure and packaging method which is a first embodiment, are described based on FIGS. 1 and 2 .
  • FIG. 1 is a plan view of the semiconductor device
  • FIG. 2 is a cross-sectional view of its main portions.
  • a semiconductor chip 30 is die-bonded on the upper face of a package substrate 10 .
  • a semiconductor chip 50 is mounted to an interposer 20 .
  • a semiconductor chip mounted interposer 60 is configured by the interposer 20 and the semiconductor chip 50 .
  • the semiconductor chip mounted interposer 60 is mounted by adhering its lower face (the lower face of the interposer 20 ) to the semiconductor chip 30 .
  • the semiconductor chip 40 is mounted to the top of the semiconductor chip 30 .
  • a plurality of terminals 11 and 11 ′ are formed arranged on the upper face of the package substrate 10 .
  • a plurality of soldering balls 12 are formed arranged on the lower face of the package substrate 10 . Between the terminals 11 and 11 ′ on the upper face and the soldering balls 12 on the lower face of the package substrate 10 , electricity is conducted via a wiring layer inside the package substrate 10 .
  • terminals arranged on the periphery of the upper face of the semiconductor chip 30 and the terminals 11 arranged on the upper face of the package substrate 10 are wire bonding executed by wires W 31 .
  • Terminals 51 are formed on the upper face of the semiconductor chip 50 .
  • Terminals 21 that correspond to “inside terminals” according to this invention are formed on the upper face of the interposer 20 , and wire bonding is executed between the terminals 21 and 51 with wires W 52 .
  • Terminals 22 that correspond to “outside terminals” according to this invention are formed on the upper face of the interposer 20 . Between these terminals 22 and the terminals 21 , electricity is conducted via a wiring layer inside the interposer 20 . Between the terminals 22 of the interposer 20 and the terminals 11 ′ of the package substrate 10 , wire bonding is executed with wires W 21 . By changing the positions of terminals on the interposer 20 in this manner, an electrical connection can be easily made with the semiconductor chips that are already present in their current state, without altering the position, pitch, signal arrangement, and the like of external connection terminals (pads) of the semiconductor chips.
  • the semiconductor chip mounted interposer 60 is treated like a KGD semiconductor chip, so that it can be mounted on a package substrate together with other semiconductor chips.
  • the semiconductor chip 40 is already designed such that it can be used as an SIP along with the semiconductor chip 30 , and so the semiconductor chip 40 does not use an interposer.
  • Wire bonding is executed with wires W 43 between terminals 41 on the upper face of the semiconductor chip 40 and terminals 31 formed on the upper face of the semiconductor chip 30 . Further, wire bonding is executed with wires W 41 between predetermined terminals 41 ′ of the semiconductor chip 40 and terminals 11 ′ on the package substrate.
  • FIG. 1 shows a state before resin sealing is performed in a portion above the package substrate 10 .
  • the semiconductor chips 30 and 40 , the semiconductor chip mounted interposer 60 and the wires that connect them are all resin sealed on the upper face of the package substrate 10 with a sealing resin 13 .
  • the semiconductor chip 30 is another semiconductor chip, whose size is, for example, 8.5 mm by 8.5 mm.
  • the semiconductor chip 40 is another semiconductor chip.
  • the semiconductor chip 50 on the interposer 20 is, for example, 32 M by 32 bit DRAM, whose size is, for example, 3.0 mm by 5.7 mm.
  • the terminals 51 are arranged on the short side of the semiconductor chip 50 , and so the terminals 21 of the interposer 20 are arranged along the short side of the semiconductor chip 50 .
  • the wire length of the wires W 52 can be short.
  • the terminals 22 are formed arranged at predetermined positions on the interposer 20 along one of the long sides of the semiconductor chip 50 near the terminals 11 ′ on the package substrate 10 . By positioning the interposer 20 near the terminals 11 ′ on the package substrate 10 , the wire length of the wires W 21 can be short.
  • FIG. 3 is a plan view of a semiconductor device according to a second embodiment.
  • the structure of the semiconductor chip mounted interposer 60 differs from the example shown in FIG. 1 .
  • two semiconductor chips 50 A and 50 B are mounted on the interposer 20 . These are each 16 M by 16 bit DRAM, and the terminals 51 are formed in the center of each semiconductor chip. Even when a plurality of semiconductor chips are used in this manner, by mounting them on a single interposer 20 , the semiconductor chip mounted interposer 60 can be treated as though it is a 32 M by 16 bit or 16 M by 32 bit DRAM.
  • the wire length of the wires W 52 between the terminals 51 of each semiconductor chip 50 A and 50 B and the terminals 21 on the interposer 20 can be short.
  • FIG. 4 is a cross-sectional view of the main portions of a semiconductor device according to a third embodiment.
  • the semiconductor chip mounted interposer 60 is configured by mounting the two semiconductor chips 50 A and 50 B on the upper face of the interposer 20 and executing wire bonding. Wiring that makes an electrical connection between the semiconductor chips 50 A and 50 B is provided in the interposer 20 .
  • the semiconductor chip 30 is bonded to the upper portion of the package substrate 10 , and the semiconductor chip mounted interposer 60 is mounted on the upper face of the semiconductor chip 30 .
  • the other semiconductor chip 40 is also mounted.
  • the periphery of the semiconductor chips 50 A and 50 B on the upper portion of the interposer 20 is resin sealed with a sealing resin 23 .
  • the semiconductor chips are resin sealed in a state as the semiconductor chip mounted interposer 60
  • handling is easy when adhering the semiconductor chip mounted interposer 60 to the semiconductor chip 30 .
  • the sealing resin 23 is ultimately covered by the sealing resin 13 above the package substrate 10 , and not exposed to the outside of the semiconductor device, so mechanical strength like that of the sealing resin 13 is not necessary, and it is preferable to use a simple method for resin sealing.
  • resin sealing is performed by a method of potting liquid resin, not by a method such as transfer molding.
  • wire bonding is executed with wires W 23 between the terminals provided on the upper face of the interposer 20 of the semiconductor chip mounted interposer 60 and the terminals provided on the top face of the semiconductor chip 30 .
  • wire bonding is executed with wires W 23 between the terminals provided on the upper face of the interposer 20 of the semiconductor chip mounted interposer 60 and the terminals provided on the top face of the semiconductor chip 30 .
  • FIG. 5 is a cross-sectional view of the main portion of a semiconductor device according to a fourth embodiment.
  • packaging was performed using the package substrate as the base material, but in the example shown in FIG. 5 , a plurality of semiconductor chips are packaged using a lead frame 9 as the base material.
  • the semiconductor chip 30 is die-bonded in the center portion of the lead frame 9 .
  • the semiconductor chip mounted interposer 60 configured from the semiconductor 50 and the interposer 20 , and the simple semiconductor chip 40 are each mounted to the upper portion of the semiconductor chip 30 . Wire bonding is executed with wires W 39 between the semiconductor chip 30 and the inner lead portion of the lead frame 9 .
  • Wire bonding is executed with wires W 49 between the semiconductor chip 40 and the inner lead of the lead frame 9 .
  • Wire bonding is executed with wires W 29 between the terminals of the interposer 20 and the inner lead of the lead frame 9 .
  • the plurality of semiconductor chips portion and the wire portion are resin sealed with the sealing resin 13 . In this way, a semiconductor with lead terminals, in which the outer leads of the lead frame 9 protrude outside of the sealing resin 13 , can be configured.
  • FIG. 6 shows the package structure and packaging method of terminal apparatuses according to a fifth embodiment.
  • Each terminal apparatus is shown in a cross-sectional view of their main portions.
  • the semiconductor chip 50 is flip-chip bonded to each of both faces of the interposer 20 .
  • the periphery of the semiconductor chips 50 is resin sealed with the sealing resin 23 , configuring the semiconductor chip mounted interposer 60 .
  • the semiconductor chip 30 is flip-chip bonded to the upper face of the package substrate 10 .
  • the semiconductor chip mounted interposer 60 is adhered to the upper portion of the semiconductor chip 30 , and wire bonding is executed with the wires W 21 between the terminals formed on the upper face of the interposer 20 and the terminals formed on the upper face of the package substrate 10 .
  • the soldering balls 12 are formed arranged on the lower face of the package substrate 10 .
  • the entire body including the semiconductor chips 30 and the semiconductor chip mounted interposer 60 is resin sealed above the package substrate 10 with the sealing resin 13 .
  • FIG. 6 shows only the outer shape of the sealing resin 13 .
  • example (B) in FIG. 6 two of the semiconductor chips 50 are disposed laminated in the interposer 20 .
  • wire bonding is executed between the semiconductor chips 50 and the interposer 20 .
  • the periphery of the semiconductor chips 50 is resin sealed with the sealing resin 23 .
  • the semiconductor chip 30 is flip-chip bonded to the upper face of the package substrate 10 , the semiconductor chip mounted interposer 60 is adhered to the upper portion of the semiconductor chip 30 , and wire bonding is executed with the wires W 21 between the interposer 20 and the package substrate 10 .
  • the configuration of the other portions in example (B) is the same as in the case of example (A).
  • the semiconductor chips 50 may also be flip-chip bonded to the interposer 20 .
  • another semiconductor chip may be flip-chip bonded on a semiconductor chip.
  • a first semiconductor chip mounted interposer 60 A formed by flip-chip bonding a semiconductor chip 50 A to an interposer 20 A
  • a semiconductor chip mounted interposer 60 B formed by flip-chip bonding a semiconductor chip SOB to an interposer 20 B
  • a semiconductor chip 30 is flip-chip bonded to the upper face of the package substrate 10 .
  • the semiconductor chip 30 is flip-chip bonded to the package substrate 10
  • the first semiconductor chip mounted interposer 60 A is adhered to the upper face of the semiconductor chip 30
  • the wire bonding is executed with wires W 21 A between the respective terminals of the upper face of the interposer 20 A and the package substrate 10 .
  • an adhesive sheet 70 is placed on the upper face of the semiconductor chip mounted interposer 60 A (the upper face of the semiconductor chip 50 A) and the second semiconductor chip mounted interposer 60 B is adhered fixed to the first semiconductor chip mounted interposer 60 A.
  • the adhesive sheet 70 may also be provided in advance on the lower face of the interposer 20 B of the second semiconductor chip mounted interposer 60 B.
  • wire bonding is executed with wires W 21 B between the terminals on the upper face of the interposer 20 B and the terminals on the upper face of the package substrate 10 .
  • resin sealing is performed in a portion above the package substrate 10 with the sealing resin 13 .
  • the two semiconductor chip mounted interposers 60 A and 60 B are arranged horizontally relative to the package substrate 10 .
  • the semiconductor chip mounted interposers 60 A and 60 B are configured by flip-chip mounting the semiconductor chips 50 A and 50 B to the upper face of the interposers 20 A and 20 B, respectively.
  • Semiconductor chips 9 A and 9 B are each flip-chip mounted to the upper face of the package substrate 10 .
  • the semiconductor chip mounted interposers 60 A and 60 B are adhered to the upper face of the semiconductor chips 9 A and 9 B. Wire bonding is executed with the wires W 21 between the terminals on the upper face of the interposers 20 A and 20 B and the terminals of the package substrate 10 .
  • example (D) The configuration of the other portions in example (D) is the same as in the case of examples (A) to (C).
  • the interposer 20 and the package substrate 10 were connected with wire, but a configuration may also be adopted in which outside terminals are arranged on the periphery of the interposer, and are joined both electrically and mechanically to terminals on the package substrate by pressing against them.
  • a configuration may also be adopted in which soldering bumps are formed as outside terminals on the joining face of the interposer (the face facing the package substrate and the like), and the soldering bumps are joined to terminals on the package substrate or terminals on the semiconductor chip on which the package substrate is mounted.
  • FIG. 7 shows a “pre-detachment interposer” 200 , in a state in which reliability and operation testing for a plurality of semiconductor chip mounted interposers is performed.
  • (A) shows an enlarged view of a test interposer unit 20 ′ when testing is performed, which is one unit of the pre-detachment interposer 200 .
  • the semiconductor chip 50 is mounted to the test interposer unit 20 ′, and wire bonding is executed with the wires W 52 between the terminals 51 of the semiconductor chip 50 and the terminals 21 of the interposer.
  • Testing terminals 25 are formed on the interposer with a larger pitch than the arranged pitch of the terminals 21 , and the testing terminals 25 and the terminals 21 are joined by wiring 24 .
  • the area shown by the double-dotted broken line in FIG. 2 is the region that becomes an interposer 20 after detachment, and after detaching this region it is used as a semiconductor chip mounted interposer.
  • the outside terminals (the terminals corresponding to the terminals 22 in FIG. 1 ) are omitted in FIG. 7 .
  • a testing apparatus is connected to each testing terminal 25 , and various reliability and operation testing is performed. For example, screening such as the high-temperature continuous operation testing (burn-in) described above is performed. Then, good units of semiconductor chip mounted interposers configured from a semiconductor chip 50 and an interposer 20 are selected.
  • a portion of the wiring 24 that extends from the terminals 21 to the testing terminals 25 (the portion of the wiring 24 shown by P in FIG. 7 ), remains in the interposer 20 .
  • the portion of the wiring 24 that remains in the interposer 20 is not shown for the sake of clarity of the figures.
  • FIG. 8 is a flowchart that shows the assembly process of an entire semiconductor device including the above interposer test.
  • an interposer is tested with a semiconductor chip that will be mounted to the interposer in a wafer state (S 11 ).
  • the back face of the wafer is polished and thinned to a predetermined thickness (S 12 ), and separated into individual semiconductor chips 50 by wafer dicing (S 13 ).
  • S 12 a predetermined thickness
  • S 13 wafer dicing
  • those deemed to be good are mounted on an interposer 20 (S 14 ).
  • the semiconductor chip portion is resin sealed as necessary (S 15 ).
  • the reliability and operation testing described above is performed, and the respective semiconductor chips are judged to be good or not (S 16 ).
  • each interposer 20 region is detached (S 17 ).
  • first testing is performed with a semiconductor chip that will be mounted to the package substrate 10 in a wafer state (S 21 ). Afterwards, wafer polishing and dicing are performed (S 22 and S 23 ), and each semiconductor chip 30 is mounted on a package substrate 10 (S 24 ). Afterwards, the semiconductor chip mounted interposer 60 , which is KGD, is mounted (S 25 ). Next the portion above the package substrate 10 is resin sealed, and detached into individual package substrates (S 26 ). Then various reliability and operation testing as performed for the interposers described above is performed for each semiconductor device (S 27 ). In this manner good semiconductor device units are obtained. A configuration may also be adopted in which instead of performing above Step S 26 , testing is performed for a plurality of semiconductor devices before detaching the package substrate, afterward resin sealing is performed, and then detachment as package substrates (S 26 ′).
  • Examples were described in which various connections were made between semiconductor chips, between a package substrate and interposer, between a semiconductor chip and package substrate, and between a semiconductor chip and interposer by wire bonding or a flip-chip connection, but a configuration may also be adopted in which all or a part of these portions are connected using a wiring sheet or the like in which wiring is executed on a flexible sheet. That is, a configuration may be adopted in which a plurality of wires are formed in sheets, both ends of which are made terminals, and those terminals are connected to counterpart terminals with which they should be connected.
  • the terminals on one side of a wiring sheet may be connected to the terminals of the interposer, and the terminals on the other side of the wiring sheet connected to the terminals of the package substrate.
  • a semiconductor chip mounted interposer configured by mounting a semiconductor chip to an interposer in which inside terminals to which the terminals of a semiconductor chip to be mounted are connected, outside terminals to which terminals other than the terminals of the semiconductor chip are connected, and conductor wiring that makes an electrical connection between the outside terminals and the inside terminals are formed, is provided, and the semiconductor chip mounted interposer is mounted along with another semiconductor chip to the base material, and so this semiconductor chip mounted interposer can be used as one of a plurality of semiconductor chips that configure a conventional SIP, for example.
  • the entire semiconductor device can be made thinner due to mounting the semiconductor chip mounted interposer on a semiconductor chip on the base material.
  • the semiconductor chip mounted interposer by configuring the semiconductor chip mounted interposer with a plurality of semiconductor chips disposed laminated on the interposer, it is possible to package more semiconductor chips in a single package without increasing the mounting area of the semiconductor chip mounted interposer relative to the base material.
  • terminals for connecting to a testing apparatus in order to perform predetermined reliability testing or operation testing are provided, and by detaching the terminals from the semiconductor chip mounted interposer after predetermined reliability and operation testing is performed using the terminals in a state before the semiconductor chip mounted interposer is mounted to the base material, it is possible to treat the semiconductor chip mounted interposer as a device that is the same as a semiconductor chip for which KGD is guaranteed.
US10/595,424 2003-10-20 2003-12-15 Semiconductor chip mounted interposer, semiconductor device, semiconductor chip interposer fabrication method, bare chip mounted interposer, and interposer sheet Abandoned US20070132080A1 (en)

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AU2003289336A1 (en) 2005-05-05
US20090065922A1 (en) 2009-03-12

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