US20070023800A1 - Semiconductor imaging device and fabrication process thereof - Google Patents

Semiconductor imaging device and fabrication process thereof Download PDF

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Publication number
US20070023800A1
US20070023800A1 US11/250,345 US25034505A US2007023800A1 US 20070023800 A1 US20070023800 A1 US 20070023800A1 US 25034505 A US25034505 A US 25034505A US 2007023800 A1 US2007023800 A1 US 2007023800A1
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region
gate electrode
conductivity type
channel region
diffusion region
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Narumi Ohkawa
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to US12/292,234 priority Critical patent/US7846758B2/en
Priority to US12/917,554 priority patent/US8008106B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding

Definitions

  • the present invention generally relates to semiconductor devices and more particularly to a semiconductor photodetection device constituting a CMOS imaging apparatus.
  • CMOS imaging apparatuses are used extensively in cellular phones with camera, digital still cameras, and the like.
  • a CMOS imaging apparatus has an advantageous feature over a CCD imaging apparatus in that the construction thereof is simple and can be produced with low cost.
  • FIG. 1 shows the construction of such a CMOS imaging apparatus 100 .
  • the CMOS imaging apparatus 100 includes a photodetection region 101 A in which a large number of CMOS pixel elements 10 are arranged in rows and columns, wherein a row selection circuit 101 B and a signal reading circuit 101 C are provided so as to cooperate with the CMOS pixel elements 10 in the photodetection region 101 A.
  • the row selection circuit 101 B selects a transfer control line TG, a reset control line RST and a selection control line SEL of a desired CMOS pixel element 10
  • the signal reading circuit 101 C supplies a reset voltage to the reset voltage line VR and reads out the signal voltage from the pixel, which is output to the signal reading line SIG.
  • FIG. 2 shows the construction of the CMOS device 10 for one pixel used in the CMOS imaging apparatus 100 of FIG. 1 .
  • a photodiode 10 D is connected to a power supply terminal 10 A connected to the reset voltage line VR and supplied with a reset voltage, wherein the photodiode 10 D is connected to the power supply terminal 10 A in a reverse bias state via a reset transistor 10 B controlled by a reset signal on the reset control line RST and a transfer gate transistor 10 C controlled by a transfer control signal on the transfer control line TG.
  • the photoelectrons formed by optical irradiation in the photodiode 10 D are accumulated in a floating diffusion region FD forming an intermediate node between the reset transistor 10 B and the transfer gate transistor 10 C.
  • the photoelectrons are converted to voltage in the floating diffusion region FD.
  • a voltage signal thus formed in the floating diffusion region FD in response to the photoelectrons from the photodiode 10 D is taken over by a reading transistor 10 F driven by a supply voltage from the power supply terminal 10 A, wherein the reading transistor 10 F forms a source follower circuit and supplies an output signal to the signal line SIG via a select transistor 10 S connected in series to the reading transistor 10 F.
  • the select transistor 10 S is controlled by a selection control signal on the selection control line SEL and the output of the read transistor 10 F is obtained on the signal line SIG in response to activation of the select transistor 10 S via the selection control signal on the selection control line SEL.
  • FIG. 3 is a diagram explaining the operation of the CMOS pixel element 10 of FIG. 2 .
  • the selection control signal on the selection control line SEL rises first, and a row of CMOS pixel elements including the desired CMOS pixel element is selected as a result of conduction of the select transistor 10 S.
  • the reset signal on the reset control line RST goes high, causing conduction of the reset transistor 10 B.
  • the floating diffusion region FD is charged to a initial state (resetting).
  • the transfer gate transistor 10 C is turned off.
  • the potential of the floating diffusion region FD rises at the same time, and the effect of this rising potential of the floating diffusion region FD is transferred also to the signal line SIG via the reading transistor 10 F and the select transistor 10 S in the conduction state, while it should be noted that this rising of the signal line SIG is not used for reading of the signal.
  • the reset signal goes low, and the potential of the floating diffusion region FD is read out to the signal line SIG by the reading transistor 10 F while maintaining the transfer gate transistor 10 C in the turned off state. With this, reading of noise level is achieved.
  • the transfer control signal on the transfer control line TG goes high and the electric charges accumulated inside the photodiode 10 D are transferred to the floating diffusion region 10 F via the transfer gate transistor 10 C.
  • the transfer control signal goes low, the potential of the floating diffusion region 10 F is read out by the reading transistor 10 F and is output to the signal line SIG via the select transistor 10 S.
  • Patent Reference 1 Japanese Laid-Open Patent Application 11-274450 official gazette
  • Patent Reference 2 Japanese Laid-Open Patent Application 2001-15727 official gazette
  • Patent Reference 3 Japanese Laid-Open Patent Application 11-284166 official gazette
  • FIGS. 4A and 4B are diagrams showing the transistor 10 C and the photodiode 10 D in the circuit of the FIG. 2 respectively in the cross-sectional view and plan view.
  • FIG. 4A and 4B correspond to the construction of Patent Reference 1 wherein the transistor 10 C is formed on a p-type active region 21 defined on a silicon substrate 21 by an STI device isolation region 21 I, and a polysilicon gate electrode 23 is formed via a gate insulation film 22 of high quality insulation film typically of a thermal oxide film in correspondence to a p-type channel region 21 P.
  • n-type diffusion region 21 D that constitutes the photodiode 10 D in the silicon substrate 21 at one side of the gate electrode 23 , and a diffusion region 21 N of n + -type constituting the floating diffusion region FD is formed at the other side of the gate electrode 23 .
  • the diffusion region 21 D undergoes depletion and photoelectrons are formed in response to irradiation of incident light.
  • the photoelectrons thus formed are then caused to flow to the diffusion region 21 N at the time of electric charge transfer operational mode via the channel region 21 P of the transfer gate transistor 10 C formed right underneath the gate electrode 23 as shown by an arrow in FIG. 4A and cause a change of potential therein.
  • FIGS. 4A and 4B there is formed a shielding layer 21 P+ of a highly doped diffusion region of p + -type on the surface of the n-type diffusion region 21 D for avoiding leakage current caused in the diffusion region 21 D by the interface states at the surface of the silicon substrate.
  • the n-type diffusion region 21 D forms a buried diffusion region.
  • Patent Reference 1 discloses the technology of forming a p-type diffusion region 21 P ⁇ to the part of the p + -type shielding layer 21 P+ adjunct to the gate electrode 23 for reducing the potential barrier in this part as shown in FIG. 5 .
  • FIG. 5 those parts corresponding to the parts explained previously are designated by the same reference numerals.
  • Patent References 2 and 3 propose a construction of extending the n-type diffusion region 21 D to the part right underneath the gate electrode 23 as shown in FIG. 6 such that the photoelectrons can flow into the channel region 21 P right underneath the gate electrode 23 efficiently as shown in the drawing by an arrow. Thereby, it is attempted to improve the transfer efficiency of the photoelectrons to the floating diffusion region 21 N while effectively shielding the influence of the interface states at the surface of the silicon substrate 21 to the photoelectrons at the same time.
  • the n-type diffusion region 21 D of low potential and the p + -type diffusion region 21 P+ forming a potential barrier exist adjacent to the foregoing p-type channel region 21 P, and thus, the potential profile taken along the path of the photoelectrons is modified by the influence of these diffusion regions. As a result, there appears a complex potential distribution profile having a dip at the central part as shown in FIG. 7 .
  • the potential barrier formed in the channel region 21 P with a dip at the top part functions to collect the electrons, particularly the thermal electrons excited thermally at the interface between silicon substrate 21 and the gate oxide film 22 , wherein the electrons thus accumulated in the dip may run down the potential barrier and reach the n-type diffusion region 21 D of the photodiode or the floating diffusion region 21 N.
  • the electrons that have reached the floating diffusion region 21 N do not cause problem as they are annihilated by the reset operation of FIG. 3 . Further, the remaining effect thereof is compensated for by the noise reading step. However, the electrons that have reached the diffusion region 21 D of the photodiode are transferred to the floating diffusion region 21 N in the charge transfer step of FIG. 3 together with photoelectrons and form a dark current.
  • the present invention provides a semiconductor imaging device, comprising:
  • a gate electrode formed on said silicon substrate in correspondence to a channel region in said active region via a gate insulation film
  • a photodetection region formed of a diffusion region of a first conductivity type, said photodetection region being formed in said active region at a first side of said gate electrode such that a top part thereof is separated from a surface of said silicon substrate and such that an inner edge part invades underneath a channel region right underneath said gate electrode;
  • a shielding layer formed of a diffusion region of a second conductivity type, said shielding layer being formed in said active region at said surface of said silicon substrate at said first side of said gate electrode such that an inner edge part thereof is aligned with a sidewall surface of said gate electrode at said first side, said shielding layer being formed so as to cover a part of said photodetection region located at said first side of said gate electrode,;
  • a floating diffusion region formed of a diffusion region of said first conductivity type, said floating diffusion region being formed in said active region at a second side of said gate electrode;
  • said channel region comprising:
  • a first channel region part having said second conductivity type a first end of said channel region being formed adjacent to said shielding layer, another end of said channel region invading to a region right underneath said gate electrode and covering a part of said photodetection region invading underneath said channel region;
  • said first channel region part containing an impurity element of said second conductivity type with an impurity concentration level lower than an impurity concentration level in said shielding layer
  • said second channel region part containing said impurity element with a concentration level lower than said impurity concentration level of said first channel region part.
  • the present invention provides a semiconductor imaging device, comprising:
  • a gate electrode formed on said silicon substrate in correspondence to a channel region in said active region via a gate insulation film
  • a shielding layer formed of a diffusion region of a second conductivity type, said shielding layer being formed in said active region at said surface of said silicon substrate at said first side of said gate electrode such that an inner edge part thereof is aligned with a sidewall surface of said gate electrode at said first side, said shielding layer being formed so as to cover a part of said photodetection region located at said first side of said gate electrode,;
  • a floating diffusion region formed of a diffusion region of said first conductivity type, said floating diffusion region being formed in said active region at a second side of said gate electrode;
  • said channel region comprising:
  • a first channel region part having said second conductivity type a first end of said channel region being formed adjacent to said shielding layer, another end of said channel region invading to a region right underneath said gate electrode and covering a part of said photodetection region invading underneath said channel region;
  • said first channel region part containing an impurity element of said second conductivity type with an impurity concentration level lower than an impurity concentration level in said shielding layer
  • said first channel region part and said second channel region part containing an impurity element of said first conductivity type and an impurity element of said second conductivity type, such that a carrier concentration level of said second conductivity type is larger in said first channel region than in said second channel region.
  • a method of fabricating a semiconductor imaging device comprising the steps of:
  • first diffusion region of a first conductivity type at a surface of a silicon substrate by introducing an impurity element of said first conductivity type into an active region defined on said silicon substrate such that said first diffusion region is formed over an entire surface of said active region with a first depth and a first impurity concentration level;
  • a photodetection region of a second conductivity type underneath said first diffusion region by covering a first part of said first diffusion region by a first mask pattern and introducing an impurity element of a second conductivity type into said active region in overlapping relationship with said first diffusion region while using said first mask pattern as a mask, such that said impurity element of said second conductivity type is introduced to a second depth deeper than said first depth;
  • a shielding layer of a diffusion region of said first conductivity type at a surface of said second diffusion region by introducing an impurity element of said first conductivity element into said active region while using said gate electrode and a second mask pattern covering a part of said active region at a side opposite to said photodetection region with regard to said gate electrode as a mask, such that said shielding layer contains said impurity element of said first conductivity type with a third impurity concentration level larger than said second impurity concentration level;
  • the present invention provides a method of fabricating a semiconductor imaging device, comprising the steps of:
  • a first diffusion region of a first conductivity type in an active region defined on a silicon substrate by a device isolation region, by introducing thereto an impurity element of a first conductivity type with a first depth deeper than a bottom edge of said device isolation region;
  • a shielding layer having said second conductivity type and a carrier concentration level higher than said first part in said active region, by covering a part of said active region opposite to said photodetection region with respect to said gate electrode by a third mask pattern, and by introducing a second impurity element to said active region in overlapping relationship with said second diffusion region while using said gate electrode and said third mask pattern as a mask;
  • a semiconductor imaging device in which a photodiode and a transfer gate transistor are integrated on a silicon substrate and constituting a part of a CMOS imaging apparatus, to form a potential barrier inclined to a floating diffusion region in a channel region of the transfer gate transistor, by forming the diffusion region constituting the photodiode such that a tip end part thereof invades underneath the channel region right underneath the gate electrode of the transfer gate transistor and by forming the channel region such that a part of the channel region close to the photodiode has an increased impurity concentration level or increased carrier concentration level as compared with the part close to the floating diffusion region and functioning as the drain region of the transfer gate transistor.
  • the reading operational mode which follows the foregoing photoreception operational mode and conducted by turning on the transfer gate transistor such that the photoelectrons accumulated in the diffusion region of the photodiode are transferred to the floating diffusion region.
  • the S/N ratio of the semiconductor imaging device is improved.
  • the thermal electrons thus flowed into the floating diffusion region are removed in the resetting operational mode conducted in advance of the reading operational mode, and thus, detection of the optical signal is not influenced by such thermal electrons.
  • the photoelectrons formed by the photodiode are not affected by the surface states at the surface of the silicon substrate when the transfer gate transistor is turned on, and the photoelectrons are caused to flow to the floating diffusion region. Thereby occurrence of leakage current at the time of reading operational mode is suppressed.
  • the transfer gate transistor having such an inclined potential profile in the channel region, it is possible to facilitate discharging of the thermal electrons to the floating diffusion region in the photoreception operational mode of the photodiode in which the transfer gate transistor is turned off, by applying a slight positive voltage to the gate electrode of the transistor.
  • FIG. 1 is a diagram showing an overall construction of a semiconductor imaging device
  • FIG. 2 is a diagram showing the construction of a CMOS imaging apparatus used with the semiconductor imaging device of FIG. 1 ;
  • FIG. 3 is a diagram explaining the operation of the CMOS imaging device of FIG. 2 ;
  • FIGS. 4A and 4B are diagrams showing the construction of a conventional CMOS imaging apparatus
  • FIG. 5 is a diagram showing the construction of another conventional CMOS imaging apparatus
  • FIG. 6 is a diagram showing the construction of another conventional CMOS imaging apparatus
  • FIG. 7 is a diagram explaining the problems of the CMOS imaging apparatus of FIGS. 5 and 6 ;
  • FIG. 8 is a diagram showing the construction of a semiconductor imaging device according to a first embodiment of the present invention.
  • FIG. 9 is a diagram showing a potential distribution profile formed in the channel region of the transfer gate transistor of the semiconductor imaging device of FIG. 8 ;
  • FIGS. 10A-10E are diagrams showing the fabrication process of a semiconductor imaging device of FIG. 8 ;
  • FIGS. 11A and 11B are plan view diagrams showing the construction of the semiconductor imaging device of FIG. 8 ;
  • FIG. 12 is a diagram showing an example of driving the transfer gate transistor at the time of detecting operation of the semiconductor imaging device of FIG. 8 ;
  • FIGS. 13A and 13B are diagrams showing the fabrication process of a semiconductor imaging device according to a second embodiment of the present invention.
  • FIG. 14 is a diagram showing construction of a semiconductor imaging device according to a second embodiment of the present invention.
  • FIGS. 15A and 15B are diagrams showing the fabrication process of semiconductor imaging device according to a third embodiment of the present invention.
  • FIGS. 16A-16D are diagrams showing the fabrication process of a semiconductor imaging device according to a fourth embodiment of the present invention.
  • FIGS. 17A and 17B are diagrams showing an example of driving of the transfer gate transistor at the time of detecting operation of a semiconductor imaging device according to a fifth embodiment of the present invention.
  • FIG. 8 is a diagram showing a cross-sectional structure of a semiconductor imaging device 40 according to a first embodiment of the present invention, wherein the semiconductor imaging device 40 corresponds to the transistor 10 C and the photodiode 10 D of the CMOS imaging apparatus of the FIG. 2 .
  • the semiconductor imaging device 40 is formed in a p-type device region 41 A defined on a silicon substrate 41 by an STI device isolation structure 41 I, wherein there is formed a polysilicon gate electrode 43 on the silicon substrate 41 via a gate insulation film 42 typically of a thermal oxide film in correspondence to a channel region formed in the device region 41 A.
  • the active region 41 A there is formed a diffusion region 41 D of n-type at a first side of the gate electrode 43 as the photodetection region of the photodiode 10 D, and a p + -type diffusion region 41 P+ is formed on the surface part of the diffusion region 41 D as a shielding layer. Further, an n + -type diffusion region 41 N is formed in the active layer 41 A at an opposite side of the diffusion region 41 D with respect to the gate electrode 43 as the floating diffusion region FD.
  • a CVD oxide film 44 is formed on the silicon substrate 41 so as to cover the device region 41 A including the gate electrode 43 .
  • the n-type diffusion region 41 D is formed such that a tip end part thereof constituting the inner edge part invades to the region underneath the channel region, which is formed right underneath the gate electrode 43 , and thus, the photoelectrons formed in the diffusion region 41 D can flow to the floating diffusion region 41 N through the channel region, when the transistor is turned on, without passing through the shielding layer 41 P+forming a high potential barrier.
  • the present embodiment forms the channel region by a first p-type region 41 P 1 adjacent to the floating diffusion region 41 N and a second p-type region 41 P 2 adjacent to the shielding layer and sets the concentration level (P 2 ) of the p-type impurity element in the region 41 P 2 to be larger than the concentration level (P 1 ) of the p-type impurity element in the region 41 P 1 (P 2 >P 1 ) but smaller than the concentration level (P 3 ) of the p-type impurity element in the shielding layer 41 P+ (P 3 >P 2 >P 1 ).
  • the p-type region 41 P 2 is formed so as to cover the part of the n-type diffusion region 41 D that has invaded underneath the channel region.
  • thermal electrons in the conduction band of the Si crystal that forms the channel region and thermal electrons are formed at the interface between the silicon substrate 41 and the gate insulation film 22 during the photoreception operational mode of the imaging apparatus, such thermal electrons are discharged to the floating diffusion region 41 N immediately along the potential gradient, and there occurs no accumulation of thermal electrons in the channel region.
  • the transfer gate transistor 10 C is turned off for enabling accumulation of the photoelectrons in the diffusion region 41 D.
  • the thermal electrons formed in the channel region do not flow to the diffusion region 41 D and the problem of noise caused by the mechanism of electrons other than photoelectrons being accumulated in the diffusion region 41 D at the time of detecting operation does not take place.
  • a potential difference of 0.15V or more between the potential peak part A formed in the region 41 P 2 as shown in FIG. 9 and the flat potential part B in the region 41 P 1 also shown in FIG. 9 it becomes possible to discharge 99% or more of the thermal electrons formed in the channel region to the floating diffusion region 41 N, and it becomes possible to suppress collection of noise at the time of photoreception operational mode effectively.
  • the electric charge amount caused by thermal electrons and flowing into the diffusion region 41 D can be decreased by the factor of 1/40- 1/50.
  • the diffusion region 41 D is shielded effectively from the silicon substrate surface by means of the shielding layer 41 P+ of p + -type formed in alignment with the edge part of the gate electrode 43 . With this, the influence of the interface states existing at the interface between the silicon substrate 41 and the CVD oxide film 44 on the diffusion region 41 D is effectively shielded.
  • FIG. 10A there is formed a device region 41 A of p-type on the silicon substrate 41 by the device isolation structure 41 I, wherein, in the step of FIG. 10A , ion implantation process is conducted via a resist pattern R 1 formed on the silicon substrate 41 so as to expose the device region 41 A. Further, B + is injected while using the resist pattern R 1 as a mask with an angle of 7 degrees under the acceleration voltage of 10-30 keV with the dose of 0.5-2.0 ⁇ 10 12 cm ⁇ 2 . Thereby, there is formed a p-type diffusion region constituting the region 41 P 1 over the entire device region 41 A.
  • a resist pattern R 2 is formed on the silicon substrate 41 so as to expose the region where the diffusion region 41 D of the photodiode 10 D is to be formed, and ion implantation process of P + is conducted into the silicon substrate 41 while using the resist pattern R 2 as a mask, first under the acceleration voltage of 110-150 keV with the dose of 1-3 ⁇ 10 12 cm ⁇ 2 and the angle of 7 degrees, next under the acceleration voltage of 180-220 keV with the dose of 1-3 ⁇ 10 12 cm ⁇ 2 and the angle of 7 degrees. With this, the n-type diffusion region 41 D is formed.
  • the same resist pattern R 2 is used for the mask and B + is introduced into the silicon substrate 41 by an ion implantation process conducted under the acceleration voltage of 10-30 keV with the dose of 1-3 ⁇ 10 12 cm ⁇ 2 and the angle of 7 degrees.
  • a p-type diffusion region forming the region 41 P 2 is formed on the surface part of the diffusion region 41 D with an impurity concentration level exceeding the impurity concentration level in the diffusion region 41 P 1 .
  • a thermal oxide film is formed on the silicon substrate 41 by a thermal oxidation processing conducted at 800° C. with the thickness of 4-10 nm as the gate insulation film 42 , and a polysilicon film is formed thereon by a CVD process with the thickness of about 180 nm. Further, by patterning the polysilicon film, the polysilicon gate electrode 43 and the gate insulation film 42 are formed so as to bridge across the diffusion region 41 D and the diffusion region with a gate length of 0.4-0.8 ⁇ m. Thereby, it should be noted that the overlap length L of the gate electrode 43 and the n-type diffusion region 41 D is set to 0.15-0.40 ⁇ m, for example.
  • the shielding layer 41 P+ is formed in alignment to the sidewall surface of the gate electrode 43 .
  • the shielding layer 41 P+ thus formed extends from the sidewall surface of the gate electrode 43 to the device isolation structure 41 I at the opposite side, wherein it should be noted that the shielding layer 41 P+ contains B thus introduced with a substantially uniform concentration level.
  • a resist pattern R 4 exposing the part of the device region 41 A at the side opposite to the shielding layer 41 P+ with respect to the gate electrode 43 , and ion implantation process of P+ is conducted into the silicon substrate 41 under the acceleration voltage of B 10 -30 keV with the dose of 2-50 ⁇ 10 12 cm ⁇ 2 and the angle of 0 degree, while using the resist pattern R 4 as a mask.
  • n + -type diffusion region 41 N in alignment with the gate electrode 43 as the floating diffusion region FD.
  • the semiconductor imaging device 40 of FIG. 8 is obtained.
  • FIG. 11A shows the silicon substrate 41 of the state of FIG. 10B in a plan view.
  • the device region 41 A is formed inside the STI device isolation structure 41 I and that the diffusion region 41 D of n-type is formed in the device region 41 A with an offset from the device isolation structure 41 I by at least 0.2 ⁇ m. Further, it can be seen that the p-type diffusion region 41 P 2 is formed in alignment with the n-type diffusion region 41 D.
  • FIG. 11B shows the silicon substrate 41 of the state of FIG. 10E in a plan view.
  • the active region 41 A is formed with the shielding layer 41 P+ at the side of the n-type diffusion region 41 D with respect to the gate electrode 43 in alignment to the gate electrode 43 and that the inner edge part of the n-type diffusion region 41 D invades to the region right underneath the gate electrode 43 .
  • n-type diffusion region 41 N is formed in the active region 41 A at the side opposite to the shielding layer 41 P+ with respect to the gate electrode 43 in alignment with the gate electrode 43 .
  • FIG. 12 shows the potential formed in the channel region at the time of photoreception operational mode of the semiconductor imaging device of FIG. 8 .
  • the gate voltage of the transfer gate transistor 10 C is set to 0V during the photoreception operational mode of the photodiode 10 D in a CMOS imaging apparatus.
  • a potential gradient in the channel region of the transistor 10 C with the present embodiment there is induced a potential gradient in the channel region of the transistor 10 C with the present embodiment, and flow of thermal electrons excited in the channel region to the photodiode 10 D is blocked and flow to the floating diffusion region 41 N is facilitated. This state is shown in FIG. 12 by a broken line.
  • the continuous line of FIG. 12 shows the case in which the gate voltage applied to the gate electrode 43 is set to +0.3-0.7V during the photoreception operational mode.
  • the potential of the electrons flowing through the path shown in FIG. 8 by the arrow undergoes a significant effect with the foregoing small gate voltage particularly in the part where the electrons are transported at a shallow depth and hence along the path near the gate electrode 43 .
  • the potential level of the electrons is lowered significantly as shown in FIG. 12 by an arrow A.
  • the influence of the gate electrode is small and the potential of the electrons changes only by a small amount as shown in FIG. 12 by an arrow B.
  • FIGS. 13A and 13B are diagrams showing a modification of the ion implantation process of FIG. 10B according to a second embodiment of the present invention while FIG. 14 is a diagram showing a semiconductor imaging device 40 A fabricated according to the process of FIGS. 13A and 13B .
  • the present embodiment sets the thickness of the resist pattern R 2 formed on the silicon substrate 41 at the time of forming the p-type diffusion region 41 P 2 in the step of FIG. 10B to be about 1 ⁇ m, and ion implantation of B+ is conducted to the surface of the n-type diffusion region 41 D with the angle of 7 degrees in at least two directions.
  • the dose of ion implantation is reduced in the shadow part of the resist pattern R 2 as shown in FIG. 13B , and there is formed a region 41 pm of intermediate impurity concentration level between the p-type region 41 P 2 and the p-type diffusion region 41 P 1 .
  • the intermediate region 41 Pm between the regions 41 P 2 and 41 P 1 is modified such that the flat part is reduced. Thereby, discharging of the thermal electrons to the floating diffusion region is facilitated further.
  • the shielding layer 41 P+ is formed only on the surface part of the diffusion regions 41 P 1 and 41 P 2 , while the shielding layer 41 P can effectively shield the effect of the surface states on the silicon substrate surface to the photoelectrons excited in the diffusion region 41 D also with such a construction.
  • FIGS. 15A and 15B show the fabrication process of a semiconductor imaging device 40 B according to a third embodiment of the present invention, wherein those parts corresponding to the parts explained previously are designated by the same reference numerals and the description thereof will be omitted.
  • FIG. 15A shows a process corresponding to the process of FIG. 10B except that the p-type diffusion region 41 P 2 is formed at a shallower level than the p-type diffusion region 41 P 1 .
  • ion implantation process of B + is conducted under the acceleration voltage of 8-15 keV with the dose of 0.5-3.0 ⁇ 10 12 cm 2 and the angle of 7 degrees, while using the resist pattern R 2 as a mask, in overlapping relationship with the n-type diffusion regions 41 D.
  • the p-type region 41 P 2 forming the potential barrier in the channel region right underneath the gate electrode 43 is formed only at the surface part of the channel region in the structure obtained after the step of FIG. 10C as shown in FIG. 15B , and thus, it becomes possible to control the potential barrier by the gate voltage applied to the gate electrode 43 easily. Thereby, it becomes possible to improve the transfer efficiency of photoelectrons in the transfer operational mode for transferring the photoelectrons from the diffusion region to the floating diffusion region 41 N via the transfer gate transistor 10 C.
  • FIG. 15B it becomes possible to form the p-type diffusion region 41 P 1 with an increased depth as compared with the p-type diffusion region 41 P 2 , and it becomes possible to suppress the punch-through between the n-type diffusion region 41 D and the n-type diffusion region 41 N.
  • FIGS. 16A-16D show the fabrication process of a semiconductor imaging device 40 C according to a fourth embodiment of the present invention, wherein those parts corresponding to the parts explained previously are designated by the same reference numerals and the description thereof will be omitted.
  • a part of the active region 41 A in the silicon substrate 41 is introduced first with P + under the acceleration voltage of 110-150 keV with the dose of 1-3 ⁇ 10 22 cm ⁇ 2 and the angle of 7 degrees, next under the acceleration voltage of 18-220 keV with the dose of 0.5-1.5 ⁇ 10 12 cm ⁇ 2 and the angle of about 7 degrees, and further under the acceleration voltage of 300-600 keV with the dose of 0.5-1.5 ⁇ 10 12 cm ⁇ 2 , while using the resist pattern RA as a mask.
  • the n-type diffusion region 41 D is formed at a depth lower than the bottom edge of the device isolation structure 41 I, which has the depth of 350-400 nm.
  • B + is introduced by an ion implantation process while using the same resist pattern RA as a mask under the acceleration voltage of 10-30 keV with the dose of 2-5 ⁇ 10 12 cm ⁇ 2 and the angle of about 7 degrees.
  • the p-type diffusion region 41 P 2 is formed on the surface of the n-type diffusion region 41 D.
  • a resist pattern RB is formed such that a part of the active region 41 A in the vicinity of the device isolation structure 41 I, a part of the channel region of the transistor 10 C to be formed and the region where the floating diffusion region FN is to be formed are exposed and such that the resist pattern RB also covers the majority of the n-type diffusion region 41 D, and ion implantation of B + is conducted first under the acceleration voltage of 65 keV with the dose of 2-10 ⁇ 10 12 cm and the angle of about 7 degrees, next under the acceleration voltage of 100 keV with the dose of 1.5- ⁇ 10 12 cm and the angle of about 7 degrees, and further under the acceleration voltage of 140 keV with the dose of 1.5-5 ⁇ 10 12 cm ⁇ 2 and the acceleration voltage of 180 keV with the dose of 1-5 ⁇ 10 12 cm ⁇ 2 and the angle of about 7 degrees, while using the resist pattern RB as a mask.
  • the n-type conductivity type formed already for the diffusion region 41 D is in the step of FIG. 16A is cancelled out in the region along the device isolation structure 41 I, and there is formed a p-type well 41 PW in such a part with a depth of about 0.1 ⁇ m as measured from the bottom edge of the device isolation structure 41 I such that the bottom edge of the n-type diffusion region 41 D is not exposed to the bottom edge of the device isolation structure 41 I.
  • ion implantation of As + is conducted while using the same resist pattern RB as a mask under the acceleration voltage of 50-80 keV with the dose of 1-2 ⁇ 10 12 cm ⁇ 2 .
  • the p conductivity type formed as a result of ion implantation of B to the surface of the silicon substrate for formation of the well 41 PW and the diffusion region 41 P 2 is partly canceled out, and the p-type diffusion regions 41 P 1 and 41 P 1 ′ are formed with lower hole concentration level.
  • the polysilicon gate electrode 43 is formed on the silicon substrate 41 via the gate insulation film 42 in correspondence to the channel region of the transfer gate transistor to be formed in the device region 41 A so as to bridge across the boundary between the diffusion regions 41 P 2 and 41 P 1 .
  • a resist pattern RC so as to cover a part of the polysilicon gate electrode 43 and the surface of the silicon substrate 41 where the floating diffusion region FN is to be formed, and B + is introduced into the silicon substrate 41 under the acceleration voltage of 5-15 keV with the dose of 1-5 ⁇ 10 13 cm ⁇ 2 while using the resist pattern RC as a mask.
  • the shielding layer 41 P+ is formed on the surface of the n-type diffusion region 41 D.
  • a resist pattern RD so as to cover the device region 41 A for a part of the polysilicon gate electrode and the surface of the silicon substrate 41 formed with the shielding layer 41 P+, and ion implantation of P+ is conducted into the silicon substrate under the acceleration voltage of 10-30 keV and the dose of 2-5 ⁇ 10 13 cm ⁇ 2 with the angle of 0 degrees while using the resist pattern RD as a mask.
  • an n-type diffusion region 41 N is formed as the floating diffusion region FN.
  • the semiconductor imaging device 40 C of such a construction there is a large opening area forth resist pattern RA used with the step of FIG. 16 A, and thus, it becomes possible to use a thick resist pattern for the ion implantation mask RA.
  • a thick resist pattern for the ion implantation mask RA thereby, it becomes possible to form the n-type diffusion region 41 D constituting the photodiode 10 D to a depth exceeding the bottom edge of the device isolation structure 41 I by using large ion implantation energy.
  • the depletion layer extends deeply in the photoreception operational mode, and it becomes possible to collect the incoming photons with large detection volume. With this, the S/N ratio of the imaging device is improved further.
  • the p-type diffusion regions 41 P 1 and 41 P 2 contain B and As at the same time, and the difference of carrier concentration level leading to the potential gradient is caused by the difference of concentration level of B and As in each of these regions.
  • FIG. 17A shows a fifth embodiment of the present invention.
  • the present embodiment uses the semiconductor imaging device 40 of FIG. 8 explained before except that a negative voltage in the range of ⁇ 0.5-2V is applied to the gate electrode 43 in the photoreception operational mode as represented in the drawing.
  • the transfer gate transistor 10 C is an n-channel MOS transistor and the channel region is doped to p-type.
  • the semiconductor imaging device is identical to the one explained with reference to FIG. 6 , wherein it is possible to suppress occurrence of dark current caused by thermal electrons excited in the channel region by similarly applying a gate voltage of ⁇ 0.5- ⁇ 2V to the gate electrode 23 at the time of photoreception operational mode thereof so that thermal excitation of electrons is suppressed.

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US8008106B2 (en) 2011-08-30
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